Mind Readers

Matt WaldersenT.J. Strzelecki

Rick SchumanKrishna Jharjaria

What We’re Doing

The proposed project will be a mobile brain-computer interface.

Various computer applications will be presented to the user on a head mounted display system.

The user will be able to navigate between different applications presented on the heads up display through eye gestures detected by an electrooculogram (EOG).

The user will be able to select different applications by increasing their level of concentration measured by an electroencephalogram (EEG).

Project-Specific Success Criteria

1) An ability to encode/decode data packets from a NeuroSky EEG.

2) An ability for a user to select applications based on signals from a NueroSky EEG.

3) An ability for a user to navigate between different applications on a display using EOG signals.

4) An ability for the system to interactively train the user to effectively operate the device.

5) An ability to display a live video stream from an external camera module, and integrate applications into the video system.

System Block Diagram

Motherboard Constraint

Processor Speeds around 1.0 GHz Utilizes Multithreading, Graphics Optimization

Plenty of Memory 2 GB System Memory 512 MB RAM

Needs at least 8 GPIO pins High Res Display No more than 12 Volt Supply USB out for head-mounted camera Head-mounted, Mobile, Lightweight Low Power

Motherboard Comparison

Intel D2550 1.86 GHz 1M Cache 4 GB max RAM 8 GPIO 8 USB VGA 1 lb. & 17cm x 17cm 12 V supply

Raspberry Pi 0.8 Ghz 256 MB RAM 8 GPIO 2 USB 86mm x 54mm VGA/HDMI 45 g weight 5 V supply

System Block Diagram

Microcontroller Criteria

Signal Processing abilities Digital Communication Optimized for C compiler Resources and reference

material Processing

speed Price

DSPIC33EP512MU10 (PIC)

Has USB capabilities Extensive DSP Library with

built in FFT function

4-UART; 4-SPI; 2-I2C

Optimized for C compiler

Large online community

~53K of RAM

DSP56857 (FREESCALE)

Team is familiar with CodeWarrior IDE

120 MIPS

Built in voltage regulator

0-UART; 1-SPI; 0-I2C

Low Power Consumption

24K of RAM

Microcontroller Comparison

Microcontroller Selection Rationale DSP Library allows us to further filter a very sensitive EOG

signal. FFT function will allow us to decompose “raw EEG” signal

at 512 Hz instead of headset values which refresh at 1 Hz. Optimization for C compiler will allow greater simplicity in

implementing k-nearest neighbor algorithm for EOG signal classification.

Will be able to communicate with the EOG, the EEG, the FPGA and the single board computer.

Large online community and online documentation will aid in troubleshooting process

System Block Diagram

FPGA Design Criteria

Large area to implement Artificial Neural Network

Number of I/O pins needed Resources and

reference material Built in functionality Price

FPGA Design Constraints

Calculated a need of around 12,700 slices. Which equates to about 24,000 logic blocks, based on ANN’s previously made on FPGA’s

Need approximately 20 I/O pins (most FPGA have many more than needed)

Low power, and low cost Built in functionality to help with

development of algorithm Level of difficulty in designing

FPGA Design Comparison

Xilinx FPGA (Spartan-6) Library for floating point

arithmetic Built in 18 bit multipliers Documented ANN on

Xilinx FPGA’s Abundant reference

material on designing and programming

Cheaper than Cyclone 1.14V – 1.26V More than enough I/O pins

Altera FPGA (Cyclone-II) Prior knowledge of Altera

FPGA’s and Altera software from 437

1.15 V – 1.25 V More expensive than

Spartan More than enough I/O pins Unable to find documented

successful ANN on Altera devices