Mathcad - Design of 26.5W Isolated Flyback Converter · Designed by Sober Hu TASK : 26.5W 9-Outputs...

26.5W AC/DC Isolated Flyback Converter Design

Designed by Sober Hu

TASK : 26.5W 9-Outputs AC/DC Isolated Flyback Converter Design

SPECIFICATION : Technical Specification on Sept 10, 2008

DATE : 15 Sept. 2008


Customer Specification

fL 100Hz:= Line frequency

fs 100kHz:= Switching frequency

Vo1 5.0V:= Main output voltage

Io1_max 2A:= Main Nominal load current

Vo2 15.0V:= Io2_max 30mA:=

Vo3 15.0V:= Io3_max 30mA:=

Vo4 15.0V:= Io4_max 0.3A:=

Vo5 24.0V:= Io5_max 0.1A:=

Vo6 18.0V:= Io6_max 0.12A:=

Vo7 18.0V:= Io7_max 0.12A:=

Vo8 18.0V:= Io8_max 0.12A:=

Vo9 18.0V:= Io9_max 0.12A:=

+5V Output ripple voltageVr 100mV:=

+5VStep load output ripple voltage∆Vostep 150mV:=

∆Io5V Io1_max 80⋅ %:= +5V Step load current amplitude

η 0.70:=


Definition Of Symbols

u t( ) Φ t( ):= Unit step function

mΩ 103−Ω:= Milliohm

ms 103−s:= Millisecond

μs 106−s:= Microsecond

ns 109−s:= Nanosecond

mW 103−W:= Milliwatts

mJ 103−J:= Millijoule

μJ 106−J:= Microjoule

nC 109−C:= Nanocoulomb

μm 106−m:= Micrometer

μo 4 π⋅ 107−

⋅ H m1−

⋅:= Permeability of free space

ρ θ( ) 1.724 1 0.0042 θ 20−( )+[ ] 106−Ω cm⋅:= Resistivity of copper at θ degC


Component Summary

Primary FET - IRFBC30A - 600V, 3.6A, 2.2Ω

ζirfbc30a 1.7:= Channel resistance elevation factor to 100 degC

Ronirfbc30a 2.2Ω ζirfbc30a⋅:= Channel resistance at 100 degC

Qgirfbc30a 23nC:= Total Gate charge at Vgs of 10V

VgMillerirfbc30a 5.5V:= Gate Miller plateau from Gate Charge Curve

Vthirfbc30a 4.5V:= Gate threshold voltage

Vdsirfbc30a 25V:= Vds test voltage for capacitance value

Crssirfbc30a 3.5pF:= Reverse transfer capacitance at Vds of 25V

Cissirfbc30a 510pF:= Input capacitance

Coss_effirfbc30a 70pF:= Effective output capacitance

American Wire Gauge Table Formulae

AWG 10 11, 40..:= American wire gauge range

Dxbare AWG( )2.54

π10

AWG−

20⋅ cm:= Diameter of bare copper wire

Dxinsulated AWG( )Dxbare AWG( )

cm0.028

Dxbare AWG( )

cm⋅+

cm:=

Diameter of wire with heavy insulation

Ax AWG( )π Dxbare AWG( )

2⋅

4:= Bare copper cross section area

Rx θ AWG, ( )ρ θ( )

Ax AWG( ):= Resistance per unit length of AWG


Converter Parameters

Ts1

fs:= Converter period

Vgnom 220V:= Nominal input voltage

Vgmin Vgnom 1 20%−( )⋅:= Minimum input voltage

Vgmin 176V=

Vgmax Vgnom 1 20%+( )⋅:= Maximum input voltage

Vgmax 264V=

Pout1 Vo1 Io1_max⋅ Vo2 Io2_max⋅+ Vo3 Io3_max⋅+:=

Pout2 Vo4 Io4_max⋅ Vo5 Io5_max⋅+:=

Pout3 Vo6 Io6_max⋅ Vo7 Io7_max⋅+ Vo8 Io8_max⋅+ Vo9 Io9_max⋅+:=

Pout Pout1 Pout2+ Pout3+:=

Pout 26.44W=


Input Capacitor and Minimum Input DC Voltage

Cin 3μF

WPout⋅:=

Cin 79.32 μF⋅=

Cin 100μF:=

TC 2ms:=Estimated value

Dch TC fL⋅:=

Dch 0.2=

VMIN 2 Vgmin⋅

2 2Pout 1 Dch−( )⋅

η Cin⋅ fL⋅−:=

VMIN 236.45V= Minimum input DC voltage

Cin

Pout

η fL⋅ 2 Vgmin⋅

2

VMIN

2−

⋅

asinVMIN

2 Vgmin⋅

⋅:=

Cin 78.322 μF⋅=

Cin 100μF:=

VMAX 2 Vgmax⋅:=

VMAX 373.352V=

Dmax 0.45:=Set maximum duty cycle at minimum input voltage

VRO

Dmax

1 Dmax−VMIN⋅:= VRO 193.459V=

VDS VRO VMAX+:= VDS 566.811V= Check Vds of primary MOSFET


Primary Current Calculation

IpAVG

Pout

η VMIN⋅:=

IpAVG 0.16A=

IP

2 Pout⋅

η VMIN⋅ Dmax⋅:=

IP 0.71A=

IpRMS IP

Dmax

3⋅:=

IpRMS 0.275A=

Lm

VMIN Dmax⋅( )2 η⋅

2 Pout⋅ fs⋅:=

Lm 1.499 mH⋅=

Lm

2 Pout⋅

η IP2

⋅ fs⋅

:= Primary Inductance with Energy Transform Point

Lm 1.499 mH⋅=

Lm1

VMIN Dmax⋅

IP fs⋅:= Primary Inductance with Core Saturated Point

Lm1 1.499 mH⋅=

Bm 1500gauss:=

KW 0.15:= Winding Utilized Factor


KJ 5 A⋅ mm2−

⋅:=

APLm1 IP

2⋅

Bm KW⋅ KJ⋅ cm4

⋅

1.14

cm4

⋅:= AP22 Pout⋅

η Bm⋅3

Dmax

⋅ fs⋅KW

2⋅ KJ⋅

:=

AP 0.635 cm4

⋅= AP2 0.52 cm4

⋅=

AP31.6 Pout⋅

η Bm⋅ fs⋅ KW⋅ KJ⋅ cm4

⋅

1.14

cm4

⋅:=AP4

Lm IP⋅ IpRMS⋅

Bm KW⋅ KJ⋅:=

AP3 0.492 cm4

⋅= AP4 0.26 cm4

⋅=

Power Transformer - EER28L/PC40 from TDK

AeEER35 107mm2

:= Effective cross section area

Winding area base on BEER35-1112CPFR standard

bobbinAwEER35 152.7mm

2:=

APEER35 AeEER35 AwEER35⋅:=

APEER35 1.634 cm4

⋅=

WtEER35 52g:=

AeEE35 89.3mm2


AwEE35 88.7mm2

:= Winding area base on BEE35-1112CPLFR standard

bobbin

APEE35 AeEE35 AwEE35⋅:=

APEE35 0.792 cm4

⋅=


WtEE35 57g:=

AeEE32 83.2mm2


AwEE32 88.8mm2

:= Winding area base on BEE33-1112CPLFR standard

bobbin


APEE32 0.739 cm4

⋅=

WtEE32 32g:=

AeEE30 109mm2


AwEE30 44.5mm2

:= Winding area base on BE30-1110CPFR standard

bobbin


APEE30 0.485 cm4

⋅=

WtEE30 32g:=

AeEER28L 81.4mm2


AwEER28L 96.3mm2

:= Winding area base on BEER28L-1110CPFR standard

bobbin

APEER28L AeEER28L AwEER28L⋅:=

APEER28L 0.784 cm4

⋅=

WtEER28L 32g:=

μiPC40 2300:= Initial permeability of PC40 core material

VeEER28L 6150mm3

:= Core volume


leEER28L 75.5mm:= Effective path length

ALEER28L_PC40 2520 109−H⋅:= Nominal inductance of ungapped core set

Tape 0.06mm:= Wrapping tape thickness

MLTEER28L 2 3.14⋅ 7.0⋅ mm:= Average length of turn

HwEER28L

21.2 9.9−

2mm:= Available winding height

BwEER28L 2 12.53⋅ mm:= Available winding breadth

Kg2020

AeEER28L

2AwEER28L⋅

MLTEER28L

:= Geometrical constant of core


Power Transformer Flux Swing With EER28L-PC40 from TDK

VF 0.5V:=

nVRO

Vo1 VF+:= Transformer primary to secondary turn ratio

n 35.174=

Iplim 1.35 IP⋅:=

Iplim 0.958A=

BsPC40 3500gauss:= Select number of secondary turn

BrPC40 500gauss:=

∆BPC40 48% BsPC40 BrPC40−( )⋅:=

∆BPC40 1.44 103

× gauss⋅=

Npmin

Lm Iplim⋅

AeEER28L BsPC40⋅:=

Npmin 50.419=

Npcal

VMIN Dmax⋅

AeEER28L ∆BPC40⋅ fs⋅:=

Npcal 90.775=

Np 106:=


Ns1cal

Np

n:=

Ns1cal 3.014= Primary no of turns

Ns1 round Ns1cal( ):=

Ns1 3=VF2 0.7V:= Vcc 14V:=

NVc roundVcc VF2+( ) Ns1⋅

Vo1 VF+

:= NVc 8=

Ns2 roundVo2 VF2+( ) Ns1⋅

Vo1 VF+

:= Ns2 9=


Vo1 VF+

:= Ns3 9=


Vo1 VF+

:= Ns4 9=


Vo1 VF+

:= Ns5 13=


Vo1 VF+

:= Ns6 10=


Vo1 VF+

:= Ns7 10=


Vo1 VF+

:= Ns8 10=


Vo1 VF+

:= Ns9 10=


Verification of Design Parameters

nact

Np

Ns1:=

VROact nact Vo1 VF+( )⋅:=

VROact 194.333V=

Vdson 0.5V:=

D Vg( )nact Vo1 VF+( )⋅

nact Vo1 VF+( )⋅ Vg+ Vdson−:=

Dmaxact

VROact

VROact VMIN+ Vdson−:=

Dmaxact 0.452=

Dminact

VROact

VROact VMAX+ Vdson−:=

Dminact 0.343=

Vdsact VMAX VROact+:=

Vdsact 567.686V=

lg μo AeEER28L⋅Np

2

Lm

1

ALEER28L_PC40

−

⋅:=

lg 0.726 mm⋅=


Lmact Np2 μo μiPC40⋅ AeEER28L⋅

leEER28L μiPC40 lg⋅+⋅:= Nom inductance with ungapped core set

Lmact 1.514 mH⋅=

Ipact

VMIN Dmaxact⋅

Lmact fs⋅:= Ipact 0.705A=

BmLmact Ipact⋅

Np AeEER28L⋅:=

Bm 0.124T=

Ipact

VMAX Dminact⋅

Lmact fs⋅:= Ipact 0.845A=

BmLmact Ipact⋅

Np AeEER28L⋅:=

Bm 0.148T=

Bpp Vg( )Vg D Vg( )⋅

Np AeEER28L⋅ fs⋅:=

Bppmax max

Bpp VMAX( )Bpp VMIN( )

:=

Bppmax 0.148T= Check flux density of transformer

Power Transformer Winding Current

ip Vg( )Vg D Vg( )⋅

Lmact fs⋅:= ip VMIN( ) 0.705A=


Vout LsIsp fs⋅

Doff⋅=

Iout

Isp Doff⋅

2=

solve Doff, 2 Iout⋅

Isp

→

D1off

2 Io1_max⋅ Lmact⋅ fs⋅

nact

2Vo1⋅

:= D1off 0.311=

I1sp

2 Io1_max⋅

D1off

:= I1sp 12.842A=

I1RMS I1sp

D1off

3⋅:= I1RMS 4.138A=

I1AVG

1

2I1sp⋅ D1off⋅:= I1AVG 2A=

Cp 2:= Number of switching pulse to

display

Imosfet Vg t, ( ) d D Vg( )←

ip ip Vg( )←

0

Cp 1−

n

ip fs⋅

dt

n

fs−

⋅ u tn

fs−

⋅ un d+

fst−

⋅

∑

=

:=

Idiode Vg t, ( ) d D Vg( )←

ip ip Vg( )←

0

Cp 1−

n

I1sp

fs− I1sp⋅

D1off

tn d+

fs−

⋅+

...

u tn d+

fs−

u1 n+

fst−

∑=

:=


0 5 106−

× 1 105−

× 1.5 105−

× 2 105−

×

0

5

10

Imosfet VMIN t, ( )Idiode VMIN t, ( )Imosfet VMAX t, ( )Idiode VMAX t, ( )

t

D2off


Np

Ns2

2

Vo2⋅

:= D2off 0.066=

I2sp

2 Io2_max⋅

D2off

:= I2sp 0.908A=

I2RMS I2sp

D2off

3⋅:= I2RMS 0.135A=

I2AVG

1

2I2sp⋅ D2off⋅:= I2AVG 0.03A=

D3off


Np

Ns3

2

Vo3⋅

:= D3off 0.066=

I3sp

2 Io3_max⋅

D3off

:= I3sp 0.908A=


I3RMS I3sp

D3off

3⋅:= I3RMS 0.135A=

D4off


Np

Ns4

2

Vo4⋅

:= D4off 0.209=

I4sp

2 Io4_max⋅

D4off

:= I4sp 2.872A=

I4RMS I4sp

D4off

3⋅:= I4RMS 0.758A=

D5off


Np

Ns5

2

Vo5⋅

:= D5off 0.138=

I5sp

2 Io5_max⋅

D5off

:= I5sp 1.452A=

I5RMS I5sp

D5off

3⋅:= I5RMS 0.311A=

D6off


Np

Ns6

2

Vo6⋅

:= D6off 0.134=

I6sp

2 Io6_max⋅

D6off

:= I6sp 1.791A=

I6RMS I6sp

D6off

3⋅:= I6RMS 0.378A=


Evaluate Possible Wire Gauge

Window area should be allocated according to the apparent current of individual winding

IpRMS Vg( )Vg D Vg( )⋅

Lmact fs⋅

D Vg( )

3⋅:=

IpRMS VMIN( ) 0.274A=

Kcutrf 0.2:= Window fill factor

Sm 2.5mm:= Safety creepage distance

Aw BwEER28L 2 Sm⋅−:= Available bobbin breadth

Aw 20.06 mm⋅=

Primary winding Np6 Secondary winding Ns1

Axpri

Kcutrf AwEER28L⋅

Np:= Axs1

Kcutrf AwEER28L⋅

Ns1 9⋅:=

Axpri 0.182 mm2

⋅= Axs1 0.713 mm2

⋅=

KJP

IpRMS VMIN( )Ax 28( )

:= KJP 3.363A

mm2

⋅= KJs1

I1RMS

Ax 28( ) 12⋅:= KJs1 4.238

A

mm2

⋅=

Dxp

Ax 28( ) 4⋅

π:= Dxs1

Ax 28( ) 4⋅

π:=

Dxp 0.322 mm⋅= Dxs1 0.322 mm⋅=

turn_per_layerpri floorAw

Dxp

:= turn_per_layers1 floorAw

Dxs1 12⋅

:=

turn_per_layerpri 62= turn_per_layers1 5=


Secondary winding Ns4

Axs4

Kcutrf AwEER28L⋅

Ns4 9⋅:=

Axs4 0.238 mm2

⋅=

KJs4

I4RMS

Ax 28( ) 3⋅:= KJs4 3.105

A

mm2

⋅=

Dxs4

Ax 28( ) 4⋅

π:=

Dxs4 0.322 mm⋅=

turn_per_layers4 floorAw

Dxs4 3⋅

:=

turn_per_layers4 20=


Primary winding Np Secondary winding Ns1

layerpri roundNp

turn_per_layerpri

:= layers1 roundNs1

turn_per_layers1

:=

layerpri 2= layers1 1=

Secondary winding Ns4

layers4 roundNs4

turn_per_layers4

0.05+

:=

layers4 1=

StackUppri layerpri Dxp Tape+( )⋅:= StackUpsec 9 layers1⋅ Dxs1 Tape+( )⋅:=

StackUppri 0.764 mm⋅= StackUpsec 3.437 mm⋅=

TotalStackUpva StackUppri StackUpsec+ 5 Tape⋅+:=

TotalStackUpva 4.501 mm⋅=

Resistance per unit length at 100 degC

Rwpri Rx 100 28, ( ):= Rws1 Rx 100 28, ( ):=

Rwpri 2.831 103−

× Ω cm1−

⋅⋅= Rws1 2.831 103−

× Ω cm1−

⋅⋅=

The dc resistance is then

Rdcpri MLTEER28L Rwpri⋅ Np⋅:= Rdcs1 MLTEER28L Rws1⋅Ns1

12⋅:=

Rdcpri 1.319 Ω⋅= Rdcs1 3.111 mΩ⋅=

Rws4 Rx 100 28, ( ):=

Rws4 2.831 103−

× Ω cm1−

⋅⋅=


Rdcs4 MLTEER28L Rws4⋅Ns4

3⋅:=

Rdcs4 37.331 mΩ⋅=

The ac resistance is

δskin

ρ 25( )

π μo⋅ fs⋅:=

δskin 0.211 mm⋅=

Racpri

Dxbare 28( )

δskin

Rdcpri⋅:= Racs1

Dxbare 28( )

δskin

Rdcs1⋅:=

Racpri 2.011 Ω⋅= Racs1 4.742 mΩ⋅=

Racs4

Dxbare 28( )

δskin

Rdcs4⋅:=

Racs4 56.905 mΩ⋅=

Transformer Copper Loss

Pcutx Vg( ) IpRMS IpRMS Vg( )←

IpRMS

2Rdcpri⋅ IpRMS

2Racpri⋅+ I1RMS

2Rdcs1⋅ 4⋅+

I1RMS

2Racs1⋅ 4⋅+

...

:=

Pcutx VMAX( ) 0.809W=

Pcutx VMIN( ) 0.787W=

Transformer Core Loss Estimation

Core loss estimation based on empirical curve fit formula and fit parameters from TDK for

PC40 material data within a frequency range of 100 to 200kHz, assumming transformer

temperature of 100 degC.


Cm 0.928:=

x 1.61:=

y 2.68:=

Pcoretx Vg( ) Cm

fs

Hz

x

⋅Bpp Vg( )

2 T⋅

y

⋅W

m3

⋅ VeEER28L⋅:=

Pcoretx VMAX( ) 0.6W= Transformer core loss

Pcoretx VMIN( ) 0.37W=

Total Transformer Losses

Ptx Vg( ) Pcutx Vg( ) Pcoretx Vg( )+:=

Ptx VMAX( ) 1.409 W⋅= Power transformer loss at high line, FL

Ptx VMIN( ) 1.157W= Loss at low line, FL

250 300 3501.1

1.2

1.3

1.4

Ptx Vg( )

Vg


Secondary Rectifier Stress

Vs1diode Vo1 VMAX

Ns1

Np⋅+:= Vs1diode 15.567V=

Vs2diode Vo2 VMAX

Ns2


Vs3diode Vo3 VMAX

Ns3


Vs4diode Vo4 VMAX

Ns4


Vs5diode Vo5 VMAX

Ns5


Vs6diode Vo6 VMAX

Ns6


Vs7diode Vo7 VMAX

Ns7


Vcdiode Vcc VMAX

NVc

Np⋅+:= Vcdiode 42.178V=

Pdrectifier VF Io1_max⋅ VF2 Io2_max⋅+ VF2 Io3_max⋅+ VF2 Io4_max⋅+ VF2 Io5_max⋅+ 4 VF2⋅ Io6_max⋅+:=

Pdrectifier 1.658W=


Output Filtering Capacitance Stress

Cout1 2200μF:= ESR1 5mΩ:=






Is1cap I1RMS

2Io1_max

2−:= Is1cap 3.623A=

∆Vs1

Io1_max Dmax⋅

Cout1 fs⋅I1sp ESR1⋅+:= ∆Vs1 0.068V=

Is2cap I2RMS

2Io2_max

2−:= Is2cap 0.131A=

∆Vs2

Io2_max Dmax⋅


Is3cap I3RMS

2Io3_max

2−:= Is3cap 0.131A=

∆Vs3

Io3_max Dmax⋅


Is4cap I4RMS

2Io4_max

2−:= Is4cap 0.696A=

∆Vs4

Io4_max Dmax⋅


Is5cap I5RMS

2Io5_max

2−:= Is5cap 0.295A=


∆Vs5

Io5_max Dmax⋅


Is6cap I6RMS

2Io6_max

2−:= Is6cap 0.359A=

∆Vs6

Io6_max Dmax⋅


Capacitance requirement - Transient response dependence

τ 15 Ts⋅:= Assume delay time before converter response to a

change in load current

∆Vocap

∆Io

Coτ⋅= Capacitive voltage change due to load step

∆Voesr ∆Io Resr⋅= Voltage change across esr due to a load step

∆Vo ∆Vocap ∆Voesr+= Output voltage change due to a load step ignoring

effect of ESL

∆Vo∆Io

Coτ⋅ ∆Io Resr⋅+=

Coτ

∆Vo

∆IoResr−

> Capacitance required for a voltage deviation of ∆Vo

with say Resr

no_of_cap 1:= Select number of capacitor required

ResrESR1

no_of_cap:=

Resr 5 mΩ⋅= Effective ESR with capacitor chosen

Capacitor ripple current and effective current handling capacity

∆Icap I1RMS

2Io1_max

2−:= AC rms current seen by cap

∆Icap 3.623A=


Output ripple voltage with selected capacitors

∆Vr I1sp ESR1⋅:= Output ripple voltage due to esr

∆Vr 64.21 mV⋅= Maximum output voltage ripple at room temperature

At low temperature, esr of capacitor changes significantly

Resrlotemp Resr 2⋅:=

Resrlotemp 0.01Ω=

∆Vrlotemp ∆Icap Resrlotemp⋅:=

∆Vrlotemp 0.036V= Maximum output ripple at low temperature

κripple 1∆Vrlotemp

Vr−:=

κripple 63.775 %⋅= Ripple voltage design margin at low temperature

Step load ripple voltage

Comin no_of_cap Cout1⋅ 1 10%−( )⋅:=

∆Vo ∆Io5V Resrlotemp

τ

Comin

+

⋅:= Voltage change due to step load

∆Vo 0.137 V⋅=

κstep 1∆Vo

∆Vostep

−:=

κstep 8.525 %⋅= Step response ripple deviation design margin at low

temperature

Estimate Power Loss In Capacitor ESR

Pesr Vg( )∆Icap

2

1

3⋅

2

Resr⋅:=

Pesr VMAX( ) 5.468 mW⋅=


Design RCD Snubber

Lpleak Lmact 0.2⋅ %:= Lpleak 3.028 μH⋅=

Vsn 220V:=Maximum snubber capacitor voltage

KVsn 5%:=

VROact 194.333V=

PsnRES

1

2Vsn⋅ Ipact⋅ fs⋅

Lpleak

Vsn VROact−⋅ Ipact⋅:=

PsnRES 0.926W=

RsnVsn

2

PsnRES

:= Rsn 52.244 KΩ⋅=

CsnVsn

KVsn Vsn⋅ Rsn⋅ fs⋅:= Csn 3.828 nF⋅=

Primary FET Voltage Stress

Vdsmax Vg( ) Vg Vsn 1 KVsn+( )⋅+:=

250 300 350450

500

550

600

Vdsmax Vg( )

Vg

Vdsmax max

Vdsmax VMIN( )Vdsmax VMAX( )

:=


Vdsmax 604.352V= Peak switch voltage stress at high line


Primary Switch Current

Main FET conducts the transformer primary current

IQ Vg t, ( ) Imosfet Vg t, ( ):= Main switch current

IQRMS Vg( )Vg D Vg( )⋅

Lmact fs⋅

D Vg( )

3⋅:= Main switch rms current

IQpk Vg( )Vg D Vg( )⋅

Lmact fs⋅:= Main switch peak current

Primary FET Loss Estimation - IRFBC30A

Gate drive loss

Vgate 10V:= Gate drive voltage

Pgate Vgate Qgirfbc30a⋅ fs⋅:=

Pgate 0.023W= Gate drive loss

Saturation loss

PQon Vg( ) IQRMS Vg( )2

Ronirfbc30a⋅:=

PQon VMAX( ) 0.305W= Saturation loss at high line, FL

PQon VMIN( ) 0.28W=

Output capacitance loss

PQcap Vg( )1

2Coss_effirfbc30a⋅ Vg

2⋅ fs⋅:=

PQcap Vgmax( ) 0.244W= Output capacitance loss at high line


Switch loss

Vplt VgMillerirfbc30a:= Gate Miller plateau voltage

Vth Vthirfbc30a:= Gate threshold voltage

Rgate 5.6Ω:= Gate series resistor

IgaVgate 0.5 Vplt Vth+( )⋅−

Rgate

:= Gate current that charges the input capacitance

from from gate threshold to Vplt

Iga 0.893A=

IgbVgate Vplt−

Rgate

:= Gate current that discharge Miller capacitance Crss

when drain voltage starts to fall to zero

Igb 0.804A=

ton Vg( ) Cgd 2 Crssirfbc30a⋅Vdsirfbc30a

Vg⋅←

Cissirfbc30a

Vplt Vth−

Iga⋅ Cgd

Vg

2 Igb⋅⋅+

:=

PQswitch_on Vg( ) ton ton Vg( )←

IQpk IQpk Vg( )←

1

2Vg⋅ IQpk⋅ ton⋅ fs⋅

:=

PQswitch_on VMIN( ) 7.556 103−

× W=

PQswitch_on VMAX( ) 0.016W=

Assumming the same order of magnitude for the switch turn off lost with a fast turn off gate drive

circuit, the total switch loss is,

PQswitch Vg( ) 2 PQswitch_on Vg( )⋅:=

PQswitch VMIN( ) 0.015W=

PQswitch VMAX( ) 0.031W= Total transitional loss at high line, FL


Total Primary FET loss

PQ Vg( ) Pgate PQon Vg( )+ PQcap Vg( )+ PQswitch Vg( )+:=

PQ VMIN( ) 0.514W=

PQ VMAX( ) 0.847W= Primary switch losses at high line, FL

Design Feeback Control Loop

Bode Plot of Power Stage

n 0 1, 50..:= f n( ) 10

1n

10+

Hz:= ω n( ) 2 π⋅ f n( )⋅:=

Gpwm

1

2 2⋅

2 2⋅ 750+VMIN⋅

:= Gpwm 0.7971

V⋅=

Small signal moel with feedfoward of UCC25706

Small signal model of DCM flyback converter operated in voltage mode control

fz11

2π Cout1⋅ ESR1⋅:= fz1 14.469 KHz⋅=

fz2 Vg( )

Np

Ns1

2 Vo1

Io1_max

⋅ 1 D Vg( )−( )2

⋅

2π Lmact⋅ D Vg( )⋅:=

fz2 VMIN( ) 218.443 KHz⋅=

fz2 VMAX( ) 413.81 KHz⋅=

fo Vg( )

Np

Ns11 D Vg( )−( )⋅

2π Lmact Cout1⋅⋅:= fo VMIN( ) 1.69 KHz⋅=

fo VMAX( ) 2.026 KHz⋅=

Q Vg( )

Np

Ns1

Vo1

Io1_max

⋅ 1 D Vg( )−( )⋅

2πLmact

Cout1

⋅

:=


Gdo Vg( )Vg

Np

Ns11 D Vg( )−( )

2⋅

:=

Tpwr Vg ω, ( )

Gpwm Gdo Vg( )⋅ 1i ω⋅

2π fz1⋅+

⋅ 1i ω⋅

2π fz2 Vg( )⋅−

⋅

1i ω⋅

2π fo Vg( )⋅ Q Vg( )⋅+

ω2

2π fo Vg( )⋅( )2−

:=

Gpwr Vg ω, ( ) 20 log Tpwr Vg ω, ( )( )⋅:=Ppwr Vg ω, ( )

180

π

arg Tpwr Vg ω, ( )( )⋅:=

Gpwrmin ω( ) Gpwr VMIN ω, ( ):= Ppwrmin ω( ) Ppwr VMIN ω, ( ):=

Gpwrmax ω( ) Gpwr VMAX ω, ( ):= Ppwrmax ω( ) Ppwr VMAX ω, ( ):=

10 100 1 103

× 1 104

× 1 105

× 1 106

×

40−

28.75−

17.5−

6.25−

5

16.25

27.5

38.75

50

Power Gain

Frequency

Gain

- d

B


10 100 1 103

× 1 104

× 1 105

× 1 106

×

200−

152.778−

105.556−

58.333−

11.111−

36.111

83.333

130.556

177.778

225

Power Stage Phase

Frequency

Phase -

Degre

es

Loop stability criteria

How to arrange the crossover frequency?

It is the best with as high as possible bandwidth. But the crossover

frequency is limited by the parameters:

1. Sampling theory limit the crossover freqency not to over 1/2

operation frequency.

2. The effect fo right plane zero which is changed followed with input

voltage, load, and filtering inductance. It can't be compensated.

Therefore, the bandwidth shall be far away the right plane zero,

1/4--1/5 of RHZ.

3. The limitation of error amplifier bandwidth. 1/6-1/10 of operation

frequency.

fcfz2 VMIN( )

30:= fc 7.281 KHz⋅= fc 3KHz:=

Phase π− atanfc

fz1

+ atanfc

fz2 VMIN( )

−

180

π⋅:= Phase 169.073−=


Because of LC resonant at the output, the phase big change and

close to 180 degree. As a result, the compensation of type III will be

used to boost the phase. Zero-pole arrangement:

1. 1st pole at the origin to boost the gain at the low frequencies.

2. 2 zeros at LC resonant point.

3. 2nd pole at the output capacitor esr zero.

4. 3nd pole at the RHZ.

Bode Plot of Error Amplifier

K-Factor Method: ϕm 45:=

Pshift 360 ϕm−:= Pshift 315=

Perrorpermitted Pshift Phase+:= Perrorpermitted 145.927=

Kfac tan450 Perrorpermitted−

4

π

180⋅

:= Kfac 4.016=

fz3fc

Kfac

:= fz4 fz3:= fz3 0.747 KHz⋅=

fp2 fc Kfac⋅:= fp3 fp2:= fp2 12.049 KHz⋅=

Gpwr.fc Gpwr VMIN 2π fc⋅, ( ):= Gpwr.fc 18.471=


Gerror.fz3 Gpwr.fc− 20 logfc

fz3

−:= Gerror.fz3 30.547−=

X1

C2

R3

C1

R1

R2

C3

Vref

R1 20KΩ:=

31.233− 20 logR2

R1

= solve R2, 0.54875690204124249564 KΩ⋅→

R2 R1 10

Gerror.fz3

20⋅:=

R2 0.594 KΩ⋅=

C21

2π fp2⋅ R2⋅:= C2 0.022 μF⋅=

C11

2π fz3⋅ R2⋅:= C1 0.359 μF⋅=

C31

2π fz4⋅ R1⋅:= C3 0.011 μF⋅=

R31

2π fp3⋅ C3⋅:= R3 1.24 KΩ⋅=

fp1

1

2π R1⋅ C1⋅:=


Tcomp ω( )

1i ω⋅

2 π⋅ fz3⋅+

1i ω⋅

2 π⋅ fz4⋅+

⋅

i ω⋅

2 π⋅ fp1⋅1

i ω⋅

2 π⋅ fp2⋅+

⋅ 1i ω⋅

2 π⋅ fp3⋅+

⋅

:=

Gcomp ω( ) 20 log Tcomp ω( )( )⋅:=Pcomp ω( )

180

π

arg Tcomp ω( )( )⋅:=

10 100 1 103

× 1 104

× 1 105

× 1 106

×

30−

23−

16−

9−

2−

5

Compensation Gain

Frequency

Gain

- d

B

10 100 1 103

× 1 104

× 1 105

× 1 106

×

100−

50−

0

50

Compensation Phase

Frequency

Phase -

Degre

es

Gcompfc Gcomp 2π fc⋅( ):=Gcompfc 18.471−=


Bode Plot of Closed-Loop

Tloop Vin ω, ( ) Tcomp ω( ) Tpwr Vin ω, ( )⋅:=

Gloop Vin ω, ( ) 20 log Tloop Vin ω, ( )( )⋅:= Ploop Vin ω, ( ) 180

π

arg Tloop Vin ω, ( )( )⋅:=

Gmaxmax ω( ) Gloop VMAX ω, ( ):= Gminmax ω( ) Gloop VMIN ω, ( ):=

Pminmax ω( ) Ploop VMIN ω, ( ):= Pmaxmax ω( ) Ploop VMAX ω, ( ):=

10 100 1 103

× 1 104

× 1 105

× 1 106

×

50−

39.375−

28.75−

18.125−

7.5−

3.125

13.75

24.375

35

Min Vin

Max Vin

0 dB

Loop Gain

Frequency

Gain

- d

B


10 100 1 103

× 1 104

× 1 105

× 1 106

×

180−

135−

90−

45−

0

45

90

135

180

Loop Phase

Frequency

Phase -

Degre

es

Phaseloop Phaseπ

2− 2atan

fc

fz3

+ atanfc

fp2

− atanfc

fp3

−

180

π⋅+:=

Phaseloop 135−=

Margin 180 Phaseloop+:= Margin 45=

Mathcad - Design of 26.5W Isolated Flyback Converter · Designed by Sober Hu TASK : 26.5W 9-Outputs...

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Transcript of Mathcad - Design of 26.5W Isolated Flyback Converter · Designed by Sober Hu TASK : 26.5W 9-Outputs...