Mask ProgrammedGate Arrays

$7.4B

ProgrammableLogic Share

$5.8B

Standard Logic$2.6B

37%37%16%

47%

Total 1996 Market – $9.5B Total 2001 Market – $15.8B

Programmable LogicTakes Market Share from Others

Mask ProgrammedGate Arrays

$5.6B

ProgrammableLogic Share

$1.9B

Standard Logic$2.0B

20%20%21%

59%

Source: Dataquest, May 1997

CMOS Programmable Logic Market

CPLDSPLD

FPGAEPLD

Total CMOSProgrammable Logic

1996$959

2001$2400

1996$884

2001$2687

1996$411

2001$279

1996$548

2001$2121

Source: In-Stat May 1997

CAGR 33%

ASIC AlternativesCustomHighest DensityASIC Tools

FPGA

EPLD

ProgrammableGA ArchitectureHigh DensityASIC Tools

ProgrammablePAL ArchitectureMedium DensityPAL-like ToolsProgrammable

AND/ORArchitectureLow DensitySimple Tools

XilinxProduct

LineHardWire(TM)

Array

CustomTransparentConversion100% Tested

PAL™

GateArray

Company Milestones

1984 Xilinx Founded1985 Introduced first field programmable gate array (FPGA)1987 Introduced second family of FPGAs1988 Established subsidiary in Japan1989 More than one million devices sold1990 Initial public offering1991 Introduced third family of FPGAs1992 Expanded into complex programmable logic (CPLDs)1993 Established Xilinx Hong Kong1995 Xilinx ranked 10th largest ASIC supplier; Xilinx Ireland opens1996 Xilinx ranked 8th largest ASIC supplier1997 Industry’s first advanced 0.35 & 0.25 micron FPGAs1998 Introduced low-cost Spartan FPGAs with RAM & cores

Why Xilinx? Silicon

Largest, fastest, lowest power FPGAs Lowest cost CPLDs

Software Alliance Series: HDL, synthesis, EDA integration, optimization Foundation Series: ready to use, complete solutions LogiCORES & AllianceCORES: optimized and supported

Service Most comprehensive field and on-line technical support Advanced Internet Web solutions

Process Technology Deep submicron capacity — Sampling 0.25 micron now Better price, performance, density

0

100

200

300

400

500

600

1990 1991 1992 1993 1994 1995 1996 1997 1998

Fiscal year ends March 31

Xilinx Revenue Growth1990–1998 Fiscal Year Revenues

$50

$ Millions

$98$136

$178

$256

$355

$561 $568$614

High Density FPGA Sales( gates, Previous 4 Quarters)

Xilinx sells more high-density FPGAs than the rest of industry combined.

This is a result of Xilinx’ past and present leadership.

13K

Rev

enu

e (M

$)Xilinx Lucent Altera

0

20

40

60

80

100

Xilinx Lucent Altera

EuropeJapan Rest of World

North America

10%10% 5%5%

63%63%

22%22%

Source: Xilinx

Worldwide Sales

Industrial &Instrumentation

Communications

12%16%16%

35%35%

Military, HighReliability

4%4% 1% Misc

32%32%

Networking

DataProcessing

Source: Xilinx

Who’s Using Xilinx

Where Xilinx Fitsin the Electronics Industry

Key components of an electronics system Processor Memory Logic

Xilinx is the Leading Innovatorof Complete Programmable Logic Solutions

How Customers UseProgrammable Logic

Xilinx Provides Standard Parts “Blank” Integrated Circuits

Customers Create Custom Circuits with Xilinx Software Tools

When Design Is Final,Customers Go intoImmediate Production

Market Segments

Communications

Computers

Instruments

Medical equipment

Networks

Consumer electronics

Xilinx Application ExamplesApplication Examples

Broadcast Communications� HDTV

� CATV (Scramblers & Decoders)

� Satellite Links

� Studio Equipment

� Video Disk Recorder

Consumer� Digital Audio Decoder

� Arcade Games

� Video Games

� Karaoke Systems

Transportation� Railway Systems

� Auto Digital Audio Systems

Industrial� Test And Measurement Equipment

� Medical Equipment

� Motor/Motion Control

� Semi. Processing Equipment

� PC Projection Units

� Robotics

� ASIC Emulators

� Postage Systems

� Vision Systems

� µP Emulators

� Lottery Systems

Military• Computer And Communications Systems

• Missile Guidance Avionics

• Fire Control

Computer• Memory Interfaces

• DMA Controllers

• Local And Mezzanine Bus Interfaces

• Cache Controllers

• SSP Co-Processors

• Multi-Media

• Graphics

Peripherals• Disk Controllers

• Video Controllers

• FAX (Incl. PCMCIA)

• Barcode Readers

• Teller Machines

• Tape Controllers

• Sound Cards

• Modems (Incl. PCMCIA)

• POS Systems

• Data Acquisition Cards

• Terminals

• Printers

• Scanners

• Copiers

Data Communications• Multiplexers

• Routers

• Video Conferencing

• Encryption/Decryption

• Switches

• Bridges

• Modems (incl. PCMCIA)

• Data Compression

• LAN Hubs

• FDDI

• Wireless LANS (Incl. PCMCIA)

Telecommunications• Central Office Switches

• SONET Interfaces

• Cellular Base Stations

• Auto. Directory Assistance

• Fiber Optic Interfaces

• ATM

• ISDN Interfaces

• Voice-Mail Controllers

• PBX Equipment

• T1 Multiplexers

• Speech Synthesis

• Pay Phone Control

• Data Compression

Strategic Business ModelEnsures Focus

“Fabless” strategy Leading edge IC process technology Wafer capacity at competitive prices Fastest, lowest cost, densest parts

Independent sales organization Sales is a variable cost Permits greater reach—over 15,000 customers

Focus on key strengths Research and development Marketing Applications engineering

Xilinx’ Fabless Advantage

$136M equity investment in UMC guaranteed 33% capacity of new 8” fab

$300M advanced payment to Seiko guaranteed capacity for next 5 years

Access to 0.25 & 0.18 leading edge fab in 1997

Guaranteed fab access to support $2B/year revenue

50 engineers working in-house on process technology Developed FastFLASH process Developed Micro-Via antifuse process

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1991 1992 1993 1994 1995 1996 1997 1998 1999 2000

Process Technology Leadership Roadmap

5.0 V

3.3 V2.5 V1.8 V

Year

Feature Size(µm)

5V “cost reduction line” hasbeen valid for >10 years

Year

Den

sity

(lo

gic

cel

ls)

Density Roadmap

2001 -> 150,000 logic cells (2.0M gates)

logic cell = 4-input LUT + FF

Gat

es

1,000

10,000

100,000

1,000,000

1994 1996 1998 2000 2002

Year

12M

1.2M

120K

12K

2.0M gates2.0M gates

Xilinx vs Other FPGAInterconnect Technology

LogicBlock

1

LogicBlock

2

LogicBlock

n

4x4x

4x

LogicBlock

(next row)

...

Across Chip

LogicBlock

1

LogicBlock

2

LogicBlock

n

LogicBlock

3 ...

6x

3x

LogicBlock

(next row)

1x

Across Chip

“Segmented” Interconnect Lines•Variable Length Interconnect Lines•1 Segmented line required to connect 4 logic cells •Smaller Die Size => Lower Cost

“Non-Segmented” Interconnect Lines•Fixed Length Interconnect Lines•3 Single Signal lines required to connect 4 logic cells •Larger Die Size => Higher Cost

Xilinx Interconnect Other FPGA Interconnect

Segmented Interconnect Structure Provides Faster Logic Cell Connections

1x 1x

Performance Roadmap

0

20

40

60

80

100

120

140

160

180

200

1995 1996 1997 1998 1999 2000

Year

MH

z

Sy

stem

Clo

ck

Ra

te1

/(T

setu

p+

Tcl

ock

-to

-ou

t)

Process Technology Makes this Possible

5x Improvement in 5 years

Power Roadmap(for constant gates & frequency)

Power CV2f

Low power = high performance

Low power = higher reliability

1996 2001

3xPower

Year

>>3x

non-segmented interconnect

(others)

non-segmented interconnect

(others)

segmented interconnect

(Xilinx)

segmented interconnect

(Xilinx)

Hardwire for High Volume2001

20k 40k 60k 80k 100k

HardWireHardWire

250k 500k 750k 1M 1.25M

FPGAFPGA

Same curves, change numbers

Largest savings on biggest devices

Design Once

Risk-free migration

No test vectors

Logic Cells

Gates

$

First to use PQFP & VQFP

First to use BGA & SBGA (Super BGA)

Investigating flip-chip today for higher integration

100

1000

1992 1994 1996 1998 2000 2002

3000

PQFPs & VQFPs BGA

Flip-chipFlip-chip

SBGASBGA

Pac

kag

e P

ins

Year

Xilinx Pioneers FPGA Packages

1997 1997 1998Buses PCI slave 33MHz PCI 3.3v slave PCI slave 66MHz

PCI master 33MHz PCI 3.3v master PCI master 66MHzUSB device controllerISABus Plug & Play

Telecom ATM cell delineation E1/E2/E3 framer SONET standard coresATM Utopia master E1/E2/E3 processor OC standard coresATM Utopia slave E1 crossconnect Echo cancellerISDN, HDLC controller E1 Add/drop mux ADSLM16450 UART SONET/SDH pointer Ethernet

STS-3 parallel framer QAM/FEC

DSP FIR filters Convolution filters Math toolkitCorrelators (8-128 bits) Channel models Voice modelsMultipliers, high speed MPEGRZ1000 DFT MAC

Basic Blocks 8237 DMA controller ASIC libraries8254 interval controller 80328255 peripheral interface CRC

Availability of LogiCores

Xilinx is the leader in LogiCores today

Xilinx FPGA Architectures

1997

11,000 Logic Cells (125k gates)

fastest RAM

5 volt tolerant IOs

buffered quad line

VersaRing IOs

6ns pin-to-pin

efficient segmented routing

lowest power

1999

65,000 Logic Cells(800k gates)

built-in logic analyzer

D/A & A/D support

custom cores

high speed differential interface (500MHz)

1998

32,000 Logic Cells

(400k gates)

programmable IOs

Advanced Clocking

100MHz system speed

fast re-configure

hierarchical memory

solution

Xilinx Leads - Others Follow

Xilinx has a long history of leadership.

This trend will continue!!

Lucent Altera

FPGA Solution 1985 1990 1994

Pin Compatibility 1988 1990 1996

Hardwire 1990 ? ?

On-chip RAM 1991 1993 1996

FPGAs >= 20k gates 1994 1995 1996

Synopsys 5 YearRelationship

1994 ? 1996

FPGA Cores 1995 ? ?

Shipped 40,000,000th FPGA

1996 ? ?

A History of Software Innovation

1986

1993

1995

Q4’96

1992

1994

1994

1994

1994

1994

1994

1985PAR TM

1992 Timing WizardTM

1992XBLOX TM ,

LogiBLOX

1994

1996

1985XACT TM

1992 EPICTM

1992 FPGA ArchitectTM

1990 Xilinx AllianceTM

1992 HLDLTM

1990 Hardware DebuggerTM

1996 LogiCoresTM

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

NoNoAnswerAnswer

1990Industry’s First FPGA Design Tools

FPGA Specific-Timing Analysis

Graphical Editor for Programmable ICs

Automatic Module Generation

Software Architectural Modeling

Commitment To Open Systems

Synopsys Constraint Interpretation

Synopsys Technology Partnership

Graphical Hardware Debugging

Software Internationalization

Fully Verified and Optimized IP Cores

Industry’s First Timing-Driven Tools

Lucent AlteraXilinxInnovation

Overview the FPGA Overview the FPGA Basic ArchitectureBasic Architecture

PLD Advantages Vs Gate Array

Faster Time to Market Immediate Prototypes Faster Debug Lower Risk PCB Development

Faster Access to Hardware for Firmware/Software Development

Test Marketing Capability

Field Upgrade Potential

Solve Gate Array Obsolescence Problems

CPLD FPGA

Architecture PAL-like Gate array-like

Density Low-to-medium Medium-to-high

Basic Cell Product Term CLB & LUT

Application Combination based Register Based

Performance Predictable timing Application dependent

Design Entry Equation & Schematic Schematic & HDL

Complex Programmable Logic Device Field-Programmable Gate Array

CPLDs and FPGAs

What is the FPGA

CLB

CLB

CLB

CLB

SwitchMatrix

ProgrammableInterconnect

I/O Blocks (IOBs)

ConfigurableLogic Blocks (CLBs)

- Look up table base architecture- Rich Flip Flop application design- No predictable pin to pin delay just CLB delay- One hot decoding & Reconfiguration - Lower price per gate & High density and Speed

I/O Block (IOB)

Identical I/O Blocks line the periphery of die

Input, output, or bi-directional

Registered, latched, or combinatorial

Three-state output Programmable

output slew rate

IOB Primitives

User explicitly defines what resources in the IOB are to be used

Special IOB primitives Inverters may also be pulled into IOBs Properties attached to primitives

IPADIBUF

Input IOB

OPADOBUF

Output IOB

Use Pull-ups/Pull-downs to Prevent Floating

Pull-up automatically connected on unused IOBs

Outputs of unused IOBs are automatically disabled

A PULLUP or PULLDOWN primitive can be specified on used IOBs

Must be instantiated in HDL

Inputs should not be left floating Add a pull-up to design inputs that may be left

floating to reduce power and noise

OPADOBUF

FAST

Slew Rate Control

Slew rate controls output speed

Default slow slew rate reduces noise

Use fast slew rate wherever speed is important FAST parameter on output logic primitive

Use I/O Registers Guaranteed clock to out and clock to setup

See Data Book (Pin-to-Pin Input Parameter Guidelines)

Provides fastest SYSTEM speed Note: Will not be reported by the static timing analysis tool. .

D

CE

Q

D

CE

Q

I/O padFrom: FPGA

Into: FPGA

CLB(Configurable Logic Block)

2 4-input LUTs and 1 3-input LUT

” muxes feed F/G LUTs or independent inputs to H LUT

2 edge-triggered FFs DIN EC SR

4 outputs Fed by “B” muxes

Flip-Flops in the CLB

2 Edge-triggered flip-flop per CLB

Independent Clock polarity

Selectable clock enable

Asynchronous set or reset

Local and/or global control

Combination Logic Resources

Lookup tables Can be combined into multiple levels Special cascade chain in XC5000

Carry logic XC4000E/X/XC5000

Wide decoders XC4000E/X

Three-state buffers XC4000E/X/XC5000

FPGA Lookup Tables Two four-input functions and one three-input function

One five-input function

One four-input function and some six-input functions

Some nine-input functions

F

G

H

DIN S/R H1

F1-F4

G1-G4

C1-C4

to flip-flops &CLB outputs

Look-Up Tables

Combinatorial Logic is stored in Look-up Tables (LUTs) in a CLB

Example:Combinatorial Logic

AB

CD

Z

A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 . . . 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1

• Capacity is limited by number of inputs, not complexity

• Delay through CLB is constant

XC4000 Select-RAM AdvantagesTM

Address

Data

WE

XC4000ERAM

Clock

Data 2

Address 2

OptionalDual Port

Select the Function - Can be Single or Dual Port - Synchronous or Asynchronous - “Mix and match” Select the Size

- No wasted resources- Scalable to needed size

Select the Location - Can be located anywhere on die - Adjacent to critical circuits for speed

Select the Programming Method - Via bitstream on start-up - During design operationSimple to use

O = I1*I2I1

I2O

F1

F2X

DATA(0)=0DATA(1)=0DATA(2)=0DATA(3)=1

A0

A1DOUT

F1

F2X

As Gates As ROM

ROM is Equivalent to Logic

When using ROM, it is simply defining logic functions in a look-up table format

Memory might be an easier way to define logic

FPGA lookup tables are essentially blocks of RAM Data is written during configuration Data is read after configuration

– Effectively operate as a ROM

RAM Provide 16X Flip-Flops

32 bits vs. 2 bits of storage Non-simultaneous access

32x8 shift register with RAM = 11 CLBs Using flip-flops, takes 128 CLBs for data alone

32 bits

A0A1A2A3A4

O12 bits

D Q

D Q

Q1

Q2

CLB CLB

D1

D2

WE CLK

D1

RAM for Status registers Provides up to a 16 to 1 density increase!

Easier routing for FPGA

Ten 16 bit read/write status registers on a bus use: 160 registers -or- 80 CLBs

In RAM the same ten status registers use:16 four input look-up-tables -or- 8 CLBs

Vs.Reg. RAM

16x32 FIFO Uses Only 32 CLBs with RAM

If implemented in registers: 256 CLBs for storage alone

Implemented in XC4000/SPARTAN RAM: Storage requires only one CLB per 32 bits

– Other CLBs used for addressing and control Runs at 66 MHz in XC4000XL-2

Dual-Port RAM

One common synchronous write port

Two asynchronous read ports

16x1 max per CLB

Data Bus Size

20

25

30

35

40

45

50

55

60

65

70

8 Bit 16 Bit 32 Bit

FLEX Block RAM is Single-Port only. Must emulate Dual-Port cutting performance in half.

Over 2x Faster System Performance

XC4000E Select-RAMXC4000E Select-RAM

FLEX EABFLEX EAB

Xilinx Select-RAM delivers 2x performance for large Dual-Port RAM

Fast Memory: Dual-Port RAM

Average pin to pin performance of dual port RAM with various depth from 8 to 1024 words

DataIn

DataOut Block RAM

0100111011

110110101001

110110101001 1

1

1

00

01001

0001001

EmulatedDual Port

Altera’s Bottleneck = One Port

Mhz

Higher Utilization: Dual-Port RAM

30 Logic Cells PLUS 1 EAB

EAB

LC LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

FLEX 10K

16x4 Dual Port RAM

LC

LC

LC

LC

LC

LC

LC

LC

LC

LC

XC4000E/EX

16x4 Dual- Port RAM

10 Logic Cells

Dual-Port Emulation

Logic

FLEX 10K emulation logic for small Dual-Port RAM consumes more logic cells than complete Xilinx solution

Resources to create arbitrary interconnection networks

Various types of interconnect

Flexible general-purpose interconnect

Low-skew long lines

Internal three-state buffers for buses and wide functions

CLB

CLB

CLB

CLB

SwitchMatrix

Programmable Interconnect

Interconnect Hierarchy

Global Clock BuffersClock Buffers are low-skew, high drive buffers

Also known as Global Buffers Drive low-skew, high-speed long line resources Drive all Flip-Flops and Latches in FPGA Can also be used for high-fanout signals Eight global buffers per FPGA

Additional clocks and high fanout signals can be routed on long lines

Otherwise routed on general interconnect– Slower and higher skew

Use Global Clock Buffers

Use clock buffers for highest fanout clocks Drive low-skew, high-speed long line resources Use BUFG primitive to be family-independent

Limit number of clocks to ease placement issues XC4000E: 8 XC4000X : 20 XC5000: 4

Additional clocks might be routable on long lines Otherwise routed on general interconnect Slower and higher skew

IPADBUFGS

D

Use Extra Global Buffers Do you have high fan-out Clock Enables, or IOB Tri-states?

Drive them through a unused BUFG to lower skew and higher performance

BUFGs have less than 1ns Skew to clock and CE inputs

Have to instantiate in HDL for non-clock signals

D

CE

Q

R

P CE or OEINPUT

CLOCK BUFG

Global Buffers Interconnect Flexibility on BUFGS allows any four of the eight to be available in

any column

All connect to clock pins, but only some connect to some of the other pins

PGCK1

PGCK2

PGCK4

PGCK3

SGCK1

SGCK4

SGCK2

SGCK3

PGCK4PGCK3PGCK2PGCK1

SGCK1SGCK4SGCK3SGCK2

How to use to Xilinx How to use to Xilinx Foundation ToolFoundation Tool

Integration of All Tools

• Hierarchy Browser allows for direct access to these files

• Message Window provides error and status messages

• Toolbar

• Project Flowchart provides automated data transfer

Library Manager

The command File>Project Libraries enables the user to associate other project libraries

To open the Library Manager, click on its icon

The Library Manager organizes all macros into libraries and enables the user to delete, copy, and rename macros

Some Useful Commands

Use the command File>Copy Project to copy an entire Foundation project directory

Use the command File>Project Type to change the design family in one step

Adding Symbols

• To start the Schematic Editor, click on its icon

• Select-and-Drag mode enables moving symbols, wires, and busses throughout the work area

• To add symbols to the schematic click on the Symbol Toolbox icon

• Scroll through the list to find a particular symbol, or enter it’s name at the bottom of the SC Symbols box

• Replicate symbols by clicking on the symbol while the Symbols Toolbox is still active

Wires and Buses

To draw wires, click on the Draw Wires icon and click on the two endpoints

To draw buses, click on the Draw Buses icon and click on the two endpoints

To name a bus, double click on the bus and enter the bus name and width

To name a wire, double click on the wire and enter the node name

Drawing Bus Taps Extend the bus vertically so

there will be sufficient room

Terminate the bus by double-clicking the right mouse button

Name the bus

Click on the bus taps icon

Click on the bus name (in green)

Place the taps by clicking on each of the destinations starting with the least significant bit

Every bus tap will be labeled automatically

Query/Find Window

Query lets the user scan through the schematic to determine connections

Select a symbol or wire in the schematic, and click on the Query Mode icon

This is useful when connecting or disconnecting symbols

The Find function helps the user locate signals, chips, and pins

Find is useful when looking for objects reported by the Alliance M1 Software

Name important nets so they are easy to find later

Adding Hierarchy Tie the project together with a top-level

schematic that includes macros from all the Foundation Design Entry Tools

As each element of the project is created, make a symbol to represent the macro so that it can be added to the top-level schematic

Before a symbol can be created to represent a schematic macro, the macro must contain I/O Terminals that represent ports on the symbol

To enter an I/O Terminal, click on its icon, enter the terminal name, select the type of port, place it, and wire it up.

Entering a Level of Hierarchy

To enter a lower level of hierarchy, click on the Hierarchy Push/Pop icon and double click on the symbol

To go back to a higher level of hierarchy, double-click on a blank area of the sheet.

To create a symbol for a schematic with I/O terminals, use the command: Hierarchy>Create Macro Symbol From Current Sheet

This will place a symbol in the project library so it can be added to the top-level schematic

Symbol Properties Attributes and parameters

communicate necessary information to the Alliance M1 Software

Attributes and parameters are maintained in the Symbol Properties dialog box

Double-click on a symbol to enter the Symbol Properties dialog box

To make a pin assignment, double-click on the OPAD symbol, enter “LOC” in the name box and enter P49 in the description box

Symbol Editor

To edit a symbol, click on the Symbol Editor button inside the Symbol Properties dialog box

The Symbol Editor can be used to move ports around on a symbol so the schematic looks good

Importing Viewlogic Schematics

Viewlogic schematics can be imported into the Foundation schematic editor by using the command File>Import Viewlogic Schematic from the Schematic Editor

Some properties of the schematic can be modified

Importing a Viewlogic Schematic can maintain hierarchy and many of the schematics characteristics

Some Useful Commands

Add VCC and GND symbols by using the SC Symbols box

Sheet size can be changed by using the menu command File>Page Setup

To modify the grid, text, and colors use the menu command View>Preferences

Edit the Table printed at the bottom of every schematic page by using the menu command File>Table Setup

Zoom in, out, area, and to page by using their icons

LogiBLOX

LogiBLOX is a graphical interactive tool for creating high-level modules

LogiBLOX customizes components

The GUI disables selections that are incompatible with your design selections

LogiBLOX components are entered just like a macro

Functional simulation is possible without implementation

XC4000E/XL/XL support

Module Types

• Clock Dividers• Comparators• Data Registers• Inputs/Outputs• Memories• Shift Registers• Simple Gates• Tristate Buffers

• Adders• Subtracters• Counters• Constants• Pads• Multiplexers• Decoders

Counters

Choosing a style will determine the resources used for the module

For example, choosing the Maximum Speed option tells the software to use the Carry Logic resources if an XC4000EX FPGA has been selected

The Counters module can be binary, Johnson, LFSR, or One-Hot encoded

Adder/Subtracters

All arithmetic functions can utilize the Carry Logic resources

Adders/Subtracters, Accumulators, and the Comparators modules can be customized for signed/unsigned binary

Memories

The Memories module is useful for creating custom sized RAM, ROM, or dual-port RAM

This module will create the input decoder and output multiplexer when necessary

Specify the necessary bus width and memory depth to customize the size

Enter a memory filename to initialize a memory (for example, tenths.mem)

Multiplexers

The Multiplexer module can have up to eight input buses

This module can be optimized for area and speed

The Mux module can utilize the tristate buffers by selecting the Wired-AND Style

Tri-state Buffers

This module synthesizes internal non-inverting tri-state buffers

The output enable is active-low

If an inversion is necessary add an inverter to the output enable

One or two pull-up resistors can be used to get faster transition times

Inputs/Outputs

The Inputs/Outputs module represents the I/O block associated with each pin on a device

Using this module allows customizable bus widths and the use of the IOB register

Buffers can be bi-directional, latched, or registered

Pads

The Pads module represents the actual pins of a device

Location constraints can be entered for each element of a bus

The slew rate is set low by default to minimize power transients

The Delay attribute can provide 0ns hold time at the IOB register

The Pull-up/down attribute is used to prevent floating

Waveform Viewer

To open the Simulator, click on the Functional Simulator or the Timing Simulator icons

An implementation within the Alliance M1 software must be completed before a Timing Simulation can be completed

Contains a list of input and output nodes and an area for viewing the signals generated by the simulator

The simulator is controlled by the Simulator Toolbox

Inserting Probes

Add probes in the schematic to automatically load a node into the Waveform Viewer

Click on the Probes icon and click on each node name in the schematic

The probes change color in the schematic to reflect their state

Component Selector

Alternatively, open the Waveform Viewer, and enter nodes by using the Component Selector

Open the Component Selector by clicking on its icon in the Waveform Viewer

Stimulator Selector

Bc and NBc represent the normal and inverted outputs of a 16-bit counter

The square LEDs represent 16 user-defined formulas

The buttons labeled C1 - C4 represent user-defined clocks

The CS button is used with the graphical waveform editor to create a custom signal

To modify the clock frequency of the 16-bit counter, use the command Options>Preferences

Simulator Toolbox

Once the necessary signals have been inserted, the Step and Long buttons can be used to control the amount of time to simulate

The Forward and Reverse buttons are used to scan the waveforms for a particular event

The Power on Reset button moves the selector to the beginning of the simulation

Displaying Buses

To group signals, click on the MSB, hold the shift key, and click on the LSB. Then use the menu command Signal>Bus>Combine

To ungroup a bus, select the bus and use the menu command Signal>Bus>Flatten

To change the bus format, select the bus then use the menu command Signal>Bus>Display…

Any signals can be grouped within a bus

Some Useful Commands

To save simulation vectors, use the menu command File>Save Simulation State

To clear the waveform area, move the blue line to the beginning of the area to be deleted and use the menu command Waveform>Delete>All Waveforms after Cursor

To clear all waveforms in the viewer, click on the Delete Waveforms icon

To load a Viewlogic command file, use the command File>Run Script File