MARKET PERSPECTIVE: SEMICONDUCTOR … perspective: semiconductor trend of 2.5d/3d ic with optical...

MARKET PERSPECTIVE: SEMICONDUCTOR TREND OF 2.5D/3D IC WITH OPTICAL INTERFACES

PHILIPPE ABSIL, IMEC

OUTLINE

Market Trends & Technology Needs

Silicon Photonics Technology

Remaining Key Challenges

Conclusion

OPTICAL VS. COPPER INTERCONNECTS TRANSITION ROADMAP

Link distance

COPPER INTERCONNECT

Copper

Optical

? 1Tbps/mm

100Gbps/mm

10Tbps/mm

I/O Density

100Tbps/mm

10Gbps/mm

Backplane Board-to-board [0.5m-3m]

Source: LightCounting

10G

50G

100G

...

25G

Nx50/100G

Package/Chip Logic Core-Core,

Logic-DRAM [1mm-5cm]

1cm

Board Logic Package-to-Package

Logic-DRAM array [5cm-0.5m]

Source: Intel

1 Mbps

1 Tbps

1 Gbps

1 Pbps

IT System Scaling requires

Scalable Optical Interconnects

Datacenter [5m-10km+] 100G-400G-1T+ Backplane [0.5-3m]

(N x) 50G-100G+ Board [5-50cm]

200Gbps+/mm Package or Chip [1mm-5cm]

10Tbps+/mm

10G

100G

40G

400G

800G

1.25G

...

2.5G

Intra-Datacenter Rack-to-Rack [5m-500m+]

Telecom [10km+]


200G

1.6T

100G

400G

800G

...

200G

1.6T

3D Technologies enables “local” interconnect scaling

3

3D Application Example Industry Implementation

Interposer stacking (“2.5D”)

Xilinx: 3D FPGA Virtex-7 2000T

Memory stacking Advanced DRAM

Micron: Hybrid Memory Cube

3D TECHNOLOGIES ENABLES ON-BOARD INTERCONNECT SCALING

AMD: Graphics

Radeon R9 FURY X

TechInsites

SystemPlus

SK Hynix: High Bandwidth Module

Samsung: 128GB 3D DDR4 RDIMM

Xilinx: Heterogeneous 3D

FPGAVirtex-7 H580T

OPTICAL VS. COPPER INTERCONNECTS TRANSITION ROADMAP

Link distance

COPPER INTERCONNECT

Copper

Optical

? 1Tbps/mm

100Gbps/mm

10Tbps/mm

I/O Density

100Tbps/mm

10Gbps/mm

Backplane Board-to-board [0.5m-3m]


10G

50G

100G

...

25G

Nx50/100G

Package/Chip Logic Core-Core,

Logic-DRAM [1mm-5cm]

1cm

Board Logic Package-to-Package

Logic-DRAM array [5cm-0.5m]

Source: Intel

1 Mbps

1 Tbps

1 Gbps

1 Pbps

IT System Scaling requires

Scalable Optical Interconnects

Datacenter [5m-10km+] 100G-400G-1T+ Backplane [0.5-3m]

(N x) 50G-100G+ Board [5-50cm]

200Gbps+/mm Package or Chip [1mm-5cm]

10Tbps+/mm

10G

100G

40G

400G

800G

1.25G

...

2.5G

Intra-Datacenter Rack-to-Rack [5m-500m+]

Telecom [10km+]


200G

1.6T

100G

400G

800G

...

200G

1.6T

Photonic Integration Is Key To Enable Global Interconnect Scaling, from within-rack to across-datacenters

5

CLOUD DATA CENTER NETWORK Building-wide Fiber Network

TODAY

40G

EMERGING (2016)

100G

NEAR FUTURE (2019E)

400G

FUTURE (2022E)

1T+

Building-wide rack-to-rack connectivity

Redundancy 100,000s fiber optic links

Up to 500m reach

Fiber cost is substantial CAPEX

Re-use fiber plant, upgrade optical ports

Data center network topology (Facebook)

WHERE IS THE PHOTONIC ?

Transceiver Needs

Scaling up the bandwidth

Scaling down the form factor

Scaling down the power consumption

Switch QSFP Transceiver

PHOTONICS: FROM THE PANEL INTO THE PACKAGE

Current Solution:

Stand-alone transceiver on front-panel

Scaling Step 1:

On-Board Transceiver

Scaling Step 2:

In-package Optical I/O

SMF

to network(1) Si Photonics Module on the Board

PCB

SMF

to network(2) Si Photonics Module in the Package

PCB

SiPh moduleLogic die

SMF

to network(1) Si Photonics Module on the Board

PCB

SMF array connector

PHOTONIC INTEGRATION ENABLES BEYOND THE BOARD INTERCONNECT SCALING

INTEGRATION OF DIVERSE OPTICAL FUNCTIONS

Source: Infinera

Complete toolbox of active and passive optical functionality High performance optical devices and circuits

InP Photonic Integration =

9

Source: Jeppix

SILICON PHOTONIC INTEGRATION

Silicon PICs Fabrication in CMOS fabs [200mm/300mm]

Large Si/SiO2 refractive index contrast of ~2 [scalable PIC density]

Advanced Si patterning capability [193(i), nanometer scale accuracy]

(Si)Ge epitaxy [photodetectors/modulators]

Low resistance contacts to Si [high-speed optical devices]

Volume scalability [>1M units/year] & Efficiencies of scale [cost]

Wafer-scale 3-D packaging and assembly [TSVs, micro-bumps, ...]

No monolithic integrated optical gain/lasing [need for hybrid solution]

BENEFITS AND DRAWBACKS

Silicon Photonics = Leverage existing CMOS infrastructure for Photonic Integration

10

DATA CENTER TRAFFIC GROWTH Zettabyte Data Volumes

Cisco Global Cloud Index (2013-2018)

Zettabyte/year since 2013

Average CAGR = 32%, some reporting 50% CAGR

>75% of this data traffic stays inside the datacenter

MARKET FORECAST Evolution of market size for discrete and integrated Photonics transceivers

Reference: LightCounting OFC2016 Dinner Seminar

• Ethernet represents dominant market share, largely driven by Cloud Mega Datacenters

• Integrated photonics grows faster than discrete photonics, cross-over expected by 2018

• Steady growth for Si Photonics, however market share remains relatively modest (~$1B by 2021)

Optical Technology that combines performance of InP (single-mode) and cost of GaAs (multimode) with manufacturability and scalability of Si Photonics has tremendous market potential!

WHO IS DOING WHAT IN SILICON PHOTONICS ?

Press Announcement

GlobalFoundries presentation at Semicon West 2016, San Francisco

Press Announcement

Integration of Silicon Photonics Into DRAM Process Samsung technical paper at OFC 2013, Anaheim

OUTLINE




Conclusion

OPTICAL TRANSCEIVER SCALING

15

Faster Channels

More Channels • Parallel (Single-Mode) Fiber [PSM] • Multi-Core Fiber, Spatial Division Multiplexing [SDM] • Wavelength Division Multiplexing [WDM]

More Bits per Symbol • Amplitude: PAM-X • Phase and Amplitude: DP-QPSK, QAM-X, ...

25G

50G

100G

4l 8l

16l 1core

8core

16core

1-bit 1l

2-bit

4-bit PAM-16 (LightWire/Luxtera)

10G

J. Sakaguchi, et al, "19-core fiber transmission of 19x100x172-Gb/s SDM-WDM-PDM-QPSK signals at 305Tb/s," OFC2012, PDP5C.1.

Focus for very-short reach interconnects:

Faster and More Channels

MULTIPLE AXES

PSM

CWDM

DWDM SDM

Edge + Surface Couplers

Mach-Zehnder, MicroRing, GeSi Electro-Absorption Modulators

Ge (Avalanche) Photo-Detectors

WDM Filters

ARCHITECTURE DIVERSITY DRIVES PLATFORM AGILITY

KEY TECHNOLOGY FEATURES OF SILICON PHOTONICS

Leveraging CMOS Technology

Starting substrate: Silicon-On-Insulator (typ. 220nm Si / 2000nm BOX)

Multi-level Si patterning with 193nm (immersion) lithography

Silicon doping & Ge doping

Ge-on-Si RPCVD Epitaxy

Metal interconnects + Al bondpad

Deep-Si etch for edge coupling

III-V on silicon (bonding, epitaxy) for gain material

IMEC’S SILICON PHOTONICS PLATFORM Fully Integrated 8x50G DWDM Si Photonics Technology

Co-integration of the various building blocks in a single platform

Today available on 200mm wafer size, coming soon on 300mm

95% compatible with CMOS130 in commercial foundries

56G Ge Electro-Absorption Modulator

56Gb/s eye diagram

56G Silicon Ring Modulator

56Gb/s eye diagram

8+1-channel DWDM (De-)Multiplexing Filter In-Plane Coupler

Surface-Normal Coupler

50G Ge Photodetector 50Gb/s eye diagram

56G Silicon Mach-Zehnder Modulator

HYBRID CMOS SI-PHOTONICS TRANSCEIVER DEMO Putting it all together

40nm CMOS 4x20Gb/s Transceiver

28nm CMOS 50Gb/s Transmitter

WIREBOND CMOS SI-PHOTONICS RING TRANSMITTER DEMO

MEASUREMENT SETUP

SiPh die with ring modulator array

Wirebond

Fiber in

Polarization controller

Tunable Laser

(12dBm)

Fiber out

EDFA (6dB)

Sampling Oscilloscope 40GHz BW

Optical Filter

- 67GHz - 50Ω GSG probe

PPG + MUX 56 Gb/s

Wirebond

20

WIREBOND CMOS SI-PHOTONICS RING TRANSMITTER DEMO

EYE DIAGRAMS VS. POWER SUPPLY VDD

Driver supply: VDD=0.9V

Ebit = 420 fJ/bit 36Gb/s NRZ

36Gb/s NRZ, PRBS07

21

40Gb/s NRZ, PRBS07





50Gb/s NRZ, PRBS07

IMEC’S SILICON PHOTONICS OFFERING

Build your own Prototype in imec’s open platform technology!

Accessing imec’s 200mm Si Photonics Platform (iSiPP200)

Both MPW and Fully Dedicated Runs

Silicon Validated PDK v1.3 is available

Supported by various EDA tools

>8 Customer tape-outs since 2014, >10 planned in 2016

Interested? Get in touch! MPW http://www.europractice-ic.com/, Dedicated:

[email protected]

http://www.europractice-ic.com/





OUTLINE




Conclusion

THE MISSING PIECE: THE LASER

Option 1: Hybrid Bonding

Manufacturability

Reliability

Option 2: Epitaxy Efficiency not proven

Reliability

Option 3: Assembly Insertion loss

Scalability & Cost

MONOLITHIC LASERS ON SILICON Addressing extreme cost and performance targets

Epitaxial growth of III-V Lasers on Silicon

InP

Silicon

Array of 10 InP lasers under optical pumping

Wang, Nature Photonics, October 2015

LOW-COST PACKAGING

Challenge 1: Fiber Assembly

(sub-) micron alignment

Fiber through package

Challenge 2: Laser Assembly

(sub-) micron alignment

Metal pads

Emerging custom solutions but still far from standard OSAT operations

SAMTEC FireFly solution

OUTLINE




Conclusion

3D & Silicon Photonics Enable Future In-Package Optical I/O’s Silicon Photonics Ready For Low Voltage Operation at 50Gb/s and beyond Light Sources & Packaging Remain Challenging Investment Required !

THANK YOU!

MARKET PERSPECTIVE: SEMICONDUCTOR … perspective: semiconductor trend of 2.5d/3d ic with optical...

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