March 2004 Modified from the notes by Saeid Nooshabadi [email protected]

COMP3221 lec9-logical-I.1 Saeid Nooshabadi

COMP 3221

Microprocessors and Embedded Systems

Lecture 3: C/Assembler Logical and Shift http://www.cse.unsw.edu.au/~cs3221

March 2004

Modified from the notes by

Saeid Nooshabadi

[email protected]


Overview

° Bitwise Logical Operations• OR

• AND

• XOR

° Shift Operations• Shift Left

• Shift Right

• Rotate

• Field Extraction


Review: Assembly Variables: Registers° Assembly Language uses registers as

operands for data processing instructions

r0 r1 r2 r3 r r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15

Register No.a1a2a3a4v1v2v3v4v5v6v7v8ipsplrpc

Register NameAll register are identical in hardware, except for PCPC is the program Counter; It always contains the addressthe instruction being fetched from memoryBy Software convention we use different registers for different thingsC Function Variables: v1 – v7 Scratch Variables: a1 – a4


Review: ARM Instructions So far

add

sub

mov


Bitwise Operations (#1/2)

° Up until now, we’ve done arithmetic (add, sub, rsb) and data movement mov.

° All of these instructions view contents of register as a single quantity (such as a signed or unsigned integer)

° New Perspective: View contents of register as 32 bits rather than as a single 32-bit number


Bitwise Operations (#2/2)

° Since registers are composed of 32 bits, we may want to access individual bits rather than the whole.

° Introduce two new classes of instructions/Operations:

• Logical Instructions

• Shift Operators


Logical Operations° Operations on less than full words

• Fields of bits or individual bits

° Think of word as 32 bits vs. 2’s comp. integers or unsigned integers

° Need to extract bits from a word, or insert bits into a word

° Extracting via Shift instructions• C operators: << (shift left), >> (shift right)

° Inserting and inverting via And/OR/EOR instructions

• C operators: & (bitwise AND), | (bitwise OR), ^ (bitwise EOR)


Logical Operators° Operator Names:

•and, bic, orr, eor:

° Operands:• Destination : Register• Operand #1: Register• Operand #2: Register, or Shifted registers, or an

immediateExample: and a1, v1, v2

and a1, v1, v2, lsl #5 and a1, v1, v2, lsl v3 and a1, v1, #0x40

° ARM Logical Operators are all bitwise, meaning that bit 0 of the output is produced by the respective bit 0’s of the inputs, bit 1 by the bit 1’s, etc.


Logical AND Operator (#1/3)

° AND:Note that anding a bit with 0 produces a 0 at the output while anding a bit with 1 produces the original bit.

° This can be used to create a mask.• Example:

1011 0110 1010 0100 0011 1101 1001 1010

0000 0000 0000 0000 0000 0000 1111 1111• The result of anding these two is:

0000 0000 0000 0000 0000 0000 1001 1010

Mask:


Logical AND Operator (#3/3)° AND: bit-by-bit operation leaves a 1 in the result

only if both bits of the operands are 1. For example, if registers v1 and v2 are

0000 0000 0000 0000 0000 1101 0000 0000two

0000 0000 0000 0000 0011 1100 0000 0000two

° After executing ARM instructionand a1,v1, v2 ; a1 v1 & v2

° Value of register a10000 0000 0000 0000 0000 1100 0000 0000two


Logical BIC (AND NOT) Operator (#1/3)

° BIC (AND NOT):Note that bicing a bit with 1 produces a 0 at the output while bicing a bit with 0 produces the original bit.

° This can be used to create a mask.• Example:

1011 0110 1010 0100 0011 1101 1001 1010

0000 0000 0000 0000 0000 0000 1111 1111• The result of bicing these two is:

1011 0110 1010 0100 0011 1101 0000 0000

Mask:


Logical OR Operator (#2/2)° OR: bit-by-bit operation leaves a 1 in the result if

either bit of the operands is 1. For example, if registers v1 and v2

0000 0000 0000 0000 0000 1101 0000 0000two

0000 0000 0000 0000 0011 1100 0000 0000two

° After executing ARM instructionORR a1,v1,v2 ; a1 v1 | v2

° Value of register a10000 0000 0000 0000 0011 1101 0000 0000two


Logical XOR Operator (#1/2)

° EOR: Eoring a bit with 1 produces its complement at the output while Eoring a bit with 0 produces the original bit.

° This can be used to force certain bits of a string to invert.

• For example, if a1 contains 0x12345678, then after this instruction:

eor a1, a1, 0xFFFF

• … a1 contains 0x1234A987 (e.g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to invert).


Shift Operations (#1/3)° Move (shift) all the bits in a word to the left or

right by a number of bits, filling the emptied bits with 0s.

° Example: shift right by 8 bits

1001 0010 0011 0100 0101 0110 0111 1000

0000 0000 1001 0010 0011 0100 0101 0110

° Example: shift left by 8 bits

1001 0010 0011 0100 0101 0110 0111 1000

0011 0100 0101 0110 0111 1000 0000 0000


Shift Operations (#2/3)° Move (shift) all the bits in a word to the right

by a number of bits, filling the emptied bits with the sign bits.

° Example: Arithmetic shift right by 8 bits

1001 0010 0011 0100 0101 0110 0111 1000

1111 1111 1001 0010 0011 0100 0101 0110

0001 0010 0011 0100 0101 0110 0111 1000

0000 0000 0001 0010 0011 0100 0101 0110


Shift Operations (#3/3)° Move (shift) all the bits in a word to the right

by a number of bits, filling the emptied bits with the bits falling of the right.

° Example: rotate right by 8 bits

1001 0010 0011 0100 0101 0110 0111 1000

0111 1000 1001 0010 0011 0100 0101 0110


ARM Shift Instructions° ARM does not have separate shift instruction.

° Shifting operations is embedded in almost all other data processing instructions.

° Pure Shift operation can be obtained via the shifted version of mov Instruction.

° Data Processing Instruction with Shift Feature Syntax:

1 2,3,4,5 6• where

1) operation

2) register that will receive value

3) first operand (register)

4) second operand (register)

5) shift operation on the second operand

6) shift value (immediate/register)

Example:

add a1, v1,v3, lsl #8

;a1 v1 +(v3 << 8 bits)

add a1, v1,v3, lsl v4

;a1 v1 +(v3 << v4 bits)


ARM Shift Variants (#1/4)1. lsl (logical shift left): shifts left and fills emptied bits with 0s

mov a1, v1, lsl #8 ;a1 v1 << 8 bits

mov a1, v1, lsl v2 ;a1 v1 << v2 bits

2. lsr (logical shift right): shifts right and fills emptied bits with 0s

mov a1, v1, lsr #8 ;a1 v1 >> 8 bits

mov a1, v1, lsr v2 ;a1 v1 >> v2 bits

DestinationCF 0

Destination CF0

shift amount between 0 to 31



ARM Shift Variants (#2/4)3. asr (arithmetic shift right): shifts right and fills emptied bits by

sign extending

mov a1, v1, asr #8 ;a1 v1 >> 8 bits

;a1[31:24]=v1[31]

mov a1, v1, asr v2 ;a1 v1 >> v2 bits

;a1[31:24]=v1[31]

Destination CF

Sign bit shifted in



ARM Shift Variants (#3/4)4. ror (rotate right): shifts right and fills emptied bits by bits

falling of the right. (bits wrap around)

mov a1, v1, ror #8

;a1 v1 >> 8 bits

;a1[31:24] v1[7:0]

mov a1, v1, ror v2

;a1 v1 >> v2 bits

;a1[31:(31-v2)] v1[v2:0]

Rotate amount between 1 to 31

Destination CF


ARM Shift Variants (#4/4)4. rrx (rotate right through carry): This operation uses the CPSR

C flag as a 33rd bit for rotation. (wrap around through carry)

mov a1, v1, rrx ;a1 v1 >> 1 bit

;a1[31] CF

;CF v[0]

Destination CF

Rotate Right through Carry

•Only Rotation by one bit is allowed

•Encoded as ror #0.


Isolation with Shift Instructions (#1/2)

° Suppose we want to isolate byte 0 (rightmost 8 bits) of a word in a0. Simply use:

and a0,a0,#0xFF

° Suppose we want to isolate byte 1 (bit 15 to bit 8) of a word in a0. We can use:

and a0,a0,#0xFF00

but then we still need to shift to the right by 8 bits...

mov a0,a0,lsr #8


Isolation with Shift Instructions (#2/2)

° Instead, we can also use:

mov a0,a0,lsl #16mov a0,a0,lsr #24

0001 0010 0011 0100 0101 0110 0111 1000

0101 0110 0111 1000 0000 0000 0000 0000

0000 0000 0000 0000 0000 0000 0101 0110


Overview

° Shift Operations• Field Insertion

° Multiplication Operations• Multiplication

• Long Multiplication

• Multiplication and accumulation

• Signed and unsigned multiplications


Extracting a field of bits (#1/2)

° Shift field as far left as possible (9 31) and then as far right as possible (317)

° Extract bit field from bit 9 (left bit no.) to bit 2 (size=8 bits) of register v1, place in rightmost part of register a1

012345678931v1

0000 00000000000000000000 a1

00 00000000000000000000 a1

0000 00000000000000000000 a1

v1


Extracting a field of bits (#2/2) mov a1, v1, lsl #22 ;8 bits to left end (31-9)

00 00000000000000000000 a1

v1

mov a1, a1, lsr #24 ;8 bits to right end(7-0)

00 00000000000000000000 a1

0000 00000000000000000000 a1


Inserting a field of bits

° Shift left field 2 bits, Mask out field, OR in field

° Insert bit field into bit 9 (left bit no.) to bit 2 (size=8 bits) of register a1 from rightmost part of register v1 (rest is 0)

°mov a2, v1, lsl #2 ; field left 2 bic a1, a1, #0x3FC ; mask out 9-2

; 0x03FC = 0011 1111 1100orr a1, a1, a2 ; OR in field

0123456789310000 00000000000000000000 v1

a1

00000000 a1 masked

0000 00 000000000000000000 a2=v1<<2

a1 ored a2

; bic stands for ‘bit clear, where ‘1’ in the second operand clears ; the corresponding bit in the first


Bit manipulation in C (#1/2)

° Convert C code to ARM ASM

° Bit Fields in C (Word as 32 bits vs int/unsigned!)struct {

unsigned int ready: 1; /* bit 0 */unsigned int enable: 1; /* bit 1 */

} rec; rec.enable = 1;rec.ready = 0;printf(“%d %d“, rec.enable, rec.ready);...

rec

0131

enable

ready

Brian Kernighan & Dennis Ritchie: The C Programming Language, 2nd Ed., PP 150


Bit manipulation in C (#2/2)struct {

unsigned int ready: 1; /* bit 0 */unsigned int enable: 1; /* bit 1 */

} rec; /* v1 */rec.enable = 1;rec.ready = 0;printf(“%d %d“, rec.enable, rec.ready);

orr v1,v1, #0x2 ;1 in bit 1 bic v1,v1 #1 ;0 in bit 0,

ldr a1, =LCO ;printf formatmov a2, v1, lsr #1 ;just bit 1 and a2, a2,0x0001 ;mask down to 1and a3, v1, 0x0001 ;just bit 0 bl printf ;call printf

; bic stands for ‘bit clear, where ‘1’ in the second operand clears ; the corresponding bit in the first


Multiply by Power of 2 via Shift Left (#3/3)

° Since shifting is so much faster than multiplication (you can imagine how complicated multiplication is), a good compiler usually notices when C code multiplies by a power of 2 and compiles it to a shift instruction:a *= 8; (in C)

would compile to:

mov a0,a0,lsl #3 (in ARM)


Shift, Add and Subtract for Multiplication

Add and Subtract Examples:f = 5*g /* f = (4+1) x g */ (in C)

add v1,v2,v2 lsl #2 ; v1 = v2 + v2 *4 (in ARM)

f = 105 *g /* f = (15 x 7) x g */ (in C)

/* f = (16 –1 ) x (8 – 1) x g */

rsb v1,v2,v2 lsl #4 ; v1 = -v2 + v2 *16 (in ARM)

; f = (16-1)* g

rsb v1,v1,v1 lsl #3 ; v1 = -v1 + v1 *8 (in ARM)

; f = (8-1)* f


Shift, Add and Subtract for Division

• ARM does not have division.

• Division A/B produces a quotient and a remainder.

• It should be done via sequence of subtraction and shifting (See Experiment 3)

• For B in A/B a constant value (eg 10) simpler technique via Shift, Add and Subtract is available (Will be discussed later)


Shift Right Arithmetic; Divide by 2???° Shifting left by n is same as Multiplying by 2n

° Shifting right by n bits would seem to be the same as dividing by 2n

° Problem is signed integers• Zero fill is wrong for negative numbers

° Shift Right Arithmetic (asr); sign extends (replicates sign bit);

° 1111 1111 1111 1000 = -8° 1111 1111 1111 1100 = -4° 1111 1111 1111 1110 = -2° 1111 1111 1111 1111 = -1


Is asr really divide by 2?

° Divide +5 by 4 via asr 2; result should be 1

0000 0000 0000 0000 0000 0000 0000 0101

0000 0000 0000 0000 0000 0000 0000 0001

° = +1, so does work

° Divide -5 by 4 via asr 2; result should be -1

1111 1111 1111 1111 1111 1111 1111 1011

1111 1111 1111 1111 1111 1111 1111 1110

° = -2, not -1; Off by 1, so doesn’t always work

° Rounds to –


MULTIPLY (unsigned): Terms, Example° Paper and pencil example (unsigned):

Multiplicand 1000Multiplier 1001

1000 0000

0000 1000

Product 01001000•m bits x n bits = m+n bit product

•32-bit value x 32-bit value = 64-bit value


Multiplication Instructions° The Basic ARM provides two multiplication instructions.

° Multiply• mul Rd, Rm, Rs ; Rd = Rm * Rs

° Multiply Accumulate - does addition for free• mla Rd, Rm, Rs,Rn ; Rd = (Rm * Rs) + Rn

° (Lower precision multiply instructions simply throws top 32bits away)

° Restrictions on use:• Rd and Rm cannot be the same register

- Can be avoided by swapping Rm and Rs around. This works because multiplication is commutative.• Cannot use PC.

These will be picked up by the assembler if overlooked.

° Operands can be considered signed or unsigned• Up to user to interpret correctly.


Multiplication Example

° Example:• in C: a = b * c;

• in ARM:

- let b be v1; let c be v2; and let a be v3 (It may be up to 64 bits)

mul v3, v2, v1 ;a = b*c

; lower half of product into ; v3. Upper half is thrown up

° Note: Often, we only care about the lower half of the product.


Multiplication and Accumulate Example° One example of use of mla is for string to

number conversion: egConvert string=“123” to value=123

value = 0

loop = 0

len = length of string

Rd = value

while loop <> len

c = extract(string, len - loop,1)

Rm = 10 ^ loop

Rs = ASC(c) - ASC (‘0’)

mla Rd, Rm, Rs, Rd

loop = loop + 1

endwhile


Multiply-Long and Multiply-Accumulate Long

° Instructions are• MULL which gives RdHi,RdLo:=Rm*Rs • MLAL which gives RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo

° However the full 64 bit of the result now matter (lower precision multiply instructions simply throws top 32 bits away)

• Need to specify whether operands are signed or unsigned

° Therefore syntax of new instructions are:• umull RdLo,RdHi,Rm,Rs ;RdHi,RdLo:=Rm*Rs • umlal RdLo,RdHi,Rm,Rs ;RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo• smull RdLo, RdHi, Rm, Rs ;RdHi,RdLo:=Rm*Rs (Signed)• smlal RdLo, RdHi, Rm, Rs ;RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo (Signed)

° Not generated by the compiler. (Needs Hand coding)


Division° No Division Instruction in ARM

° Division has to be done in software through a sequence of shift/ subtract / add instruction.

• General A/B implementation (See Experiment 3)

• For B in A/B a constant value (eg 10) simpler technique via Shift, Add and Subtract is available (Will be discussed later)


Quiz

1. Specify instructions which will implement the following:

a) a1 = 16 b) a2 = a1 * 4

c) a1 = a2 / 16 ( r1 signed 2's comp.) d) a2 = a3 * 7

2. What will the following instructions do?a) add a1, a2, a2, lsl #2 b) rsb a3, a2, #0

3. What does the following instruction sequence do?add a1, a2, a2, lsl #1

sub a1, a1, a2, lsl #4

add a1, a1, a2, lsl #7


Quiz Solution (#1/2)

1. Specify instructions which will implement the following:a) a1 = 16 mov a1, #16

b) a2 = a1 * 4 mov a2, a1, lsl #2

c) a1 = a2 / 16 ( r1 signed 2's comp.) mov a1, a2, asr #4

d) a2 = a3 * 7 rsb a2, a3, a3, lsl #3

a2 = a3* (8-1)

whereas sub a2, a3, a3, lsl #3 would give a3* -7

2. What will the following instructions do?a) add a1, a2, a2, lsl #2

a1= a2+ (a2 * 4) ie a1:=a2*5

b) rsb a3, a2, #0

° r2=0-r1 ie r2:= -r1


Quiz Solution (#2/2)

3. What does the following instruction sequence do?add a1, a2, a2, lsl #1

sub a1, a1, a2, lsl #4

add a1, a1, a2, lsl #7

a1 = a2 + (a2 * 2) = a2 * 3

a1 = a1 - (a2 * 16)= (a2 * 3) - (a2 * 16) = a2 * -13

a1 = a1 + (a2 * 128) = (a2 * -13) + (a2 * 128)

= r1 * 115

i.e. a1 = a2 * 115

March 2004 Modified from the notes by Saeid Nooshabadi [email protected]

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Transcript of March 2004 Modified from the notes by Saeid Nooshabadi [email protected]