Map_K Dengan Kondisi Dont Care

C. E. Stroud Combinational Logic Minimization (9/12)

1

Karnaugh Maps (K-map) Alternate representation of a truth tableRed decimal = minterm value

Note that A is the MSB for this minterm numberingAdjacent squares have distance = 1

Valuable tool for logic minimizationApplies most Boolean theorems & postulates

automatically (when procedure is followed)B

A 0 101

0 12 3

2-variableK-Maps

B

A0 12 3form 1 form 2


2

Karnaugh Maps (K-map) Alternate forms of 3-variable K-mapsNote end-around adjacency

Distance = 1 Note: A is MSB, C is LSB for minterm

numberingBC

A 00 01 11 1001

0 14 5

3 27 6

B

C

A0 14 5

3 27 6

B

C

A

0 12 3

6 74 5

form 1

form 2

CAB

00

010 12 3

6 74 5

11

10

0 1


3

K-mapping & Minimization StepsStep 1: generate K-mapPut a 1 in all specified mintermsPut a 0 in all other boxes (optional)

Step 2: group all adjacent 1s without including any 0sAll groups (aka prime implicants) must be rectangular and

contain a power-of-2 number of 1s 1, 2, 4, 8, 16, 32,

An essential group (aka essential prime implicant) contains at least 1 minterm not included in any other groups

A given minterm may be included in multiple groupsStep 3: define product terms using variables common to

all minterms in groupStep 4: sum all essential groups plus a minimal set of

remaining groups to obtain a minimum SOP


4

K-map Minimization Example Z=A,B,C(1,3,6,7)Recall SOP minterm

implementation 8 gates 27 gate I/O

K-map results 4 gates 11 gate I/O

0 1 1 0

0 0 1 1

BCA 00 01 11 10

01

0 14 5

3 27 6

A B C ZRowvalue

0 0 0 0 00 0 1 1 10 1 0 0 20 1 1 1 31 0 0 0 41 0 1 0 51 1 0 1 61 1 1 1 7

Z=AC + ABAC

AC

AB

A

B

Note: this group not needed since 1s are already covered

essential primeimplicants


5

K-map Minimization Goals Larger groups:Smaller product terms

Fewer variables in commonSmaller AND gates

In terms of number of inputs

Fewer groups:Fewer product terms

Fewer AND gates Smaller OR gate

In terms of number of inputs

Alternate method:Group 0s

Could produce fewer and/or smaller product terms

Invert output Use NOR instead

of OR gate


6

4-variable K-maps Note adjacency of 4 corners as well as sides Variable ordering for this minterm numbering: ABCD

form 2

0 14 5

3 27 6

12 138 9

15 1411 10

D

C

B

A

form 1

CDAB 00 01 11 10

00

01

11

10

0 14 5

3 27 6

12 138 9

15 1411 10


7

5-variable K-map Note adjacency between maps when overlayeddistance=1

Variable order for this minterm numbering:A,B,C,D,E (A is MSB, E is LSB)

BC 00 01 11 1000

01

11

10

0 14 5

3 27 6

12 138 9

15 1411 10

DE

A=0

BC 00 01 11 1000

01

11

10

16 1720 21

19 1823 22

28 2924 25

31 3027 26

DE

A=1


8

5-variable K-map Changing the variable used to separate maps

changes minterm numbering Same variable order for this minterm numbering:A,B,C,D,E (A is MSB, E is LSB)

AB 00 01 11 1000

01

11

10

0 28 10

6 414 12

24 2616 18

30 2822 20

CD

E=0

AB 00 01 11 1000

01

11

10

1 39 11

7 515 13

25 2717 19

31 2923 21

CD

E=1


9

6-variable K-map Variable order for minterm numbers: ABCDEF

CD 00 01 11 1000

01

11

10

0 14 5

3 27 6

12 138 9

15 1411 10

EF

B=0

CD 00 01 11 1000

01

11

10

16 1720 21

19 1823 22

28 2924 25

31 3027 26

EF

B=1

A=0

A=1

CD 00 01 11 1000

01

11

10

32 3336 37

35 3439 38

44 4540 41

47 4643 42

EFCD 00 01 11 10

00

01

11

10

48 4952 53

51 5055 54

60 6156 57

63 6259 58

EF


10

Dont Care Conditions Sometimes input combinations are of no concernBecause they may not exist

Example: BCD uses only 10 of possible 16 input combinationsSince we dont care what the output, we can use these

dont care conditions for logic minimization The output for a dont care condition can be either 0 or 1

WE DONT CARE!!! Dont Care conditions denoted by:X, -, d, 2

X is probably the most often used

Can also be used to denote inputsExample: ABC = 1X1 = AC

B can be a 0 or a 1


11

Dont Care Conditions Truth Table K-map MintermZ=A,B,C(1,3,6,7)+d(2)

MaxtermZ=A,B,C(0,4,5)+d(2)

Notice Dont Cares are same for both minterm & maxterm

0 1 1 X

0 0 1 1

BCA 00 01 11 10

01

0 14 5

3 27 6

A B C Z0 0 0 00 0 1 10 1 0 X0 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1

Z=B+AC

Z=AC + BAC

ACA

B

Circuit analysis:G=3 GIO=8(compared to G=4 & GIO=11 w/o dont care)


12

Design Example Hexadecimal to 7-segment display decoderA common circuit in calculators7-segments (A-G) to represent digits (0-9 & A-F)

A logic 1 turns on given segment

Hex to7-segment decoder

In3

In2

In1

In0

ABCDFFG Circuit block diagram

7 segmentsactive (on) segments

for a given HEX value

A

B

C

D

E

F

G

= dont care


13

HEX to 7-seg Design Example Create truth table from specification

In3 In2 In1 In0 A B C D E F G0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 1 0 1 1 1 1 10 1 1 1 1 1 1 0 0 X 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 X 0 1 11 0 1 0 1 1 1 0 1 1 11 0 1 1 0 0 1 1 1 1 11 1 0 0 1 0 0 1 1 1 01 1 0 1 0 1 1 1 1 0 11 1 1 0 1 0 0 1 1 1 11 1 1 1 1 0 0 0 1 1 1

A

B

C

D

E

F

G

= dont care


14

HEX to 7-seg Design Example Generate K-maps & obtain logic equations

In3 In2 In1 In0 A B C D E F G0 0 0 0 1 1 1 1 1 1 00 0 0 1 0 1 1 0 0 0 00 0 1 0 1 1 0 1 1 0 10 0 1 1 1 1 1 1 0 0 10 1 0 0 0 1 1 0 0 1 10 1 0 1 1 0 1 1 0 1 10 1 1 0 1 0 1 1 1 1 10 1 1 1 1 1 1 0 0 0 01 0 0 0 1 1 1 1 1 1 11 0 0 1 1 1 1 0 0 1 11 0 1 0 1 1 1 0 1 1 11 0 1 1 0 0 1 1 1 1 11 1 0 0 1 0 0 1 1 1 01 1 0 1 0 1 1 1 1 0 11 1 1 0 1 0 0 1 1 1 11 1 1 1 1 0 0 0 1 1 1

1 1 1 1

1 0 1 0

1 1 0 1

0 1 0 0

00 01 11 1000

01

11

10

In3 In2In1 In0

1 0 1 1

0 1 1 1

1 1 0 1

1 0 1 1

00 01 11 1000

01

11

10

In3 In2In1 In0

A = In2In0 + In3In1 + In2 In1+ In3 In0 + In3In2 In0 + In3 In2In1

B = In2In0 + In2In1 + In3In1In0+ In3 In1In0 + In3In1 In0

K-map forA output

K-map forB output


15

HEX to 7-seg Design Example K-maps & logic equations for outputs C-G

1 0 0 1

0 0 0 1

1 0 1 1

1 1 1 1

00 01 11 1000

01

11

10

In3 In2In1 In0

K-map for E output

1 0 0 0

1 1 X 1

1 1 1 1

1 0 1 1

00 01 11 1000

01

11

10

In3 In2In1 In0

K-map for F output

C = In3 In2 + In1In0 + In2In1 + In3In0 + In3In2D = In3In2In0 + In2In1 In0 + In2 In1In0

+ In3 In1 + In2 In1 In0E = In2In0 + In3 In2 + In1 In0 + In3 In1F = In1In0 + In3 In2 + In2 In0 + In3 In1 + In3In2G = In3 In2 + In1 In0 + In3 In0 + In3In2 In1 + In2In1

K-map for G output

0 0 1 1

1 1 0 1

1 1 1 1

0 1 1 1

00 01 11 1000

01

11

10

In3 In2In1 In0

1 1 1 0

1 1 1 1

1 1 1 1

0 1 0 0

00 01 11 1000

01

11

10

In3 In2In1 In0

K-map for C output

1 0 1 1

0 1 0 1

1 X 1 0

1 1 0 1

00 01 11 1000

01

11

10

In3 In2In1 In0

K-map for D output


16

HEX to 7-seg Design Example Remaining steps to complete design:Draw logic diagram (sharing common gates)

Analyze for optimization metirc: G, GIO, Gdel, PdelSee next page for logic diagram & circuit analysis

Simulate circuit for design verification Debug & fix problems when output is incorrect

Check truth table against K-map populationCheck K-map groups against logic equation product termsCheck logic equations against schematic

Optimize circuit for area and/or performance Use Boolean postulates & theorems

Re-simulate & verify optimized design


17

HEX to 7-seg Design ExampleIn2 In2

In1 In1

In0 In0

In3 In3

In2In0 G1

In3In2 G6

In3In1 G2

In2In1 G3

In3In0 G4

In2In1 G5

In1In0 G7

In3In2 G8

In1In0 G9

In3In0 G10

In3In2 G11

In3In1 G12

In2In0 G13

In3In0 G14

In2In1 G15

In3In2In0

G17

In1In0 G16

In3In2In1

G18

In3In1In0

G19

In3In1In0

G20

In3In1In0

G21

In3In2In0

G23

In2In1In0

G24

In3In2In1

G27

In2In1In0

G25

In2In1In0

G26

A

G1G2G3G4G17G18

B

G1G5G19G20G21C

G6G7G5G10G11

D

G22G23G24G25G26E

G1G8G9G12

F

G6G11G12G13G16

G

G6G9G14G15G27

Circuit AnalysisG = 38 GIO = 141Gdel = 3 Pdel = 30

worst case path: In0In0G1 A

1+8

1+7

1+9

1+92+3

2+1

2+1

2+1

2+1

2+3

2+1

2+1

2+1

2+1

2+2

2+2

2+1

2+1

2+1

2+1

3+1

3+1

3+1

3+1

3+1

3+1

2+1

3+1

3+1

3+2

3+1

6+0

5+0

4+0

5+0

5+0

5+0

5+0

Prop delay in gates#inputs + # loads9

9

9

9

In3In1 G22

# loadson PIs

Map_K Dengan Kondisi Dont Care

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