Manufacturing Monolithic Integrated Photonics · Design Automaon Mul-Project Wafer and Assembly...
Transcript of Manufacturing Monolithic Integrated Photonics · Design Automaon Mul-Project Wafer and Assembly...
Manufacturing Monolithic
Integrated Photonics
Lionel C. Kimerling PSMC- AIM Photonics Webinar Series October 20, 2015 http://photonicsmanufacturing.org/
Definethedifficultchallenges.Createthepoten6alsolu6ons.
LeadershipRobertC.Pfahl,Jr,iNEMI,PrincipalInves;gator,PSMCLionelC.Kimerling,MIT,PrincipalInves;gator,PSMCJimMcElroy,iNEMI,Execu;veDirector,PSMCTechnologyWorkingGroups
§ MonolithicIntegra9on:LionelC.Kimerling,MIT§ DataCenterEmulator:BobPfahl,iNEMI§ IoTEmulator:RichardGrzybowski,MACOM§ EmulatorCostModeling:ElsaOliveOandRandolphKirchain,MIT§ PhotonicsPackaging:BillBoPoms,ThirdMillenniumTestSolu;ons§ Boards,Backplanes,Connectors:JohnMacWilliams,USCompe;tors§ AssemblyandTest:DickOPe,PromexIndustries
WeeklyWebinarSeriesbeginningOctober20RoadmapReleaseonDecember7
ThePhotonicSystemsManufacturingRoadmap
AIMPhotonicsProprietary 1
AgreementtomergethisRoadmapintoAIM’sIPTRMorethan125companiespar:cipatedin2015
NISTAMTech
Distribu;onA:ClearedforPublicRelease 2Distribu;onA:ClearedforPublicRelease
AmericanIns:tuteforManufacturingIntegratedPhotonics
Datacom/Telecom Sensing
PICArrayTechnologies RFPhotonics
KeyTechnologyManufacturingAreas
Manufacturinginnova9onCentersofExcellence
Electronic-PhotonicDesignAutoma:on
Mul:-ProjectWaferandAssembly
InlineControlsandTest
TestAssemblyandOp:calPackaging
Vision:Establishatechnology,businessandeduca;onframeworkforindustry,governmentandacademiatoacceleratethetransi6onofintegratedphotonicsolu6onsfrominnova6ontomanufacturing-readydeploymentinsystems.
Integratedphotonicsallowsdesignersandmanufacturerstoputthousandsofphotoniccomponentstogetheronasinglechip:providingsignificantreduc;onsinsize,weight,andpower;whiledrama;callyimprovingperformanceandreliability.
Lead:AmericanIns;tuteforManufacturingIntegratedPhotonics(AIMPhotonics)(ResearchFounda;onSUNY)Established:July2015Hubloca9on:NewYorkFunding:$110Mfederalinvestmentcombinedwith~$500MIndustry/StatecostshareMembers:55companies,21States,20universi;es,33CommunityColleges,16otherorganiza;ons
Monolithic Integration TWG Charter
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The goal of the Monolithic TWG is to: • Evaluate the imperative for future technologies to
employ highly integrated photonic systems. • Catalog the Technology Roadmap for Integrated
Photonics Technology. • Identify Roadblocks and potential Show-Stoppers
holding back these developments. • Communicate this information to the industry supply
chain, the AIM program and its stakeholders. • Continue to catalog this evolving technology roadmap
as more is known about the strategic imperative for integrated silicon photonics technology & manufacturing in the US.
Monolithic Integration TWG Membership
• Lionel Kimerling, MIT • Corentin Monmeyran (Scribe), MIT • Mark Webster, Cisco • Luca Alloatti, MIT • George Celler, SOITEC, retired • Pieter Dumon, IMEC, Luceda • Madeleine Glick, U Arizona • Mark Beals, MIT • Richard Grzybowski, MACOM • Irene Sterian, Celestica • Jeff Shainline, NIST • Mark Wade, MIT • Jurgen Michel, MIT • Michael Watts, MIT • Dirk Englund, MIT • Anuradha Agarwal, MIT • David Bishop, Boston University
• Kal Shastri, Cisco • Alice White, Boston University • Jonathan Klamkin, BU/UCSB • Bill Bottoms, 3MTS • Anthony Ley, Harmonic emeritus • Ram Rao, Oclaro • Jiashu Chen, Finisar • Haisheng Rong, Intel, • Richard Otte, Promex • Philip Lippel, MIT • Rob Stone, Broadcom • John Bowers, UCSB • Robert Blum, Oclaro • Chris Weaver, MIT • Caroline Ross, MIT • Juejun Hu, MIT • Alan Benner, IBM • Nicholas Ilyadis, Broadcom • Haifeng Liu, Intel
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MONOLITHIC INTEGRATION
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INTRODUCTIONSITUATIONANALYSISDESIGNTOOLSMANUFACTURINGEQUIPMENTMANUFACTURINGPROCESSESMATERIALSQUALITY/RELIABILITYENVIRONMENTALTECHNOLOGYTEST,INSPECTION,MEASUREMENT(TIM)ROADMAPOFQUANTIFIEDKEYATTRIBUTENEEDSCRITICAL(INFRASTRUCTURE)ISSUESTECHNOLOGYNEEDSPRIORITIZEDRESEARCHNEEDS(>5YEARSRESULTS)PRIORITIZEDDEVELOPMENTANDIMPLEMENTATIONNEEDS(<5YEARSRESULTS)GAPSANDSHOWSTOPPERSRECOMMENDATIONSONPOTENTIALALTERNATIVETECHNOLOGIESCONTRIBUTORS
Key Roadmap Attributes
• Cost ($/Gb/s) • Energy (pJ/bit) • Bandwidth density (Gb/cm2) • Reach (cm) • Critical Dimension for each device (nm) • Interface/Sidewall rms and p-p roughness (nm) • Thermo-optic spectral stability for each device
(pm/K) • Integration level (devices/cm2) • Production capacity (wafer starts per week) • Impedance matching (FP oscillation amplitude
in S/N) • Latency (ns) • Coupled Photodetector responsivity (A/W) • Coupled Photodetector saturation level (mW) • Coupled Photodetector response time (pS) • Coupled Modulator extinction/insertion-loss
(dB/dB)
• Coupled Modulator efficiency (dB/V) • Coupled Laser threshold current (mA) • Coupled Laser threshold current
temperature stability (mA/K) • Coupled Laser slope efficiency (W/A) • Waveguide transmission loss (dB/cm) • I/O coupling loss (dB/interface, dB/chip) • Matrix switch capacity (ports-in x ports-out) • I/O port count (ports, channels/port, Gb/s/
channel) • I/O capacity (Gb/s for packaged chip) • Yield (die and line) • Reliability (MTTF, FIT) • Time-to-Market (design to production:
months) • Design (simulation, automation) • Layout (automation to tapeout) • Inspection (in-situ, in-line, throughput) • Package (thermal, BW density) • Test (throughput, BIST)
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2035: cost decrease of 1,000,000x
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HarmDorren,TUE
A Major Information Technology Transition performance scaling of 1000x/10yr at constant cost
Server market reaching maturity at ~10M units/yr. – Center of power shifted from OEMs to large end users – Virtualization could reduce hardware 10:1 – Microservers could reduce system size 10:1 – Constraints: Cost, Energy, and Bandwidth Density
• Will the IP Router survive to 2020? • Will ToR Switches survive to 2020? • Will the Rack and Blade Server survive to 2020? • Will the E-O-E transceiver survive to 2020?
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Deployment of Optical Interconnection Design Rule: photonics at BxD=1Tb/s x cm
Monolithic, chip-level photonic integration: solution to cost, energy, bandwidth density.
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Silicon Photonics CMOSFET-PhotonicIntegra9onScenarios
900
<550
<450
750*
SiGe
SiGe
SiCMOS FEOL BEOL
Siliconistheonlyplagormcapableofhighvolume,highdensityelectronic-photonicintegra;on.
The First Silicon Photonics Process Flow BAE Manassis Fab, 2005
Edge View Silicon
Waveguides & Vertical Coupler
α-Silicon
SOI BOX
xtal-Silicon CVD-SiO2
Side View
λ in λ out
SiGe
Ge growth, CMP & Top electrode
vertical coupler
butt coupler
p+ region
n+ region
Vertical I/O couplers
n+ contact
p+ contacts
SiGe
p
n
λ
λ
Butt coupler
Edge View
Contacts & Interconnect
p+ region
n+ region
0.6um
Waveguide Integrated Devices in CMOS
Everything improves with integration: speed, power efficiency and functionality.
50 nm Ge
Si Two Step Ge-on-Si CVD Ge “Damascene
communications technology roadmap
Silicon Microphotonics § The transceiver is the near term driver for silicon
microphotonics. § Silicon is the only material platform capable of supporting
a standard cross-market, high-volume transceiver in the long term.
§ Initial optical cabling applications will be multimode; but board, module and chip level interconnection will be single mode.
§ A WDM standard of ~20Gb/s per channel will optimize the tradeoff between power efficiency and aggregate bandwidth density.
§ An independent optical power supply will be the dominant architecture in the near term.
12 CTR II TWG Report, 2009
communications technology roadmap
Interconnection and Packaging
§ Optical pins will be needed within the next decade to address EMI and pin count issues.
§ Multimode and short wavelengths (800-900 nm) will dominate board-level optical interconnects through the next decade.
§ WDM will be necessary to meet off-chip bandwidth needs by 2020: single-mode, long wavelength (1300-1600 nm) will be the standard.
§ For large volume commercial applications, transceiver chips will stand alone from signal processing chips during the next decade; and they will become monolithically integrated thereafter for chip-to-chip interconnection.
13 CTR II TWG Report, 2009
Emerging Front Panel Bandwidth Limits
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NicholasIlyadis,Brioadcom
Strategy: Photons Closer to the Chip
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NicholasIlyadis,Brioadcom
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Ver;callyIntegratedFirmsnolongerexistConsor6aandOpenSourcePlaNormStandardization
Majorca@MIT:MassimilianoSalsi,Juniper
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Silicon Photonics for Disaggregation
In Jan. 2013, Intel announced a collaboration with Facebook on a new disaggregated, rack-scale server architecture that enables independent upgrading of compute, network and storage subsystems
The disaggregated rack architecture includes Intel’s new photonic architecture, based on high-bandwidth, 100Gbps Intel® Silicon Photonics Technology, that enables fewer cables, increased bandwidth, farther reach and extreme power efficiency compared to today’s copper based interconnects.
Mezzanine Options
Intel Ethernet chip and Intel Silicon Photonics
Optical PCIe via Intel Silicon Photonics
Intel® Xeon ® processor based tray
Mezzanine fiber
Intel® AtomTM
Micro-server tray
Source:Jus6nRaTner,Intel
18 Majorca@MIT:RichJensen,Pola6s
Interconnection Paradigm Shifts
Paradigm-shifting technologies will occur above the connector industry in the OEM ranks: new connectors and cable assembly applications as required by these new system-level developments. • One connector paradigm would be the introduction of
production automation for a future low cost optical “USB” connector with silicon photonics.
• Commercial HVM of Silicon Photonic ASICs and CPUs – accelerated shift of optical interconnect and packaging inside the box.
• Commercial HVM Silicon Photonic Chip Packaging – based on System-in-Package/3D packaging technology
• Commercial HVM Optical PCB Technology
Challenges: Monolithic Integration TWG
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• Light Source • Process Tools (193nm litho, 65nm CMOS) • Universal E-P CAD for photonic integration • E-P process integration • Power distribution • Athermal devices • Wafer-level inspection and test • Scalable (single mode, E-P) packaging
solution • Throughput, Yield and Reliability
Monolithic Silicon Microphotonics Roadmap
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E-Phybrid
MatrixSwitch
Embedded
Embedded
Embedded
Comm/Comp/Sense/Image Embedded
$0.01/Gbps
128Tbps
SmallCommercialDemandforTechnicallyViableOp;calSolu;ons
NoTechnicallyViableOp;calSolu;onsExist
Func;on
TxRx
Processor
Cost
BWdensity
Energy
ReachChip-escapeDataRate
NOW NEXT LIMITS
8x8 32x32
$1/Gbps $0.1/Gbps
30Tb/s/cm2(PETRA)
10pJ/b
1000km 100m 1cm
40Gbps 400Gbps
CommerciallyViableOp;calSolu;onsDeployed
WDMcoherent
SignalCondi;oning FFT
1pJ/b 100fJ/b
RF Photonic Filter with Coherent Detection
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Metrics:Spurious-FreeDynamicRange(SFDR),NoiseFigure(NF),Gain• Reduceop9callosses:integratedmodulatorandwaveguideloss<1dB/cm.• PowerHandlingandLinearityaremoreimportantthanBandwidth.• AlowRINnoise(Rela;veIntensityNoise)signallaserisimportant.
RF-photonicsystem-on-chip:400filtersona2x2.5cmre6cle
BlockdiagramofRF-Photonicfilterimplementedwithcoherentdetec;on
Gaps and Show Stoppers Reduce cost 2x to 5x in relatively mature technologies.
– Applications in the 100K to 10M needed to automate designs.
• 2015-18: Existing hodge-podge of proprietary, company-specific and standard interconnect designs, which do fulfill existing applications, if at a high cost.
• 2018-20: Evolution of Standards based on an interim Hybrid Approach to Photonic Chip Packaging
• 2020-25: Heterogeneous silicon photonics solutions with advanced 3D Packaging
• 2025-35: Monolithic Integration resulting in Single Chip or Complex 3D Chip Solutions with Minimal Outboard photonic Interconnect at the System Level.
JohnMacWilliams,USCompe6tors
Silicon Microphotonicsmanufacturing,performanceandbusiness
siliconphotonicsis“future-proof”
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Scalingwithastandard,modularplagorm:• increases:yield,reliability,density• reduces:cost,6metomarket,power,latency
Next PSMC Webinar in Series
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Abstract: The next webinar will discuss the iNEMI Roadmapping Process used to identify the cost, performance, and size needs of the end user for two key market segments-data centers and the internet of things. It will also discuss the methodology used to determine manufacturing processes that can achieve the cost objectives. • 10/27 Data Center, IoT, and Cost Modeling TWGs
– Robert Pfahl – Richard Grzybowski – Randolph Kirchain and Elsa Olivetti
Following PSMC Webinar in Series
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Abstract: The last three webinars will present the manufacturing technology and design needs to achieve low-cost, high-volume manufacturing of integrated photonic systems that have been identified and quantified to date. • -11/3 Photonic System Packaging TWG
– Wilmer Bottoms • -11/10 Interconnection TWG
– John L. MacWilliams • -11/17 Assembly and Test TWG
– Richard Otte