Manual Ec1 New

PARISUTHAM INSTITUTE OF TECHNOLOGY AND SCIENCE

DEPT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ANNA UNIVERSITY CHENNAI

REGULATION 2013

II YEAR/ III SEMESTER

EC6311-ANALOG AND DIGITAL CIRCUITS LABORATORY

LAB MANUAL

PREPARED BY APPROVED BYMs.B.KRUTHIKA/AP/ECE Prof. G. MARY AMIRTHA SAGAYEE

Mr.P.BRIGHT PRABAHAR/AP/ECE HOD/ECE

1

S.No CONTENT PAGE NO.

1 Syllabus 3

2 Lab Course Handout 5 3 Bread board connection 6 4 Ex. No. Experiments Analog Lab

5 1a Frequency Response of CE 8

6 1b Frequency Response of CB 12

7 1c Frequency Response of CC 16

8 2 Frequency response of CS Amplifiers 19

9 3 Darlington Amplifier 23

10 4 Differential Amplifiers- Transfer characteristic, CMRR Measurement 26

11 5a Cascade amplifier 29

12 5b Cascode amplifier 32

13 6 Spice Simulation of Common Emitter and Common Source amplifiers 35

14 Experiments Digital Lab15 7 Code converters using logic gates 37

16 8 4 bit binary Adder/ Subtractor and BCD adder using IC 7483 43

17 9 Multiplexer and De-multiplexer using logic gates 48

18 10 Encoder and Decoder using logic gates 53

19 11 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 57

20 12 3-bit synchronous up/down counter 62

21 13 SISO, SIPO, PISO and PIPO shift registers using Flip- flops 66

2

SYLLABUS

LIST OF ANALOG EXPERIMENTS

1. Frequency Response of CE / CB / CC amplifier

2. Frequency response of CS Amplifiers

3. Darlington Amplifier

4. Differential Amplifiers- Transfer characteristic, CMRR Measurement

5. Cascode / Cascade amplifier -Determination of bandwidth of single stage and multistage

amplifiers.

6. Spice Simulation of Common Emitter and Common Source amplifiers

LIST OF DIGITAL EXPERIMENTS

7. Design and implementation of code converters using logic gates

8. BCD to excess-3 code and vice versa ,Binary to gray and vice-versa

9. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483

10. Design and implementation of Multiplexer and De-multiplexer using logic gates

11. Design and implementation of encoder and decoder using logic gates

12. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters

13. Design and implementation of 3-bit synchronous up/down counter

14. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

3

LIST OF EQUIPMENTS AND COMPONENTS FOR A BATCH OF 30 STUDENTS(2 per Batch)

Equipments for Analog Lab

CRO (30MHz) – 15 Nos.

Signal Generator /Function Generators (3 MHz) – 15 Nos

Dual Regulated Power Supplies ( 0 – 30V) – 15 Nos.

Standalone desktop PCs with SPICE software – 15 Nos.

Transistor/FET (BJT-NPN-PNP and NMOS/PMOS) – 50 Nos

Components and Accessories

Equipments for Digital Lab

Dual power supply/ single mode power supply - 15 Nos

IC Trainer Kit - 15 Nos

Bread Boards -15 Nos

Computer with HDL software - 15 Nos

Seven segment display -15 Nos

Multimeter -15 Nos

ICs each 50 Nos

7400/ 7402 / 7404 / 7486 / 7408 / 7432 / 7483 / 74150 /

74151 / 74147 / 7445 / 7476/7491/ 555 / 7494 / 7447 / 74180 /

7485 / 7473 / 74138 / 7411 / 7474

4

STUDENTS GUIDELINES

There are 3 hours allocated to a laboratory session in Analog and Digital Lab. It is a necessary part of the course at which attendance is compulsory.

Here are some guidelines to help you perform the Programs and to submit the reports:

1. Read all instructions carefully and proceed according to that. 2. Ask the faculty if you are unsure of any concept. 3. Give the connection as per the diagrams. 4. After verification by the faculty, tabulate the readings. 5. Write up full and suitable conclusions for each experiment and draw the graph. 6. After completing the experiment complete the observation and get signature from the staff.

7. Before coming to next lab make sure that you complete the record and get sign from the faculty.

5

BREADBOARD

The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. That is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node requiring a large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is a node. You will build your circuits on the terminal strips by inserting the leads of circuit components into the contact receptacles and making connections with

Incorrect connection of power to the ICs could result in them exploding or becoming very hot with the possible serious injury occurring to the people working on the experiment! Ensure that the power supply polarity and all components and connections are correct before switching on power .

The breadboard. The lines indicate connected holes.

6

BUILDING THE CIRCUIT

The steps for wiring a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything! 2. Make sure the power is off before you build anything! 3. Connect the supply and ground (GND) leads of the power supply to the power and ground bus

strips on your breadboard. 4. Plug the devices you will be using into the breadboard. 5. Mark each connection on your schematic as you go, so as not to try to make the same

connection again at a later stage. 6. Get one of your group members to check the connections, before you turn the power on. 7. If an error is made and is not spotted before you turn the power on. Turn the power off

immediately before you begin to rewire the circuit. 8. At the end of the laboratory session, collect you hook-up wires, devices and all equipment and

return them to the demonstrator. 9. Tidy the area that you were working in and leave it in the same condition as it was before you

started.

Common Causes of Problems:1. Not connecting the ground and/or power pins. 2. Not turning on the power supply before checking the operation of the circuit. 3. Leaving out wires. 4. Plugging wires into the wrong holes. 5. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the start of the experiment and return them to their proper place after you have finished the experiment. Please inform the demonstrator or technician if you locate faulty equipment.

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EXPERIMENT NO -1 a

FREQUENCY RESPONSE OF CE AMPLIFIER

AIM:

1. To measure the voltage gain of a CE amplifier

2. To draw the frequency response curve of the CE amplifier

APPARATUS REQUIRED:

S. No. Components/ Devices Range/ Specifications Qty

1 Transistor BC107 1No.

2 Regulated power Supply 0-30V 1No.

3 Function Generator 3 MHz 1No.

4 CRO 30 MHz 1No.

5 Resistors 33KΩ, 3.3KΩ, 330Ω, 1.5KΩ,

1KΩ, 2.2KΩ, 4.7KΩ

1No.Each

6 Capacitors 10µF - 100µF 2No, 1No.

7 Bread Board 1 No.

8 Connecting wires As Req.

THEORY:

The CE amplifier provides high gain &wide frequency response. The emitter lead is

common to both input & output circuits and is grounded. The emitter-base circuit is forward

biased. The collector current is controlled by the base current rather than emitter current. When

a transistor is biased in active region it acts like an amplifier. The input signal is applied to base

terminal of the transistor and amplifier output is taken across collector terminal. A very small

change in base current produces a much larger change in collector current. When positive half-

cycle is fed to the input circuit, it opposes the forward bias of the circuit which causes the

collector current to decrease; it decreases the voltage more negative. Thus when input cycle

varies through a negative half-cycle, increases the forward bias of the circuit, which causes the

collector current to increases thus the output signal is common emitter amplifier is in out of

phase with the input signal. An amplified output signal is obtained when this fluctuating

collector current flows through a collector resistor,Rc.

The capacitor across the collector resistor Rc will act as a bypass capacitor. This

will improve high frequency response of amplifier

8

CIRCUIT DIAGRAM

EXPECTED WAVE FORMS: A) INPUT WAVE FORM:

B) OUTPUT WAVE FORM

9

INPUT-VS OUTPUT WAVEFORM:

FREQUENCY RESPONSE

CALCULATION OF BANDWIDTH FROM FREQUENCY RESPONSE:

Bandwidth=f2-f1 Hz

10

OBSERVATIONS: FREQUENCY RESPONSE: Vi=40mv

Frequency in HZ OUTPUTVOLTAGE(Vo)

GAIN INdB=20log10(Vo/Vi)

PROCEDURE: 1. Connect the circuit as shown in circuit diagram 2. Apply the input of 20mV peak-to-peak and 1 KHz frequency using Function

a. Generator 3. Measure the Output Voltage Vo (p-p) for various load resistors. 4. Tabulate the readings in the tabular form. 5. The voltage gain can be calculated by using the expression , Av= (V0/Vi) 6. For plotting the frequency response the input voltage is kept Constant at 20mV 7. peak-to-peak and the frequency is varied from 100Hz to 1MHz Using function 8. generator 9. Note down the value of output voltage for each frequency. 10. All the readings are tabulated and voltage gain in dB is calculated by Using The 11. expression Av=20 log10 (V0/Vi) 12. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis On Semi-log

graph. 13. The band width of the amplifier is calculated from the graph Using the expression,

Bandwidth, BW=f2-f1

Where f1 lower cut-off frequency of CE amplifier, and Where f2 upper cut-off frequency of CE amplifier

14. The bandwidth product of the amplifier is calculated using the Expression

Gain Bandwidth product=3-dBmidband gain X Bandwidth

RESULT: The 3-dB Bandwidth of the CE Amplifier is _____.

EXPERIMENT NO -1 b

11

FREQUENCY RESPONSE OF CC AMPLIFIER

AIM:

1. To measure the voltage gain of a CC amplifier.

2. To draw the frequency response of the CC amplifier.

APPARATUS REQUIRED:


1 Transistor BC107 1No.

2 Regulated power Supply 0-30V 1No.

3 Function Generator 3 MHz 1No.

4 CRO 30 MHz 1No.

5 Resistors 33KΩ, 3.3KΩ, 330Ω, -

1.5KΩ, 1KΩ, 2.2KΩ, 4.7KΩ

1No.Each

6 Breadboard 1No.

7 Capacitors 10µF - 100µF 2No, 1No.

8 Connecting wires As Req.

THEORY:

In common-collector amplifier the input is given at the base and the output is taken at

the emitter. In this amplifier, there is no phase inversion between input and output. The input

impedance of the CC amplifier is very high and output impedance is low. The voltage gain is less

than unity. Here the collector is at ac ground and the capacitors used must have a negligible

reactance at the frequency of operation. This amplifier is used for impedance matching and as a

buffer amplifier. This circuit is also known as emitter follower.

The most common use of the emitter follower is as a circuit, which performs the

function of impedance transformation over a wide range of frequencies.

12

CIRCUIT DIAGRAM:

INPUT VS OUTPUT WAVEFORM

Blue Colour: Input

Green Colour: Output

x-axis: frequency , y-axis: voltage

FREQUENCY RESPONSE PLOT:13

OBSERVATIONS:

A) Gain ,Vi=40mV

Load Resistance(KΩ) output

Voltage(Vo)

Gain, Av=V0/V Gain in dB

Av=20log 10(V0/Vi)

B) FREQUENCY RESPONSE,Vi=40mV

Frequency(Hz) Output Voltage(Vo) Gain in dB Av=20log

10(V0/Vi)

14

PROCEDURE:

1. Connect the circuit as shown in circuit diagram 2. Apply the input of 20mV peak-to-peak and 1 KHz frequency using Function 3. Generator 4. Measure the Output Voltage Vo (p-p) for various load resistors. 5. Tabulate the readings in the tabular form. 6. The voltage gain can be calculated by using the expression , Av= (V0/Vi) 7. For plotting the frequency response the input voltage is kept Constant at 20mV 8. peak-to-peak and the frequency is varied from 100Hz to 1MHz Using function 9. generator 10. Note down the value of output voltage for each frequency. 11. All the readings are tabulated and voltage gain in dB is calculated by Using The 12. expression Av=20 log10 (V0/Vi) 13. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis On Semi-log

graph. 14. The band width of the amplifier is calculated from the graph Using the expression,

Bandwidth, BW=f2-f1

Where f1 lower cut-off frequency of CE amplifier, and Where f2 upper cut-off frequency of CE amplifier

15. The bandwidth product of the amplifier is calculated using the Expression

Gain Bandwidth product=3-dBmidband gain X Bandwidth

RESULT:

The 3-dB Bandwidth of the CC Amplifier is _____.

EXPERIMENT NO -1 c

15

FREQUENCY RESPONSE OF CB AMPLIFIER

AIM:

1. To measure the voltage gain of a CC amplifier.

2. To draw the frequency response of the CC amplifier.

APPARATUS REQUIRED:


1 NPN-Transistor BC107 1

2 Regulated Power supply (0-15V) 2

3 Resistor 1KΩ 2

4 Ammeter (0-200mA) 1

5 Voltmeter (0-20V) 1

6 Breadboard As REQ.

7 Connecting wires As REQ.

THEORY:

A transistor is a three terminal active device. The terminals are emitter, base, collector.

In CB configuration, the base is common to both input (emitter) and output (collector). For

normal operation, the E-B junction is forward biased and C-B junction is reverse biased.

In CB configuration, IE is +ve, IC is –ve and IB is –ve. So, VEB = f1 (VCB, IE) and

IC = f2 (VCB, IE)

With an increasing the reverse collector voltage, the space-charge width at the output

junction increases and the effective base width „W‟ decreases. This phenomenon is known as

“Early effect”. Then, there will be less chance for recombination within the base region. With

increase of charge gradient with in the base region, the current of minority carriers injected

across the emitter junction increases. The current amplification factor of CB configuration is

given by,

= ∆Iα C / ∆IE

CIRCUIT DIAGRAM:

16

INPUT VS OUTPUT WAVEFORM

Blue Colour: Input

Green Colour: Output

x-axis: frequency , y-axis: voltage

17

OBSERVATIONS:

A) Gain ,Vi=40mV

Load Resistance(KΩ) output

Voltage(Vo)

Gain, Av=V0/V Gain in dB

Av=20log 10(V0/Vi)

B) FREQUENCY RESPONSE,Vi=40mV

Frequency(Hz) Output Voltage(Vo) Gain in dB Av=20log

10(V0/Vi)

RESULT:

The 3-dB Bandwidth of the CB Amplifier is _____.

18

EXPERIMENT NO -2

FREQUENCY RESPONSE OF COMMON SOURCE FET AMPLIFIER

AIM:

1. To obtain the frequency response of the common source FET Amplifier

2. To find the Bandwidth.

APPRATUS REQUIRED:


1 N-channel FET BFW11 1

2 Regulated Power supply (0-30V) 1

3 Resistors 6.8KΩ, 1MΩ, 1.5KΩ Each 1 no

4 Capacitors 0.1µF, 47µF 2 Nos, 1No.

5 Function generator 3 MHz 1

6 CRO 30 MHz 1

7 Breadboard As REQ.

8 Connecting wires As REQ.

THEORY:

A field-effect transistor (FET) is a type of transistor commonly used for weak-signal

amplification (for example, for amplifying wireless (signals). The device can amplify analog or digital

signals It can also switch DC or function as an oscillator. In the FET, current flows along a

semiconductor path called the channel. At one end of the channel, there is an electrode called the

source. At the other end of the channel, there is an electrode called the drain. The physical diameter of

the channel is fixed, but its effective electrical diameter can be varied by the application of a voltage to

a control electrode called the gate. Field-effect transistors exist in two major classifications. These are

known as the junction FET (JFET) It can also switch DC or function as an oscillator. In the FET, current

flows along a semiconductor path called the channel. At one end of the channel, there is an electrode

called the source. At the other end of the channel, there is an electrode called the drain. The physical

diameter of the channel is fixed, but its effective electrical diameter can be varied by the application of

a voltage to a control electrode called the gate. Field-effect transistors exist in two major

classifications. These are known as the junction FET (JFET) and the metal-oxide- semiconductor FET

(MOSFET).In a JFET, the junction is the boundary between the channel and the gate. Normally, this P-

N junction is reverse-biased (a DC voltage is applied to it) so that no current flows between the

channel and the gate. However, under some conditions there is a small current through the junction

19

during part of the input signal cycle. The FET has some advantages and some disadvantages relative to

the bipolar transistor. Field-effect transistors are preferred for weak-signal work, for example in

wireless, communications and broadcast receivers. They are also preferred in circuits and systems

requiring high impedance. The FET is not, in general, used for high-power amplification, such as is

required in large wireless communications and broadcast transmitters.

Field-effect transistors are fabricated onto silicon integrated circuit (IC) chips. A single

IC can contain many thousands of FETs, along with other components such as resistors, capacitors,

and diodes. A common source amplifier FET amplifier has high input impedance and a moderate

voltage gain. Also, the input and output voltages are 180 degrees out of Phase.

CIRCUIT DIAGRAM:

EXPECTED GRAPH: A) INPUT WAVEFORM

B) OUTPUT WAVEFORM

20

CALCULATION OF BANDWIDTH FROM FREQUENCY RESPONSE:

Bandwidth=f2-f1 Hz

FREQUENCY RESPONSE,Vi=20mA

Output Voltage(Vo) Voltage gain=V0/Vin Gain in

dB=20log10(V0/Vin)

21

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. A signal of 1 KHz frequency and 20mV peak-to-peak is applied at the Input of amplifier.

3. Output is taken at drain and gain is calculated by using the expression,

Av=V0/Vi

4. Voltage gain in dB is calculated by using the expression,

Av=20log 10(V0/Vi)

5. Repeat the above steps for various input voltages.

6. Plot Av in dB Versus Frequency

7. The Bandwidth of the amplifier is calculated from the graph using the Expression,

Bandwidth BW=f2-f1

8. Where f1 is lower 3 dB frequency f2 is upper 3 dB frequency

PRECAUTIONS:

1. All the connections should be tight.

2. Transistor terminals must be identified properly

RESULT:

The 3-dB Bandwidth of the CS Amplifier is _____.

EXPERIMENT NO -3

22

DARLINGTON AMPLIFIER USING BJT

AIM:

To construct a Darlington current amplifier circuit and to plot the frequency response characteristics.

APPARATUS REQUIRED:

S. No. Components/ Devices Range/ Specifications Qty1. Transistor BC 107 12. Resistor 15k ,10k ,680 ,6k 1,1,1,13. Capacitor 0.1µ F, 47µ F 2, 14. Function Generator (0-3)MHz 15. CRO 30MHz 16. Regulated power supply (0-30)V 17. Bread Board 1

THEORY:

In Darlington connection of transistors, emitter of the first transistor is directly connected to the base of the second transistor .Because of direct coupling dc output current of the first stage is (1+hfe )Ib1.If Darlington connection for n transitor is considered, then due to direct coupling the dc output current foe last stage is (1+hfe ) n times Ib1 .Due to very large amplification factor even two stage Darlington connection has large output current and output stage may have to be a power stage. As the power amplifiers are not used in the amplifier circuits it is not possible to use more than two transistors in the Darlington connection.

In Darlington transistor connection, the leakage current of the first transistor is amplified by the second transistor and overall leakage current may be high, Which is not desired.

23

CIRCUIT DIAGRAM

MODEL GRAPH

f 1 f2 f (Hz)

24

OBSERVATION:

Keep the input voltage constant, Vin =

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)

PROCEDURE:

1. Connect the circuit as per the circuit diagram.

2. Set Vi =50 mv, using the signal generator.

3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps and note down the corresponding output voltage.

4. Plot the graph; Gain (dB) vs Frequency(Hz).

5. Calculate the bandwidth from the graph.

RESULT:

Thus, the Darlington current amplifier was constructed and the frequency response curve is plotted. . The Gain Bandwidth Product is found to be =

REVIEW QUESTIONS:

1. What is meant by Darlington pair?

2. How many transistors are used to construct a Darlington amplifier circuit?

3. What is the advantage of Darlington amplifier circuit?

4. Write some applications of Darlington amplifier.

25

EXPERIMENT NO -4DIFFERENTIAL AMPLIFIER USING BJT

AIM:

To construct a differential amplifier using BJT and to determine the dc collector current of

individual transistors and also to calculate the CMRR.

APPARATUS REQUIRED:

S. No. Components/ Devices Range/ Specifications Qty1. Transistor BC107 22. Resistor 4.7kΩ, 10kΩ 2,13. Regulated power supply (0-30)V 14. Function Generator (0-3) MHz 25. CRO 30 MHz 16. Bread Board 1

FORMULA:

Common mode Gain (Ac) = VO / VIN

Differential mode Gain (Ad) = V0 / VIN

Where VIN = V1 – V2

Common Mode Rejection Ratio (CMRR) = Ad/Ac

Where, Ad is the differential mode gain

Ac is the common mode gain.

THEORY:

The differential amplifier is a basic stage of an integrated operational amplifier. It is used to amplify the difference between 2 signals. It has excellent stability, high versatility and immunity to noise. In a practical differential amplifier, the output depends not only upon the difference of the 2 signals but also depends upon the common mode signal.

Transistor Q1 and Q2 have matched characteristics. The values of RC1 and RC2 are equal. Re1

and Re2 are also equal and this differential amplifier is called emitter coupled differential amplifier. The output is taken between the two output terminals.

26

CIRCUIT DIAGRAM

OBSERVATION VIN =VO =AC = VO / VIN

27

OBSERVATION VIN = V1 – V2

V0 =

Ad = V0/ VIN

For the differential mode operation the input is taken from two different sources and the common mode operation the applied signals are taken from the same source

Common Mode Rejection Ratio (CMRR) is an important parameter of the differential amplifier. CMRR is defined as the ratio of the differential mode gain, Ad to the common mode gain, Ac.

CMRR = Ad / Ac

In ideal cases, the value of CMRR is very high.

PROCEDURE:

1. Connections are given as per the circuit diagram.2. To determine the common mode gain, we set input signal with voltage Vin=2V

and determine Vo at the collector terminals. Calculate common mode gain, Ac=Vo/Vin.

3. To determine the differential mode gain, we set input signals with voltages V1 and V2. Compute Vin=V1-V2 and find Vo at the collector terminals. Calculate differential mode gain, Ad=Vo/Vin.

4. Calculate the CMRR=Ad/Ac.5. Measure the dc collector current for the individual transistors.

RESULT:

Thus, the Differential amplifier was constructed and dc collector current for the individual transistors is determined. The CMRR is calculated as

28

EXPERIMENT NO -5a

CASCADE AMPLIFIER CIRCUIT

AIM:

To construct a cascade amplifier circuit and to plot the frequency response characteristics.

APPARATUS REQUIRED:

S. No. Components/ Devices Range/ Specifications Qty1. Transistor BC107 1

2. Resistor 10kΩ,8 kΩ,500 Ω,100Ω 1,1,1,1

3. Regulated power supply (0-30)V 1

4. Signal Generator (0-3)MHz 1

5. CRO 30 MHz 1

6. Bread Board 1

7. Capacitor 0.01µF 5

8. Connecting wires As Req.

THEORY:

A cascade amplifier has many of the same benefits as a cascode. A cascade is basically a differential amplifier with one input grounded and the side with the real input has no load. It can also be seen as a common collector (emitter follower) followed by a common base.

By cascading a CE stage followed by an emitter-follower (CC) stage, a good voltage amplifier results. The CE input resistance is high and CC output resistance is low. The CC contributes no increase in voltage gain but provides a near voltage-source (low resistance) output so that the gain is nearly independent of load resistance. The high input resistance of the CE stage makes the input voltage nearly independent of input-source resistance. Multiple CE stages can be cascaded and CC stages inserted between them to reduce attenuation due to inter-stage loading.

29

MODEL GRAPH

f 1 f2 f (Hz)

PROCEDURE:


2. The waveforms at the input and output are observed for cascade operations by varying the input frequency.

3. The biasing resistances needed to locate the Q-point are determined.

4. Set the input voltage as 1V and by varying the frequency, note the output voltage.

5. Calculate gain=20 log (Vo / Vin.)

6. A graph is plotted between frequency and gain.

30

FREQUENCY RESPONSE OF CASCADE AMPLIFIER

Keep the input voltage constant (Vin) =

Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

RESULT:

Thus, the Cascade amplifier was constructed and the gain was determined.

REVIEW QUESTIONS

1. What is meant by Cascading?

2. What is the overall gain of the two stage cascaded amplifier?

3. What methods are used for cascading?

4. What is the disadvantage of direct coupled cascade amplifier?

5. Write some application of cascaded amplifier.

31

EXPERIMENT NO -5bCASCODE AMPLIFIER CIRCUIT

AIM:

To construct a cascode amplifier circuit and to plot the frequency response characteristics.

APPARATUS REQUIRED:

S. No. Components/ Devices Range/ Specifications Qty1. Transistor BC107 2

2. Resistor22kΩ,6 kΩ,700 Ω,470Ω, 16 kΩ, 6.2 kΩ,3.3 kΩ,1.1 kΩ

Each one

3. Regulated power supply (0-30)V 1

4. Signal Generator (0-3)MHz 1

5. CRO 30 MHz 1

6. Bread Board 1

7. Capacitor 0.01µF 3

THEORY:

A cascode amplifier consists of a common emitter amplifier stage in series with a common base amplifier stage. It it one approach to solve the low impedance problem of a common base circuit. Transistor Q1 and its associated components operate as a common emitter amplifier, while the circuit of Q2 functions as a common base output stage. The cascade amplifier gives the high input impedance of a common emitter amplifier, as well as the good voltage gain and frequency performance of a common base circuit.

32

MODEL GRAPH

f 1 f2 f (Hz)

PROCEDURE:


2. The waveforms at the input and output are observed for cascode operations by varying the input frequency.

3. The biasing resistances needed to locate the Q-point are determined.

4. Set the input voltage as 1V and by varying the frequency, note the output voltage.

5. Calculate gain=20 log (Vo / Vin.)

6. A graph is plotted between frequency and gain.

FREQUENCY RESPONSE OF CASCODE AMPLIFIER33

Keep the input voltage constant (Vin) =

Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

RESULT:

Thus, the Cascade amplifier was constructed and the gain was determined.

REVIEW QUESTIONS:

1. What is meant by Cascoding?

2. What is the overall gain of the two stage cascaded amplifier?

3. What methods are used for cascading?

4. What is the disadvantage of direct coupled cascade amplifier?

5.Compare cascade amplifier with cascade amplifier.

EXPERIMENT NO -6

34

SPICE SIMULATION OF COMMON EMITTER AND COMMON SOURCE AMPLIFIERS

AIM:

To construct and simulate the Common Emitter and Common Source amplifiers using OrCAD Pspice software.

SOFTWARE USED:

OrCAD release version 9.1.

CIRCUIT DIAGRAM:

Common Emitter:

Common Source:

PROCEDURE:

35

Common Emitter:

Common Source:

Result:

Thus the design of Common Emitter and Common Source amplifiers were simulated and verified using OrCAD Pspice.

EXPERIMENT NO -7

DESIGN AND IMPLEMENTATION OF CODE CONVERTER

AIM:

36

To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:

Sl.No COMPONENT SPECIFICATION QTY.

1 X-OR GATE IC 7486 1

2 AND GATE IC 7408 1

3 OR GATE IC 7432 1

4 NOT GATE IC 7404 1

5 IC TRAINER KIT - 1

6 PATCH CORDS - As req.

THEORY:

The availability of large variety of codes for the same discrete elements of information results in the

use of different codes by different systems. A conversion circuit must be inserted between the two

systems if each uses different codes for same information. Thus, code converter is a circuit that makes

the two systems compatible even though each uses different binary code. The bit combination

assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There

are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated

as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table,

combinational circuit is designed. The Boolean functions are obtained from K-Map for each output

variable. A code converter is a circuit that makes the two systems compatible even though each uses a

different binary code. To convert from binary code to Excess-3 code, the input lines must supply the

bit combination of elements as specified by code and the output lines generate the corresponding bit

combination of code. Each one of the four maps represents one of the four outputs of the circuit as a

function o f the four input variables. A two-level logic diagram may be obtained directly from the

Boolean expressions derived by the maps. These are various other possibilities for a logic diagram

that implements this circuit. Now the OR gate whose output is C+D has been used to implement

partially each of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

37

LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTER TRUTH TABLE:

38

LOGIC DIAGRAM:

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BCD TO EXCESS-3 CONVERTOR TRUTH TABLE:

LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTOR TRUTH TABLE:

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LOGIC DIAGRAM:

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PROCEDURE: 1. Connections were given as per Logic diagram. 2. Logical inputs were given as per truth table .3. Observe the logical output and verify with the truth tables

RESULT: Thus the Binary to gray code converter, Gray to binary code converter, BCD to excess-3 code

converter and Excess-3 to BCD code converter was designed and implemented.

EXPERIMENT NO -8

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DESIGN OF 4-BIT ADDER AND SUBTRACTOR

AIM: To design and implement 4-bit adder, subtractor and BCD adder using IC 7483.

APPARATUS REQUIRED:

Sl.No COMPONENTS SPECIFICATION QTY1 IC IC 7483 12 EX-OR GATE IC 7486 13 NOT GATE IC 7404 14 IC TRAINER KIT - 15 WIRES - AS REQ.

THEORY:4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between each data input ‘B’ and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns.

ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum

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PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:

4-BIT BINARY ADDER

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LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR

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TRUTH TABLE:

LOGIC DIAGRAM: BCD ADDER

TRUTH TABLE:

46

PROCEDURE: 1. Connections were given as per Logic diagram. 2. Logical inputs were given as per truth table. 3. Observe the logical output and verify with the truth tables

RESULT:

Thus the 4-bit adder, subtractor and BCD adder using IC 7483 was designed and implemented.

EXPERIMENT NO -9

47

DESIGN AND IMPLEMENTATION OF MULTIPLEXER ANDDEMULTIPLEXER USING LOGIC GATES

AIM: To design and implement multiplexer and demultiplexer using logic gates.

APPARATUS REQUIRED:

S. No COMPONENTS SPECIFICATION QTY1 3 I/P AND GATE IC 7411 12 OR GATE IC 7432 13 NOT GATE IC 7404 14 IC TRAINER KIT - 15 WIRES - AS REQ.

THEORY:

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

48

FUNCTION TABLE:

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

49

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:

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TRUTH TABLE:

PROCEDURE:

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1. Connections are given as per Logic diagram. 2. Logical inputs are given as per truth table. 3. Observe the output and verify the truth table.

RESULT:

Thus the multiplexer and demultiplexer using logic gates was designed.

EXPERIMENT NO -10

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER USING LOGIC GATES

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AIM: To design and implement encoder and decoder using logic gates.

APPARATUS REQUIRED:

Sl.No COMPONENTS SPECIFICATION QTY1 3 I/P NAND GATE IC 7410 12 OR GATE IC 7432 13 NOT GATE IC 7404 14 IC TRAINER KIT - 15 PATCH CORDS - As req.

THEORY: ENCODER:

An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n

input lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.

DECODER:A decoder is a multiple input multiple output logic circuit which converts coded input into

coded output where input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n output values are from 0 through out 2n – 1

TRUTH TABLE FOR ENCODER:

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LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE FOR DECODER:

54

LOGIC DIAGRAM FOR DECODER:

PROCEDURE:

1. Connections are given as per Logic diagram.

2. Logical inputs are given as per the truth table.

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3. Observe the output and verify the truth table.

RESULT:

Thus the encoder and decoder using logic gates were designed.

EXPERIMENT NO -11

CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD-10 / MOD-12 RIPPLE COUNTERS

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AIM: To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1JK FLIP FLOP

IC 74762

2NAND GATE

IC 74001

3IC TRAINER KIT

1

4 WIRES AS REQUIRED

THEORY:A counter is a register capable of counting number of clock pulse arriving at its clock input.

Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference between a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation.

PIN DIAGRAM FOR IC 7476:

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LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:

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LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

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LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

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PROCEDURE:

1. Connections are given as per logic diagram.

2. Logical inputs are given as per truth table.


RESULT: Thus the 4 bit ripple counter mod 10/ mod 12 ripple counters was implemented and the truth

table was verified.61

EXPERIMENT NO -12

DESIGN AND IMPLEMENTATION OF 3-BIT SYNCHRONOUS UP/DOWN COUNTER

AIM: To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 1

JK FLIP FLOP

IC 74762

23 I/P AND GATE IC 7411

1

3OR GATE IC 7432

1

4XOR GATE IC 7486

1

5NOT GATE IC 7404

1

6IC TRAINER KIT

1

7 WIRES AS REQ.

THEORY:A counter is a register capable of counting number of clock pulse arriving at its clock input.

Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or decreasing order through a certain sequence. An up/down counter is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down signal. When this signal is high counter goes through up sequence and when up/down signal is low counter follows reverse sequence

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K MAP

STATE DIAGRAM:

CHARACTERISTICS TABLE:

63

LOGIC DIAGRAM:

TRUTH TABLE:

64

PROCEDURE:




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RESULT: Thus the 3 bit synchronous up/down counter was designed implemented.

EXPERIMENT NO -13

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM: To design and implement

i. Serial in serial out shift register (SISO)

ii. Serial in parallel out shift register (SIPO)

iii. Parallel in serial out shift register (PISO)

iv. Parallel in parallel out shift register (PIPO)

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.1

D FLIP FLOP IC 7474 2

2OR GATE IC 7432

1

3IC TRAINER KIT

- 1

66

4WIRES

-AS REQ.

THEORY: A register is capable of shifting its binary information in one or both directions is known as

shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right

PIN DIAGRAM:

LOGIC DIAGRAM: SERIAL IN SERIAL OUT:

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TRUTH TABLE:

LOGIC DIAGRAM: SERIAL IN PARALLEL OUT:

TRUTH TABLE:

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LOGIC DIAGRAM: PARALLEL IN SERIAL OUT:

TRUTH TABLE:

LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT:

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TRUTH TABLE:

PROCEDURE:




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RESULT: Thus the Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in parallel

out shift registers were implemented using IC 7474.

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Manual Ec1 New

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