Lv Power Mosfet

Renesas Electronics America Inc.

Confidential

May 2011 Rev.1.0

Intermediate

Low Voltage Power MOSFETs

Christopher Lee, PMD & GP Products [email protected]

408-649-4703

Confidential

Course Introduction

Purpose This course provides intermediate knowledge of low voltage Power MOSFETs.

Objective Learn what a power MOSFET is and how it works. Understand how to read a MOSFET datasheet. Understand basic MOSFET characteristics.

Content 35 pages (except exam. Session) 5 questions

Learning Time 40 minutes

MOSFETs

© 2010 Renesas Electronics America Inc. All rights reserved.3

MOSFET’s Packaging Trends Characteristics and Datasheet

Confidential

What is a Power MOSFET?

MOSFET: metal–oxide–semiconductor field-effect transistor MOSFET is a transistor used for amplifying or switching electronic signals In MOSFETs a voltage on the oxide-insulated GATE [G in the diagram below] induces a

conducting channel between the two other contacts called SOURCE [S] & DRAIN [D]. Gate voltage is denoted Vg A Power MOSFET can switch and conduct very high power levels, an is useful in power

conversion circuits (i.e. boost voltage, decrease voltage , convert DC to AC, etc.)


D

G

S

ID

VG

D

G

S

Confidential

What is a Power MOSFET?

The threshold voltage is the minimum VG at which a conducting channel forms.

For switching applications such as for switching voltage regulators, the VG is modulated between on (> saturation voltage of the channel) and OFF …

For switching applications, this channel between the Drain and Source can be thought of a resistor (RDSON) that is controlled by the VG in power applications.


D

G

S

ID

VG

D

G

S

Packaging Trends in LV MOSFETs

6


Confidential

SMD Packages

Confidential

Footprint Compatibility Footprint Compatibility

8

Solutions from Renesas : (LFPAK/LFPAK-i, WPAK) + WINFET/BEAM MOSFETs

Renesas(Hitachi, NXP)

Bottom Side Cooling Double-Sided Cooling

LFPAK-i

S S S G

Top

D D D DLFPAK-i

S S S G

Top

D D D D

Renesas – LFPAK-i

IR – DirectFET

Bottom

Bottom

Bottom

Bottom Bottom

Bottom

D

WPAK

Bottom

Confidential

Space Saving Packages

QFN56 QFN40

SOP-8WPAK

LFPAK LFPAK-i

WPAK-Dual

HVSON

mini-HVSON

HWSON3044

HWSON3030

Vin

Vout

Vcc

LDriver /Controller

Hi

Lo

[ 5x6 ][ 5x6 ]

[ 5x6 ] [ 5x6 ]

[ 3.3x3.3 ]

[ 5x6 ][ 3x4.4 ]

[ 6x6 ][ 8x8 ]

Integrated Power IC

Compounded Hi/Lo MOSFETs

Down sizing

-56% (5x6 ->3x4.4)

-44% (8x8 ->6x6)

-64% (5x6 ->3.3x3.3)

-50% (5x6x2 ->5x6x1)

-29% (5x6x3 ->8x8)

Downsizing

Downsizing

9 © 2010 Renesas Electronics America Inc. All rights reserved.

Confidential10

Package Roadmap for High Current Application

Confidential

Package Resistance

~1.0m

~0.5~0.5mm

Au wireAu wire

Die

Lead Frame(Source, Gate)

Au Wire

Die pad (Drain)

AL ribbon

lead(Source, Gate) Die

Die pad (Drain)Au bump

LFPAKLFPAK-i

Lower PKG resistance Reduces Conduction loss!Reduces Conduction loss!

Die pad (Drain)

DieAL ribbonAL ribbon

WirelessWireless

Cu clip

Die pad (Drain)

DieCu clipCu clip

SOP-8WPAKWPAK-DualHWSON3044HWSON3030

HVSONmini-HVSON3x3mm

SOP-8

Cu wireCu wire

Die

Lead Frame(Source, Gate)

Cu Wire

Die pad (Drain)


Confidential

Observed Trend Toward IntegrationObserved Trend Toward Integration

12

- Another Solution from Renesas -- Another Solution from Renesas -

12Vin

Controller

CPU

DISBL

VCIN REG5V VIN

PGNDVLDRV

PWMVSWH

OverlapProtect.

GH

CGND

BOOT

SBD

GL

3-stateInput

REG5VUVL

A “System in Package”, SiP

Driver

QFN40

[ 6x6 ]Top viewTop view Bottom ViewBottom View

[ 8x8 ]

QFN56

Downsizing


Characteristics & Datasheet


Confidential© 2010 Renesas Electronics America Inc. All rights reserved.14

MOSFET Characteristics

Break down voltages (VDSS, VGSS)

On Resistance (RDSON)

Switching chacteristics Gate Charge (QG, QGD)

Capacitances (CISS, COSS, etc)

Avalanche Body Diode ASO Area of Safe Operation

Confidential

Power MOSFET Absolute Maximum Ratings


Confidential

Gate to Source Leak Current

Gate Source Cutoff Voltage

Forward Transfer Admittance

Drain Source on Resistance 1

Drain Source on Resistance 2

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

VDSS

IDSS

IGSS

VGS(off)

IYfsI (gm)

RDS(on)1

RDS(on)2

CISS

COSS

CRSS

Min Typ Max

60 - -

- - 10

- - 0.1

1.0 - 2.5

55 90 -

- 4.3 5.5

- 6.0 9.0

- 9770 -

- 1340 -

- 470 -

ID=10mA, VGS=0

VDS=60V, VGS=0

VGS=20V, VDS=0

VDS=10V, ID=1mA

ID=45A, VDS=10V

ID=45A, VGS=10V

ID=45A, VGS=4V

VDS=10V

VGS=0

FSW=1MHz

Parameter Symbol Value Test

ConditionTemperatureDependence

Attention for Design

(Ta=25degC) : Have positive temperature coefficient.

: Have negative temperature coefficient.

There is a VDS dependency here. Indicate drive loss at operatingtime of analogThere is VDS dependency. Influence on fall time tf at light load time.There is VDS dependency.Influence on SW time tr and tf

Influence on noise at operatingtime of SW and SW time tr and tf

It is related to on-resistance

High dependence ontemperature, but low loss

Protection diode built in products are from scores of nA to scores of A. The guarantee is 10uA.

This is the most important parameter to decide on-loss.Pay attention to rise in curvewith temperature

Unit

V

uA

uA

V

S

m

m

pF

pF

pF

Drain-source destruction voltageZero Gate VoltageDrain Current

Note: VDS(off) = VTH

S = siemens = 1/

CISS = CGS + CGD

COSS = CDS + CGD

CRSS = CGD

MOSFET Electrical CharacteristicsMOSFET Electrical Characteristics


Confidential

Important MOSFET Device Design ParametersImportant MOSFET Device Design Parameters

RDS(si) = Rch + Repi + Rsub

Structure of N-Channel Trench Cell

N++

N -

N+

P+

D

SG

EpiSubstrate

RGI


RDS(si)

Drain

Gate

Source

RWIRE

RG

RWIRE

Parasitic NPNBipolar Transistor

RGI

Rsub

Repi

Rch

MOSFET Resistances

Body Diode

VGSS

VDSS

Confidential

D

GS

P (CH)

N (Epi)-

N (Sub)++

+

Rsub

Repi

S

Rch

RWIRE

N (S) N (S)+

P (CH)

N (Epi)

N (Sub)++

-

D

G

Planar Trench

VDSS 30V 200V60V

Rch

Repi

Rsub

30%

40%

30%

10%

80%

10%

5%

94%

1%

The Resistive Components of the overall RDS(on) Structure of a Vertical Power MOSFET

RDS(ON) = Rch + Repi + Rsub + RWIRE

Resistance ratio for Trench MOSFET

Vertical MOSFET Cells Vertical MOSFET Cells Overall ROverall RDS(on)DS(on) ComponentsComponents


Drain of the Si is glued to the tab with silver epoxy, so the contribution of that resistance is negligible

Return

Confidential

RDS(ON) - TC characteristic (2SK3418)

Temperature dependency of On-Resistance, RTemperature dependency of On-Resistance, RDS(ON)DS(ON)


Confidential



N++

N -

N+

P+

D

SG

EpiSubstrate

Rgi


Drain

Gate

Source

LG

Ls

RG

LD

RTAB

MOSFET Package Parasitic

RWIRE

Packaging

Confidential


CISS = CGS + CGD

COSS = CDS + CGD

CRSS = CGD


N++

N -

N+

P+

D

SG

EpiSubstrate

Rgi


CGS

CDS

Drain

Gate

Source

CGD

MOSFET Capacitances

VGSS

VDSS

Confidential



N++

N -

N+

P+

D

SG

EpiSubstrate

Rgi


Drain

Gate

Source

BodyDiode

trr

ID

IDR

Parasitic NPNBipolar TransistorVGSS

VDSS

MOSFET Body Diode

Confidential

The Characteristics of a MOSFET Body Diode The Characteristics of a MOSFET Body Diode

IDR - VSD characteristic (2SK3418)(N-channel)

= 0 V

1. A parasitic body diode is built in the Power MOSFET between the source and drain. The maximum current rating of this diode, IDR, is the same value as the maximum rating of the MOSFET forward drain current, ID

2. This diode shows that it has the same characteristic for forward voltage as an ordinary diode in the case of zero bias for the gate drive voltage, VGS=0

3. If the gate drive voltage, VGS, has a positive bias, as in the case of N-channel MOSFET. Then, VSD will be a voltage that is determined by the on-resistance RDS(on) (VSD = ID x RDS(on)), as shown on the figure to the right. Therefore, it is possible to get very low forward voltage similar to a Schottky barrier diode (SBD).

4. By taking advantage of such a characteristic, the body diode can be used to benefit the application in the following:

a) Load switches for protection against reverse connection of battery

b) Hot swap circuits of redundant method for switching power supply (n+1)

c) Replace external diodes in motor driving circuit bridges

d) Secondary synchronous rectifier circuits in switching power supplies


Confidential

Schottky Barrier Diode

Non-overlap/Dead Time to avoid cross conduction (“shoot-through”) Body diode of a synchronous switch conducts during dead time Body diode is lossy and is slow to turn on/off A Schottky diode (SBD) is used in parallel with the MOSFET

Reduced the forward voltage drop from ~0.7V to ~0.2V Reduces losses from body diode turn on and reverse recovery losses Limits overshoot on turn on

Non-overlap time conduction can be significant at high switching frequencies


Gate

Source

Drain

SBD

Body Diode

Confidential

SBD Reduces Turn-on Spike Noise

VP=22.6V

-17%

Vds(L)

Vg(H)

Vgs(L)

SuppressingSuppressingSpike voltageSpike voltage

VP=27.2V

Lo:RJK0351DPA (without SBD)

Vds(L)

Vgs(L)Vg(H)

Lo:RJK0381DPA (Built in SBDBuilt in SBD)

Confidential

Drain-Source Saturation Voltage, VDrain-Source Saturation Voltage, VDS(ON)DS(ON)

VDS(on) - VGS characteristic(2SK3418)

VVDS(ON)DS(ON) depends on the Gate Drive Voltage, V depends on the Gate Drive Voltage, VGSGS, and the Drain current, I, and the Drain current, IDD

VVDS(ON) DS(ON) = I= IDD x R x RDS(ON)DS(ON)


Confidential

1. Total gate charge, QG, is the point where the gate driving voltage, VGS, becomes equal to the Driver output voltage (DVGS) at the gate of the MOSFET

2. QG is the parameter that controls gate peak current, IG(peak), from the MOSFET driver and the drive loss, P(drive loss) IG(peak) = QG/t (1)

P(drive loss) = FSW*QG*VGS (2)3. QGD corresponds to mirror capacitance, CRSS

and its value depends on the power supply voltage VDS. Recall that CRSS = CGD

4. QGD is the parameter that greatly influences a devices switching fall time, tf,

where RS = RDRIVER, RG = RPCB++Rgi:

5. The fall time, tf, controls the switching loss and tf is computed using formula (3) above. Both QG and QGD are important items when designing for high frequency operation. For high-speed switching (over FSW=100kHz) applications, the smaller the RON/QG or RON/QGD the more efficiency the MOSFET device will become

QQGG, Q, QGDGD, ig(peak), P(Drive Loss) & Fall Time (t, ig(peak), P(Drive Loss) & Fall Time (tff) ) definitionsdefinitions

.

tf = VGS(on) - VTH

ln VGS(on)(RS + rg)*QGD

VTH

(3)..

Input Dynamic Characteristic (2SK3418)

VG

S (

V)

Gate Charge(a)

QG @ (VGS=DVGS)

QTH

QGD

VD

S (

V)

VDS

VGS

VTH

VGS(on)

QGS

QG

DVGS

Q = CISSVGS = integral (IG * dt) = I*t = I*1/FSW

I = Q*FSW

P= IV =Q*FSW*V = C*FSW*V2


Confidential

Avalanche Breakdown

It is a phenomenon that can occur in both insulating and semiconductor materials.

It is a form of electric current multiplication that can allow very large currents to flow within materials which are otherwise good insulators.

It is a type of electron avalanche.

The Avalanche process occurs when the carriers in the transition region are accelerated by the electric field to energies sufficient to free electron-hole pairs via collisions with bond electrons.


Confidential

Avalanche - Destruction Failure ModesAvalanche - Destruction Failure ModesWhen the current through the output inductor is quickly turned off, the magnetic field of the inductor induces a counter electromagnetic force, EMF, that can build up a high VDS voltage across the MOSFET. The full buildup of this induced voltage may exceed the rated breakdown voltage, VDSS, of the MOSFET and result in the catastrophic failure of the MOSFET.

Two failure modes exist when MOSFETs are subjected to unclamped inductive switching, UIS. These two failure mechanisms are defined as either 1) the active Mode 1 or 2) the passive Mode 2.

1.The first, or active Mode 1, results when the avalanche current actively forces the parasitic bipolar transistor into conduction and turns it on. Today, MOSFETs are being manufactured in which the parasitic bipolar transistor never turns on and Mode 1 failures do not occur

2.The second, or passive Mode 2, results when the instantaneous chip temperature reaches a critical value. At this elevated temperature, a “meso-plasma” forms within the parasitic NPN bipolar transistor and causes catastrophic thermal runaway. The passive mechanism is, therefore, identified as that failure mode not directly attributed to avalanche currents.

In either of the first or the second cases, the MOSFET is destroyed.

Parasitic Bipolar Transistor


VIN

VOUT

IOUT

L

CD IL

Confidential

1

23

4

5

Safe Operation Area, SOA, DefinitionsSafe Operation Area, SOA, Definitions

SOA for the (2SK3418)


PROPERTIES

On passing, 'Finish' button: Goes to Next SlideOn failing, 'Finish' button: Goes to Next SlideAllow user to leave quiz: After user has completed quizUser may view slides after quiz: At any timeUser may attempt quiz: Unlimited times

Lv Power Mosfet

Documents

Transcript of Lv Power Mosfet