LTE MIMO System Level Design
description
Transcript of LTE MIMO System Level Design
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LTE MIMO System-Level Design(Preliminary)
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Agenda
MIMO OverviewMIMO Transmitter Case StudyMIMO Receiver Case StudyEarly R&D LTE Hardware Testing
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Basic channel access modesTransmitAntennas
ReceiveAntennas
SISO
The Radio Channel
MISO
Single Input Single Output
Multiple Input Single Output(Transmit diversity)
ReceiveAntennas
TransmitAntennas
MIMO
The Radio Channel
SIMO
Single Input Multiple Output(Receive diversity)
Multiple Input Multiple Output(Multiple stream)
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Advantages of multiple antennas
MISO (Tx diversity) increases the robustness of the signal to poor channel conditions. It does not increase data rates but increases coverage and therefore cell capacity.
SIMO (Rx diversity) improves the received SNR by combining multiple copies of the same signal. Like MISO it does not increase data rates but extends coverage and hence cell capacity.
MIMO uses multiple data streams to increase cell capacity. The data streams can be allocated to one user to increase single-user data rates.
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Multiple antenna techniques
Multiple antenna techniques are fundamental to LTE and an appreciation of the different methods and their relative advantages and disadvantages is important
There are three main multi-antenna techniques used in LTE1. Transmit/receive diversity2. Spatial multiplexing
Single User MIMO (SU-MIMO) Multi-user MIMO (MU-MIMO)
3. Beamforming
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Transmit/receive diversity
This is the same as what already exists for UMTS Transmit diversity has been specified for W-CDMA since R99. Receive
diversity was introduced in Rel-6 for HSDPA.
The same data is sent on two antennas which provides better SNRImproves performance in low SNR conditions and with fadingSimple combining is used in the receiver
eNB UE
Stream 1
Stream 1
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Single user MIMO
This is an example of downlink 2x2 single user MIMO with precoding. Two data streams are mixed (precoded) to best match the channel
conditions.The receiver reconstructs the original streams resulting in increased single-
user data rates and corresponding increase in cell capacity. 2x2 SU-MIMO is mandatory for the downlink and optional for the uplink
SU-MIMO
eNB 1 UE 1
= data stream 1
= data stream 2
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Multiple user MIMO
UE 2
UE 1
eNB 1
MU-MIMO
Example of uplink 2x2 MU-MIMO.In multiple user MIMO the data streams come from different UE.There is no possibility to do precoding since the UE are not connected but
the wider TX antenna spacing gives better de-correlation in the channel.Cell capacity increases but not the single user data rate.The key advantage of MU-MIMO over SU-MIMO is that the cell capacity
increase can be had without the increased cost and battery drain of two UE transmitters.
MU-MIMO is more complicated to schedule than SU-MIMO
= data stream 1
= data stream 2
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SystemVue MIMO Source
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SystemVue MIMO Channel Model
Simulated Spectrum with MIMO Fading
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SystemVue MIMO Receiver
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Agenda
MIMO OverviewMIMO Transmitter Case StudyMIMO Receiver Case StudyEarly R&D LTE Hardware Testing
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Mixed-Signal Challenges: System Design Tradeoffs
Tx RxCodingAlgorithms
D/ABits In Decoding
Algorithms Bits Out
ChannelA/D
GainLinearityOutput Power
GainNFPhase Noise
Considerations: Key Algorithms Baseband Implementation/ Fixed-Point Effects RF Design Impairments/Non-Linearities Phase Noise, ADC Jitter Channel Impairments
FPGA HDL Code
Fixed Point Baseband Designs
Math Algorithms
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System-Level Architecture DesignPartition Design Requirements to Meet LTE Specifications without Over-Designing
ADC and DACImpairments
RF Transmitter/PA Nonlinarities
Baseband Fixed-PointMixed-Signal
Receiver
Tx RxCodingAlgorithms
D/A
Bits In DecodingAlgorithms Bits Out
RF ChannelA/D
Coding/Decoding
Algorithms
With LTE having such high performance targets every part of the transmit and receive chain becomes critical to the link budgetSo how to decide the optimum balance, without over-designing?How are design requirements impacted going from QPSK to 16QAM to 64QAM?
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Baseband Libraries Algorithm Test Vectors for FPGA Development
(Preliminary)
Coding/Decoding
Algorithms
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Configurable References
(Preliminary)
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Diff
FPGA HDL CoSim Output
SystemVueScrambler
Output
HDL (Actual Scrambler Code Not Shown)
Switch between C++ model and math algorithm model
FPGA Scrambler Example
(Preliminary)
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Diff
FPGA HDL CoSim Output
SystemVueScrambler
Output
HDL (Actual Scrambler Code Not Shown)
Switch between C++ model and math algorithm model
FPGA Scrambler Example
(Preliminary)
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Transmitter Design Start with SystemVue Pre-Configured Template
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I in
Q in
4XUpSample
4XUpSample
FIR RRC
FIR RRC
Fs/4 Carrier Multiplexing
I(t)*CosWc(t)
Q(t)*SinWc(t)
I(t)*CosWc(t)-Q(t)*SinWc(t)
Design Fixed Point IQ Modulator andReplace Ideal IQ Modulator
Baseband Fixed-Point
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64QAM EVM Results with FIR Wordlength =10 for Fixed Point IQ Modulator Design
EVM = 0.5 %
(Preliminary)
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64QAM EVM Results with FIR Wordlength =8 forFixed Point IQ Modulator Design
EVM = 1.3 %
(Preliminary)
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64QAM EVM Results with FIR Wordlength =6 & 7 for Fixed Point IQ Modulator Design
EVM = 2.9 % EVM = 46 % !
FIR Wordlength = 7 bits FIR Wordlength = 6 bits
(Preliminary)
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Enable HDL Code Gen to Target an FPGA
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Add RF Design: Transmitter and Antenna Cross Talk
Specify LO Phase Noise dBc/Hz @ Freq. Offset RF Transmitter/
PA Nonlinarities
Specify 1dBComp. Pt.
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-80 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk
Specify Phase Noise in
dBc/Hz vs. Frequency
Offset
RS EVM = 1.3 % RS EVM = 1.3 %
QPSK 64 QAM(Preliminary)
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-70 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk
Specify Phase Noise in
dBc/Hz vs. Frequency
Offset
RS EVM = 3.5 % RS EVM = 3.5 %
QPSK 64 QAM(Preliminary)
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-60 dBc/Hz Phase Noise @ 10kHz with -30 dB CrossTalk
RS EVM = 11.2 %
QPSK
Specify Phase Noise in
dBc/Hz vs. Frequency
Offset
RS EVM = 11.2 % ,but composite EVM is 85%
64 QAM
Phase noise is introducing significant ICI , which is impacting OFDMA subcarrier orthogonality
(Preliminary)
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LTE MIMO Downlink BER with ADI A/D Converter
MIMO SourceMIMO Receiver
Sweep SNR
ADI A/D Converter
MIMO Channel
ADC and DACImpairments
Mixed-SignalReceiver
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QPSK BER Results with Swept ADI A/D Converter Jitter
2% Jitter
4% Jitter
6% Jitter
(Preliminary)
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QPSK , 16QAM, 64QAM Results vs. Swept ADI ADC Jitter
QPSK 16 QAM 64 QAM
2% Jitter4% Jitter
6% Jitter
2% Jitter
4% Jitter
6% Jitter
2% Jitter4% Jitter
6% Jitter
(Preliminary)
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QPSK , 16QAM, 64QAM Results vs. Swept LO Phase Noise
QPSK 16 QAM 64 QAM
-70 dBc/Hz
-65 dBc/Hz
-60 dBc/Hz
(Preliminary)
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Agenda
MIMO OverviewMIMO Transmitter Case StudyMIMO Receiver Case StudyEarly R&D LTE Hardware Testing
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Demodulator
RF IF
BasebandDe-Coding
RF/RF BER
A/DConverter
I
Q
Simulated COTS Receiver
MXG, ESGMXA, PSA
SystemVue+ VSA SW
Simulated
COTS Waveform
Step 1Download
Signal
Step 2Capture Signal
SISO Early R&D SDR Hardware Testing
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Demodulator
RF IF
BasebandDe-Coding
RF/IF BER
A/DConverter
I
Q
MXG, ESGMXA, PSA
Simulated COTS Receiver
SystemVue+ VSA SW
Simulated
COTS Waveform
Step 1Download
Signal
Step 2Capture Signal
SISO Early R&D SDR Hardware Testing
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Demodulator
RF IF
BasebandDe-Coding
A/DConverter
I
Q
Simulated COTS Receiver
MXG, ESG MXA with BB IQ
I Q
RF/ Analog IQ BER
SystemVue+ VSA SW
Simulated
COTS Waveform
Step 1Download
Signal
Step 2Capture Signal
SISO Early R&D SDR Hardware Testing
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Demodulator
RF IF
BasebandDe-Coding
RF/Digital IQ BER
A/DConverter
I
Q Simulated COTS Baseband Receiver
MXG, ESG
RF/Digital IF BER
Logic Analyzers
SystemVue+ VSA SW
Simulated
COTS Waveform
Step 1Download
Signal
Step 2Capture Signal
SISO Early R&D SDR Hardware Testing
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Picture of LTE OFDMA Mixed-Signal DUTSISO BER Test Setup
16822ALogic Analyzerwith AgilentSystemVue*
N6705ADC PowerAnalyzer
MXG(Download Signal from SystemVue)ESG(DUT Clock)
14 Bit A/D Board DUT
* Note: SystemVue does not ship with Logic Analyzer
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LTE OFDMA SISO BER Test Setup Diagram
Trigger In
16822 Logic Analyzer withSystemVue
installed
14-Bit A/DConverter
Board (DUT)
LAN Cable
Event 1 Marker Out
Analog In
Clk In
30.72 MHzDig.Out
ESG
SVue LTE TDD/FDD Signal at 7.68 MHz IF
Download SystemVue LTE TDD/FDDSignal via LAN
SystemVueMXG
+ 3.3V + 5V
N6705A DC Power Analyzer
LAN Cable
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LTE OFDMA SISO BER Results (TDD)
(Preliminary)
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Automate Testing with SystemVue Math Scripting
Sweep DC Biaswith PowerSupply/Analyzer
SweepRF Poweron MXG
MXG
Power Supply/Analyzer
Sweep from: QPSK to 16 QAM to 64QAM
Logic Analyzer with SystemVue
Installed
14-BitA/D Converter
DUT
BER
(Preliminary)
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FDD SISO BER with Swept QPSK, 16QAM, 64QAM, +5V Bias
(Preliminary)
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http://www.agilent.com/find/eesof-lte-whitepaper
From an Agilent FPGA Developer using SystemVue:
SystemVue helped me discover a typing error in my 16QAM scrambler which was failing tests. It has saved MBD at least 3 months of development time already, and is crucial for meeting - and exceeding - our on-going development time goals.
http://cp.literature.agilent.com/litweb/pdf/5990-3671EN.pdf
New LTE Reference Vector White Paper
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New LTE Bookwww.agilent.com/find/ltebook
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For More Information:www.agilent.com/find/systemvue
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For More Information:www.agilent.com/find/lte
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Summary
Trade-off baseband and RF design impairments for system-level design requirements Evaluate fixed-point design impairments on system-level metrics such as EVM and BER; Generate HDL from fixed-point design to target FPGAs Generate LTE reference vectors to validate hand-written HDL code for FPGA implementations Perform system-level design trade-offs to minimize over-designing to meet specs (e.g. fixed point vs. LO phase noise vs. RF nonlinearities vs. ADC jitter) Combine simulation with test equipment to perform coded BER on RF/mixed-signal hardware, using simulation to provide baseband coding/decoding functionality
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Thank You!