Low Power VLSI Circuit Design with Efficient HDL Coding.doc

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Novel High Speed Vedic Mathemat ics Multiplier using Compressors AIM: The ma in aim of the pro je ct is to des ig n “No vel Hi gh Spe ed Ved ic Mathematic s Multiplier using Compressors”. ABS!AC: With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an inte gra l pa rt of pr ocessor de si gn. ue to this rega rd, hi gh spee d mult ipli er architectures !ecome the need of the day. In this paper, we introduce a novel arc hit ect ure to per form high speed multip lic ation using ancient Ved ic mat hs techni"ues. # new high speed approach utili$ing %&' compressors and novel (&' compressors for addition has also !een incorporated in the same and has !een e)plored. *pon comparison, the compressor !ased multiplier introduced in this  paper, is almost two times faster than the popular methods of multiplication. With regards to area, a + reduction is seen. The design and e)periments were carried out on a -ilin) Spartan e series of /01# and the timing and area of the design, on the same have !een calculated. V.Mallikarjun a (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIED COMPANY  Branch!: "#$ra%a$ & Na'()r

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Novel High Speed Vedic Mathematics Multiplier using Compressors

AIM:

The main aim of the project is to design “Novel High Speed Vedic

Mathematics Multiplier using Compressors”.

ABS!AC:

With the advent of new technology in the fields of VLSI and

communication, there is also an ever growing demand for high speed processing

and low area design. It is also a well known fact that the multiplier unit forms an

integral part of processor design. ue to this regard, high speed multiplier

architectures !ecome the need of the day. In this paper, we introduce a novel

architecture to perform high speed multiplication using ancient Vedic maths

techni"ues. # new high speed approach utili$ing %&' compressors and novel (&'

compressors for addition has also !een incorporated in the same and has !eene)plored. *pon comparison, the compressor !ased multiplier introduced in this

 paper, is almost two times faster than the popular methods of multiplication. With

regards to area, a + reduction is seen. The design and e)periments were carried

out on a -ilin) Spartan e series of /01# and the timing and area of the design,

on the same have !een calculated.

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY   Branch!: "#$ra%a$ &Na'()r

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• The speed of a processor greatly depends on its multiplier7s performance.

This in turn increases the demand for high speed multipliers, at the sametime keeping in mind low area and moderate power consumption.

• The compressor !ased Vedic maths multiplier proves to !e a !etter option

over conventional multipliers used in several e)peditious and comple) VLSI

circuits.

!()(!(NC(S:

• L. 8iminiera and #. Valen$ano, 9Low cost serial multipliers for highspeed

specialised processors,9 8omputers and igital Techni"ues, I44 0roc. 4,

vol. +:.:, pp. ':3;'6:.

• #..<ooth, =# Signed <inary 5ultiplication Techni"ue,> ?. mech. #nd

appl. math, vol %, no.', pp. '6;'%@, A)ford *niversity 0ress.

• 8. B. <augh, <. #. Wooley, =# Two7s 8omplement 0arallel #rray

5ultiplication #lgorithm,>, I444 Trans. 8omputers ''C+'D, pp. +@%:E+@%(.

• Foren Israel, >8omputer #rithmetic #lgorithms,> 'nd 4d, pp. +%+;+%3,

*niversities 0ress.

• L. Sriraman, T.G. 0ra!akar, =esign and Implementation of Two Varia!le

5ultiplier *sing F85 and Vedic 5athematics,> +st Int. 8onf. on Becent

#dvances in Information Technology, han!ad, India, I444 0roc., pp. (H';

(H(.

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

ISO: 9001- 2008 CERTIFIED COMPANY   Branch!: "#$ra%a$ &Na'()r