Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

1

1.11.2008

Low Power System-on-Chip Design

Chapters 3-4

Tomasz Patyk

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Chapter 3: Multi-Voltage Design

� Challenges in Multi-Voltage Designs

� Voltage Scaling Interfaces

� Timing Issues in Multi-Voltage Designs

� Power Planning for Multi-Voltage Design

� System Design Issues with Multi-Voltage Designs

2

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Introduction

� Techniques discussed so far (Clock Gating, Gate Level Power Optimization, Multi-VDD, Multi-VT)

- Well known

- Supported by the CAD tools for years

- Not efficient enough nowadays

� More aggressive approaches required

- Adaptive Voltage Scaling

- Power Gating

� General rule: Depart from the idea of the single rail supplying all gates in the design

3

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Different Multi-Voltage strategies

� Static Voltage Scaling (SVC): different suply voltage for different blocks of the system

� Multi-level Voltage Scaling (MVS): extension of SVC, each block or subsystem can be supplied with 2 or more different voltages (discrete, fixed number, dependent on the mode)

� Dynamic Voltage and Frequency Scaling (DVFS): extension of MVS, large number of voltage levels dynamically switched based on theworkload

� Adaptive Voltage Scaling (AVS): extension of DVFS, voltage is adjusted with the help of the control loop

4

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Challenges in Multi-Voltage Designs

� Level shifters

� Characterization and Static Timing Analysis

� Floor planning, power planning, grids

� Board level issues

� Power up and power down sequencing

5

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Voltage Scaling Interfaces – The need for Level Shifters

� 1V domain to 5V domain

� 0.9V domain to 1.2V domain (crowbar currents)

� Correct boundary voltage is required to leave the timing within the domain unaffected

6

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Unidirectional Level Shifters

� Difficulty with building bidirectional shifters

� Unidirectional LSs are not a problem for static voltage scaling

� In other forms of multi-voltage, the designs needs to be partitioned and the neighboring domains need to have a defined relation (always higher, lower, the same)

� Basic types- High to Low Level Shifter

- Low to High Level Shifter

7

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

High to Low Level Shifter

� Simple to build

� Single power rail (from lower voltage domain)

� Intruces only buffer delay, hence impact on timing is small

8

1.11.2008

Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-ChipDesign”

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Low to High Level Shifter

� Driving signals from low to high voltage domain is a bigger chalange

� Under-driven signal degrades the rise and fall times at the receiving inputs (higher switchin current, reduced noise margins)

� One simple designe shown in the figure

� Introduce significant delay

9

1.11.2008

Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-ChipDesign”

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Level Shifter Recommendations and Pitfalls

� Recommendations- Place the level shifter in the receiving domain

- Consider delay introduced by Low to High level shifters in timing of the critical blocks

- Ensure that there is a defined relationship between different voltage domains

� Pitfalls- Bidirectional interfaces between domains will require specialized level

shifter components

- Make the verification process much more complicated

10

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Timing Issues in Multi-Voltage Designs

� Clock routing across different power domains requires level shifters� Problem with the synthesis process automation� STA – time constraints need to be defined for each power domain independently� Lets consider an example of the MLVS design...

Question: Under which conditions should we minimize the clock skew relative to the 1.2V domain?Answer: Optimization and timing analysis must be done for both cases to ensure that the timing requirements

will be met in both cases.

11

1.11.2008

Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-ChipDesign”

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

System Design Issues with Multi-Voltage Design

� Power sequencing

- Bringing up all power supplies at the same time not practical inmost cases

- Power up sequence may be required for the correct functioning

� Ramp times need to be controlled to avoid voltage overshoot or undershoot

- System mulfunction or lock up if the voltage raises above or falls below the target voltage

� If power controller is controlled by a CPU, the power control software needs to be integrated into software run by the CPU

12

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Chapter 4: Power Gating Overview

� Dynamic and Leakage power profiles

� Impact of Power Gating on Classes of Sub-systems

� Principles of Power Gating Design

13

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

The Basic Strategy of Power Gating

� The basic idea: provide low and active power modes

� The main goal: effectively switch between these modes to maximize power savings while minimizing the impact on the performance

� More invasive than e.g. Clock-Gating

- Affects inter-block interface communication

- Adds time delays when entering and leaving the power modes

� Changing the mode can be done:

- Explicitly e.g. control software

- Implicitly e.g. timers, system level power management cotroller

14

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Dynamic and Leakage Power Profiles - Example

15

1.11.2008

Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-ChipDesign”

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Dynamic and Leakage Power Profiles – Realistic Profile

16

1.11.2008

Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-ChipDesign”

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Impact of Power Gating on Classes of Subsystems

� Trade-offs in a power gated cached CPU subsystem being inactive for longer periods of time:

- Good leakage power reduction

- Time required to restore the caches states

- Bilans of the energy saved while the CPU was shut down, minus energy required to refill the caches

� The system with multiple CPUs

- Shut down cores performing idle tasks

- No need for the caches states saving

- Optimized energy savings by the implementation of algorithms varying the number of cores accordingly to the workload

17

1.11.2008

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Principles of Power Gating Design

� Two approaches for switching the power- Fine Grain Power Gating – the switch placed locally inside each standard cell- Coarse Grain Power Gating – blocks of designe are switched by a collection of

switches� Fine Grain method can be used in traditional design flow, at the cost of the significant area

overhead (2x- 4x)� The Coarse Grain scheme is prefered (less area penalty)

18

1.11.2008

Source: Keating, Flynn & al.: ”Low Power Methodology Manual for System-on-ChipDesign”

Department of Computer Systems / TKT-9626 Low Power System-on-Chip Design Chapters 3-4

Challenges of Power Gating

� The power switching circuitry

� The power gating controller

� Retention registers

� Minimalization of the impact on the design timing and area

� The functional control of clocks and resets

� Developement of the constraints for implementation and analysis

� State-dependent verification of all supported power states

� State transition verification

� Developing manufacturing and production test strategies

19

1.11.2008