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Low-Complexity Full-Melt Laser-Anneal Process for Fabricationof Low-Leakage Implanted Ultrashallow Junctions

CLEBER BIASOTTO,1,4 VIKTOR GONDA,1,2 LIS K. NANVER,1

TOM L.M. SCHOLTES,1 JOHAN VAN DER CINGEL,1 DANIEL VIDAL,1

VLADIMIR JOVANOVIC1,3,5

1.—Delft Institute of Microsystems and Nanotechnology DIMES, Delft University of Technology,Feldmannweg 17, 2628 CT Delft, The Netherlands. 2.—Present address: Institute of Mechanicaland Materials Engineering, College of Dunaujvaros, Tancsics M. u. 1/a, Dunaujvaros 24000,Hungary. 3.—Faculty of Electrical Engineering and Computing, University of Zagreb, Unska 3,10000 Zagreb, Croatia. 4.—e-mail: [email protected]. 5.—e-mail: [email protected]

Good-quality ultrashallow n+p junctions are formed using 5-keV amorphizingAs+ implantations followed by a single-shot excimer laser anneal for dopantactivation. By using an implant that is self-aligned to the contact windowsetched in an oxide isolation layer, straightforward processing of the diodes isachieved with postimplantation processing temperatures kept below 400�C. Apossible source of junction leakage at the perimeter caused by dip-etchenlargement of the contact window, also confirmed by transmission electronmicroscopy (TEM) analysis, is identified, and diode performance is improvedby increasing the junction/contact window overlap. The optimum performancein terms of low leakage, shallow junctions, and low resistivity is achieved for30� tilted implants and by applying a thin laser-reflective aluminum layer.This work isolates the minimum requirements for achieving low-leakage diodecharacteristics.

Key words: Excimer laser annealing, ultrashallow junctions, tiltedimplantations, low-temperature processing, reflective maskinglayer

INTRODUCTION

Laser annealing for implanted dopant activationhas been receiving considerable attention since itwas put on the International Technology Roadmapfor Semiconductors (ITRS) in 1999 as one of the onlymeans of achieving the targets for source/drainrequirements related to the scaling down of com-plementary metal–oxide–semiconductor (CMOS)devices in silicon.1 Many experiments based ondoping profiling and sheet resistance measurementshave shown that both full-melt and laser thermalprocessing can result in attractive values for junc-tion depth, abruptness, and sheet resistance.2–8 Ofthe rapid anneal procedures investigated for futureCMOS devices, excimer laser annealing (ELA) has

the shortest annealing times, practically eliminat-ing any transient-enhanced diffusion (TED) effects,and also offers benefits such as precise control ofjunction depth, good abruptness of the dopant pro-file, and high dopant activation. The depth of junc-tions processed by full-melt ELA can be preciselycontrolled by applying amorphizing ion implanta-tion, since amorphous silicon has a lower meltingtemperature than crystalline silicon, and the energydensity of the laser light can be adjusted to onlymelt the top amorphous region, thus aligning thejunction depth to the amorphous/crystalline inter-face region.9–13 Therefore, for this type of annealinga reduction of the vertical implantation range canserve as a direct means of also decreasing thejunction depth.

The laser processing research presented in thispaper, rather than being aimed at the fabrication ofsource and drain regions for CMOS, has been

(Received January 28, 2011; accepted August 9, 2011;published online September 9, 2011)

Journal of ELECTRONIC MATERIALS, Vol. 40, No. 11, 2011

DOI: 10.1007/s11664-011-1734-6� 2011 The Author(s). This article is published with open access at Springerlink.com

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motivated by the need to have access to good-qualitydiodes in integration situations where only very lowtemperatures are permitted. This is, for example,the case when adding sensor/actuator elements tofully processed CMOS wafers and in the post-sub-strate-transfer processing of silicon-on-glassdevices.14 In the former case the metallization willlimit the further processing to the 400�C to 500�Crange, and in the latter case the adhesive used forsubstrate transfer will force the limit even furtherdown to 300�C. With the full-melt high-power ELAthat is the topic of this paper, essentially room-temperature annealing can be achieved because thelaser energy only heats an ultrashallow surfaceregion and the silicon substrate serves as a heatsink, resulting in a large temperature gradient andvirtually no heating outside the irradiated surfaceregion. Moreover, for the targeted applications, lowcomplexity is an important requirement, since theyoften involve large-area structures (e.g., photodi-odes, protection diodes, passive elements) that can-not profit from aggressive downscaling to becomecost-effective. This paper presents the moststraightforward and therefore most widely applica-ble processing scheme that has issued from ourresearch towards such low-cost add-on diodes. Inthis process the dopants are implanted in a contactwindow etched through a layer stack of Al (thereflective mask for the laser annealing) on a SiO2

surface isolation layer. Full-melt laser annealing isthen performed, and the resulting diode is metal-lized without any further thermal processing. Inthis way the diode is self-aligned to the originalcontact window. This paper discusses in detail theintricacies of each stage of this fabrication process,and on the basis of these observations, generalconclusions are made on the conditions that areimportant for achieving good-quality diodes alsoin situations where downscaling will demand morecomplex overall processing; for example, a variant ofthe process was adopted in the fabrication of low-temperature metal-gate n-channel devices asdescribed in Refs. 15 and 16.

EXPERIMENTAL PROCEDURES

The starting material is 2 Xcm to 5 Xcm (100)p-type silicon wafers, which are processed with n+

buried layers and both deep and shallow implants sothat the fabricated diode is embedded in a surfacelayer doping of 1017 cm�3 and can be contacted fromthe front of the wafer with low series resistance.Silicon dioxide is used as surface passivation andisolation layer for the diodes. Of the various possibleways to grow or deposit an oxide layer on the siliconsurface, thermal oxidation gives the highest-qualitylayer in terms of defect-state density at the interfaceto silicon and the density of the oxide itself. Hence,the etch rate of thermal oxide during a typical dip-etch step to remove native oxide is low. In our caseonly 10 nm is removed during a 4-min dip in 0.55%

hydrofluoric acid (HF) solution, which is attractivefor control of the lateral dimensions. Oxide layersdeposited by low-pressure chemical vapor deposi-tion (LPCVD) and plasma-enhanced chemical vapordeposition (PECVD) have inferior interface proper-ties and etch significantly faster in HF. On the otherhand, they can be deposited at much lower tem-peratures than normally usable for thermal oxida-tion. The experiments presented here in detail makeuse of a 330-nm-thick oxide stack consisting of a30-nm-thick thermal oxide grown at 850�C, whichgives a good interface to the silicon, covered with a300-nm-thick LPCVD oxide deposited at 700�C fromtetraethyl orthosilicate (TEOS) source, whichreduces the total thermal budget. A layer of 100-nm-thick aluminum with 1% silicon [Al/Si(1%)] is thendeposited by physical vapor deposition (PVD) toserve as a reflective masking layer for the laserlight, as shown in Fig. 1. Aluminum has been shownto be efficient in protecting regions that should notbe modified during laser annealing.6,8 The lowimplantation energy required for fabricating shallowjunctions also makes the implantation profile verydependent on the state of the silicon surface prior toion implantation. It has been demonstrated that aclean and smooth surface is essential for havinggood electrical characteristics of the implantedjunctions annealed by ELA, which requires softlanding during reactive-ion etching (RIE) steps andnative oxide removal before implanting ions.17

Various HF solutions can be used for the strippingof native oxide, the applicability of which will dependon the degree to which other layers are etched.

Openings in the isolating/reflective stack arepatterned in resist and etched by first reactive-ionetching of Al/Si(1%) using hydrogen bromide andchlorine plasma and then oxide RIE using a fluo-rine-based plasma. To prevent damage to the siliconsurface from the RIE process, the removal of the lastpart of the oxide isolation is done at lower radio-frequency (RF) power of 100 W, compared with300 W during bulk oxide etching. As specified inTable I, soft landing on the silicon surface results insmaller surface roughness, as good as that achievedby wet landing using HF solutions, but with theadvantage of not significantly etching in the lateraldirection.17,18 Native oxide is removed in bufferedHF (BHF) diluted with water in 1:7 ratio during a15-s dip that is performed immediately prior to theimplantation of As+ ions. Aluminum is readilyetched by HF solutions, but a dip in BHF(1:7) ispreferable here because the Al etching saturatesafter approximately 50 nm, leaving a sufficientlythick Al/Si(1%) layer to function as a reflectivemask. However, any etching of the Al/Si(1%) layercreates a rough surface that degrades the reflectiv-ity. To prevent this, the Al around the contactwindows is protected by resist during dip-etchingand implantation. The resist used to pattern thewindows themselves cannot be used for this purposebecause resist at the window perimeter will then be

Biasotto, Gonda, Nanver, Scholtes, van der Cingel, Vidal, and Jovanovic2188

co-implanted in the openings to the silicon and thisdegrades the ideality of the final laser-annealedjunction. Therefore, an additional lithography step isapplied where the contact-window mask is oversizedby 0.3 lm to 0.5 lm. The As+ ions are implantedwith an energy of 5 keV and to a dose of either1015 cm�2, 2 9 1015 cm�2 or 3 9 1015 cm�2. Toreduce the vertical implantation range, ions areimplanted at angles of either 7�, 30� or 45�. More-over, the higher tilt angles will result in somedopants being implanted further underneath theisolation oxide, thereby increasing the overlapbetween the isolation oxide and the junction. Duringthe implantation, some Al atoms can be knocked

from the top layer and predominantly sputtered inthe direction of the As+ ions. However, during a dipin BHF(1:7) the Al is recessed approximately 50 nmmore than the LPCVD oxide since it is exposed tothe solution also from the bottom side. The recess ofAl is sufficient to prevent it from being sputteredonto the contact window for all the implantationangles used in our experiments, as has been indi-cated in Fig. 2.

Laser annealing was performed using an ExitechM800V double laser system with a Lambda PhysikLPX 210 XeCl excimer laser with a wavelength of308 nm and a pulse duration of 25 ns full-width athalf-maximum (FWHM) using single-shot illumi-nation. A flat-top intensity profile was producedover a 1.75 mm 9 2.5 mm spot by using a homoge-nizer, and energy densities of laser illuminationwere varied from 700 mJ/cm2 to 1000 mJ/cm2.Sputtering of Al/Si(1%) is used for contacting of thediodes, preceded by a dip-etch in HF (0.55%) for4 min to remove native oxide, passivate the surfacewith hydrogen, and ensure reliably low contactresistance. When necessary, an additional substratecontact is also created on the backside of the wafer.The processing ends with alloying in forming gas for

p-Sith. SiO2

LPCVD SiO2

Al/Si(1%)

p-Sith. SiO2

LPCVD SiO2

Al/Si(1%)

ION IMPLANTATION

photoresist

Implanted region

p-Sith. SiO2

LPCVD SiO2

Al/Si(1%)

Annealed region

LASER ANNEALING

p-Sith. SiO2

LPCVD SiO2

Al/Si(1%)

(a)

(b)

(d)

(c)

Thermal oxidation – 30 nm

LPCVD oxide – 300 nm

Al/Si(1%) – 100 nm (a)

Lithography – contact opening

Contact hole etching by RIE

Lithography – enlarged contact

BHF(1:7), 15 s

As+ implantation (b)

ELA (c)

HF(0.55%), 4 min

Al/Si(1%) – 675 nm

Metallization patterning by RIE

Alloying @ 400 C, 30 min (d)

Fig. 1. Schematic process flow for fabrication of As+-implanted and laser-annealed ultrashallow n+p diodes.

Table I. Pre-implantation root-mean-square (RMS)surface roughness as a function of the type ofreflective mask and etch process used for landingon silicon18

Type of Landing Al (A) Al/Si(1%) (A)

Hard, 300 W 17 27Soft, 100 W 12 12Wet, BHF(1:7) 11 35

Low-Complexity Full-Melt Laser-Anneal Processfor Fabrication of Low-Leakage Implanted Ultrashallow Junctions

2189

20 min at 400�C, which is the highest-temperaturestep after the deposition of the LPCVD oxide layer.

STRUCTURAL JUNCTION PROPERTIES

Junction Morphology

The processing steps which predominantlydetermine the surface properties of the ultrashallowjunctions and the position and shape of the contactopening perimeter are: (i) RIE of the isolation oxidestack, (ii) native oxide removal in BHF(1:7) prior toion implantation, (iii) ion implantation, (iv) excimerlaser annealing of the structure, and (v) native oxideremoval in HF (0.55%) before metallization. Anoverview of the transformations of the contactperimeter at each of these stages is depicted inFig. 2. The selectivity of the oxide RIE in the fluo-rine-based plasma system to silicon is approxi-mately 10:1, but a certain overetch time is includedto remove all oxide inside the opening before junc-tion implantation, albeit at lower RF power. Nativeoxide removal by surface treatment by BHF(1:7) for15 s immediately prior to the As+ implantation alsoetches the isolation oxide in the lateral direction.The LPCVD oxide is removed faster than the ther-mal oxide, giving a recess of about 60 nm in additionto the 8 nm to 9 nm removed near the interface.

The slow etch rate of the thermal oxide is beneficialif maintaining minimum contact window size isimportant since tight control over the junctiondimensions is then preserved after this step, butotherwise the type of oxide used at the interface isnot critical at this stage of the process. The sub-sequent high-dose ion implantation amorphizes thesurface region of the silicon substrate and alsosputters some of the silicon atoms from the surface,an effect that increases with tilt angle: with a tiltangle of either 7�, 30� or 45�, respectively, 1, 1.58 or6 Si atoms are removed per As+ ion.18 In general,illumination by laser light melts the exposed surfacelayer to a depth that depends on the laser energy,but also on the depth of the region amorphized byion implantation because the amorphous silicon hasa lower melting temperature than the crystallinesilicon.9 The optimum annealing is achieved if thelaser energy is tuned to melt the complete amor-phous region which recrystallizes epitaxially fromthe underlying crystalline substrate. The absorptionlength of light with 308 nm wavelength is less than10 nm in silicon, in both the solid and liquid phase,and the major part of the laser energy is absorbed atthe Si surface. Additionally, the heat-sinking capa-bility of the silicon substrate keeps the regionbeyond a few microns from the irradiated area

RIE with “soft landing”

Contact hole etching by RIE (a)

Lithography – enlarged contact

BHF(1:7), 15 s

As+ implantation (b)

ELA

HF(0.55%), 4 min (c)

(a)

(b)

(c)

IONIMPLANTATION

p-Si

30 nm th. SiO2

300 nm LPCVD SiO2

100 nm Al/Si(1%)

p-Si

th. SiO2

LPCVD SiO2

Al/Si(1%)

Implanted region

7 30 45

73045

p-Si

th. SiO2

LPCVD SiO2

Junction edge possibly exposedFig. 2. Transformation of the structure of the contact window perimeter as it undergoes (a) oxide RIE, (b) pre-implantation native oxide removalin BHF(1:7), and (c) premetallization stripping of the native oxide in HF (0.55%). The schematic is drawn to scale and assumes an ideally verticaletching profile as obtained by RIE.


effectively at room temperature, whereas the lowermelting temperature of the amorphous siliconensures that only this region melts during laseraction.10–13 The melt onset begins at 600 mJ/cm2,and full melt to a depth of 20 nm happens for1100 mJ/cm2.18 However, for energy densities above1000 mJ/cm2, surface degradation patterns can de-velop that are referred to as laser-induced periodicsurface structuring (LIPSS). Such surface degra-dation can have a large impact on the quality of anultrashallow junction, and the maximum laserenergy density was therefore limited to 1000 mJ/cm2.19 The high temperature achieved in the meltedregion decays toward the bulk of the wafer and inthe lateral direction, but it can also exceed ablationlimits of the aluminum layer used as the reflectivemask, in which case some of the Al/Si(1%) isremoved from the edges of the openings while theoxide isolation remains unchanged. This is shown inFig. 3 for contact windows which were openedthrough the stack of oxide and reflective Al/Si(1%)layers, implanted, and laser annealed. A small partof the laser light is absorbed in the Al/Si(1%) and isnot conducted away efficiently due to the low ther-mal conductance of the thick underlying oxide. Thiscauses ablation of Al/Si(1%) at the edges thatincreases with laser energy density.17 The premetal-lization HF dip-etch further etches the oxide layers,and this step can potentially expose the junctionedges as indicated in Fig. 2c. For this reason itbecomes attractive to use implantations at highertilt angles to increase the lateral junction extensionunder the sides. In Fig. 4, a TEM image of the finalcontact opening confirms the shape of the edge ofthe isolation layer, with only a small lateral removalof the thermal oxide layer as opposed to the LPCVDoxide. A slight loss of silicon at the surface in theimplanted region can also be observed. This maystem from the overetch during oxide RIE, Si sput-tering during implantation, and/or native oxideremoval.

Doping Profiles

Secondary-ion mass spectrometry (SIMS) analy-ses of the samples implanted with arsenic ions to a

dose of 1015 cm�2 at different tilt angles and laserannealed at 1000 mJ/cm2 are shown in Fig. 5. Themain parameters extracted from these profiles arelisted in Table II. The increase in tilt angle results

Fig. 3. Series of microphotographs of five implanted and laser-annealed contact windows as a function of laser energy from 0 mJ/cm2 to1000 mJ/cm2. The light-grey area is the reflective Al masking layer, the middle grey is the Si of the contact window, and the dark grey is SiO2

around the contact window that is exposed due to ablation of the Al layer during the illumination by laser light.

Fig. 4. TEM image of the edge of a contact window that has beenexposed to steps (a–c) illustrated in Fig. 2.

30 tilt, Qimp = 7.98 1014 cm-2

45 tilt, Qimp = 7.43 1014 cm-2

7 tilt, Qimp = 1.05 1015 cm-2

Ars

enic

conc

entr

atio

n(c

m-3

)

Fig. 5. SIMS profiles of 5-keV As+ implants to dose of 1015 cm�2 attilt angles of 7�, 30�, and 45�, laser annealed at 1000 mJ/cm2. Thedose Qimp extracted by integration of the respective profile isindicated.


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in shallower doping profiles, from 20 nm at 7� tiltdown to only 15 nm at 45�, with a small amount ofchanneling being observed for the tilt of 30�. How-ever, with higher tilting of the ion beam, a lowereffective dose is implanted since the area exposed tothe ion beam is proportional to the cosine of the tiltangle. This is further exacerbated with more ionsreflected from the silicon surface at the higher tilt,resulting in the measured implanted doses of1.05 9 1015 cm�2, 7.98 9 1014 cm�2, and 7.43 91014 cm�2 at tilt angles of 7�, 30�, and 45� respec-tively, for the same ion dose generated by theimplanter. To compensate for this effect, a higherion dose setting could be used as the tilt angle isincreased. The practical limit for the reduction ofjunction depth using the increase in implantationtilt depends on the size of the contact opening, sincemore shadowing of the implanted ions by the ther-mal oxide/LPCVD oxide/aluminum stack will occurat larger angles. This effect has more impact as thelateral dimensions are scaled down. Furthermore,the increased surface roughness from LIPSS athigher annealing energies can start to play a moresignificant role and increase the leakage when thejunction depth reaches a critically low value.

ELECTRICAL CHARACTERIZATION

Current–Voltage Characteristics

The quality of the ultrashallow n+p junctions wasevaluated by examining the reverse leakage currentand the ideality of the forward current–voltagecharacteristics. The I–V characteristics of the As+-implanted diodes laser-annealed with an energydensity of 1000 mJ/cm2 are shown in Fig. 6. Thesemeasurements were taken at 100�C to reduce therelative influence of the leakage current fromShockley–Read–Hall recombination on the diodecurrent in the forward region. From the I–V charac-teristics in the reverse region, the diodes implanted at7� with a dose of 2 9 1015 cm�2 suffer from highleakage, which can be attributed to the oxide recessat the edge of the contact hole, as presented inFigs. 2 and 4. A reduction of leakage is achieved byeither increasing the implanted dose from2 9 1015 cm�2 to 3 9 1015 cm�2 or by increasing thetilt angle from 7� to 30�. Plausibly the increase to30� shifts the junction perimeter further under-neath the isolation oxide, preventing exposure of thejunction edge during the premetallization dip inBHF(1:7). For implantation at 7�, increasing the

dose can have the same effect, and moreover, thehigher dopant concentration can also be moreeffective in limiting the spread of the depletion intothe n-region. The energy transferred to the sub-strate by laser illumination melts the amorphizedregion, which then recrystallizes where the meltzone has extended to the amorphous–crystallineinterface. At the perimeter of the diodes the heattransfer to the substrate may be larger than in themiddle because the surrounding silicon mass thatcan absorb the heat is effectively larger.12 Thiswould mean a less effective melting of the edge ofthe diode. Such an effect is probably the cause of thedarker edge region seen in the TEM image of Fig. 7.These regions suggest that there might be somenonannealed point defects near the junction edges,and it is possible that these defects also contributeto higher leakage along the diode perimeter.18 Thisis substantiated by an area/perimeter analysis ofdiodes of different sizes. Typical characteristics areshown in Fig. 6 for diodes with sizes of 2 lm 9 40 lmand 4 lm 9 20 lm, where the comparison showsthat the latter diode with the smaller perimeter isless leaky. The metal acts as a sink for minoritycarrier (hole) injection that therefore increases asthe junction becomes shallower. For junction depthsbelow 20 nm, this hole injection can become com-parable to the electron injection into the substrate,and the total current, including the reverse current,increases. Moreover, the doping of the junction canbecome so low that it becomes completely depleted.

Table II. Summary of junction properties after implantation and laser annealing at 1000 mJ/cm2

Laser EnergyDensity (mJ/cm2)

NominalDose (cm22)

Implantation(Tilt Angle)

Implantation Dose,SIMS (cm22)

JunctionDepth (nm)

Sheet ResistanceAvg. (X/square)

1000 1 9 1015 7� 1.05 9 1015 20 2201000 1 9 1015 30� 7.98 9 1014 18 2751000 1 9 1015 45� 7.43 9 1014 15 311

n = 1

line 2 40 m2

dash 4 20 m2

Tilt = 7 , Q = 2 1015 cm-2

Tilt = 7 , Q = 3 1015 cm-2

Tilt = 30 , Q = 2 1015 cm-2

T = 100 C

Fig. 6. Current–voltage characteristics of n+p diodes laser annealedat 1000 mJ/cm2, for various implantation doses Q and tilt angles.


This leads to punch-through phenomena that alsowill increase the current through the diode, and thereverse current can even be increased by decades.20

Such effects can prohibit the reduction of the leak-age current to the low levels obtainable in conven-tional deep n+p junctions. Nevertheless, forjunctions formed by implantation at 30� tilt or witha dose of 3 9 1015 cm�2 implanted at 7� tilt, quitelow leakage on the order of 7.5 9 10�5 A/cm2 at atemperature of 100�C and 1.9 9 10�7 A/cm2 at 25�Chave been reached. An Arrhenius-type plot of theleakage currents measured over the temperaturerange of 25�C to 125�C in Fig. 8 confirms that atroom temperature all types of analyzed diodes havean activation energy (Ea) close to half of the band-gap (Eg/2), indicating a strong influence of genera-tion–recombination currents. However, at elevatedtemperature, the Ea extracted for the diodesimplanted at 30� tilt or at 7� with a higherimplanted dose is larger due to a stronger influenceof diffusion-type currents, and the diode behaviorbecomes closer to that of an ideal diode. Therefore,the analysis of the diodes in forward bias was alsodone at 100�C.

When the diodes are forward biased, the influenceof the residual defects can be identified as a devia-tion of the slope of the I–V characteristics from thatof an ideal diode with ideality factor n = 1. Theextracted values of n, as well as the reverse leakagecurrent at �2 V for the six diodes from Fig. 6 aresummarized in Table III. The larger ideality factorscorrespond to the diodes with larger leakage inreverse region, and nearly ideal values are obtainedfor the diodes implanted at 7� to a dose of 3 91015 cm�2 or at 30� and 2 9 1015 cm�2. The area

component of the current at a forward bias of 0.3 Vwas extracted from the measurements of diodeswith different dimensions, and the results are givenin Table IV. As is evident from the extracted values,the largest area component of the current isachieved for the diode implanted at 30� to a dose of2 9 1015 cm�2, which is the diode with the shal-lowest junction. With the scaling down of junctiondepth to the sub-20-nm range, the holes injectedinto the cathode from the p-substrate travel a veryshort distance before being recombined at theAl/Si(1%)-Si interface, which can result in a holecurrent that starts to become comparable to thecurrent of electrons injected from the cathode. Onthe other hand, the electron current has littledependency on the junction depth, since the activedoping level inside the n+ region is close to themaximum that can be achieved and a few nmchange in the width of the micron-wide, lightlydoped p-side of the junction will not have a signifi-cant impact on the electron current. In accordance,the high area component of the forward currentconfirms that the 30�, 2 9 1015 cm�2 junction isvery shallow and has a hole current of the sameorder of magnitude as the electron current. The holecurrent can therefore not be neglected.

The possible improvement in leakage current andideality factor obtained by increasing the implan-tation tilt angle was investigated further by fabri-cating diodes implanted with As+ ions at 45�.However, the additional tilting of the ion beam ledto a significant increase of the leakage current,which can be related to the extremely shallowjunction, also under the oxide edge where interfacestates may then have more impact on the diodeperformance. As another possible enhancement ofthe process, it could be thought that a larger overlapof the junction with the oxide could be achievedby PECVD deposition after the laser annealing

2 40 m2

4 20 m2

Tilt = 7 , Q = 2 1015 cm-2

Ea = 0.49 eVEa = 0.52 eV

Tilt = 7 , Q = 3 1015 cm-2

0.77 eV @ 100 C, 0.44 eV @ 25 C0.89 eV @ 100 C, 0.48 eV @ 25 C

Tilt = 30 , Q = 2 1015 cm-2

0.74 eV @ 100 C, 0.59 eV @ 25 C0.70 eV @ 100 C, 0.56 eV @ 25 C

1000/T (1/K)

I/T3

(A/K

3 )

Fig. 8. Arrhenius plot of I/ T 3 of n+p diodes laser annealed at1000 mJ/cm2, for various implantation doses Q and tilt anglesmeasured at reverse bias of 2 V and temperatures from 25�C to125�C. Activation energies (Ea) are extracted for each diode and arealso listed in Table III.

Fig. 7. TEM image of the edge of a fully processed junctionimplanted at 45� and laser annealed at 1000 mJ/cm2, with a darkregion of Si near the edge of the contact opening that indicatesincomplete epitaxial regrowth.


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followed by the opening of a smaller window to thejunction, possibly by using inside spacers to reducethe contact window size. Nevertheless, experimentsin this direction were not successful and resulted ina large spread in the I–V characteristics with a highfrequency of high leakage. Poor performance of thediodes processed in this way can be traced to thepoor interface of the PECVD oxide to the laser-annealed silicon, which cannot be passivated by thestandard alloying in forming gas. A better interfaceto the PECVD oxide could improve the quality ofdiodes made in this way, and promising results havebeen obtained for the inductively coupled plasma(ICP) PECVD oxide deposited at 250�C, which has asignificantly lower concentration of interfacestates.16

Sheet Resistance

Using van der Pauw structures, sheet resistancemeasurements were performed on the n+ ultra-shallow laser-annealed junctions specified inTable II. The results as a function of laser annealenergy are plotted in Fig. 9. The increase in sheetresistance with higher tilt angles can be correlatedto the reduction in implanted dose and junctiondepth that are determined from the SIMS mea-surements of Fig. 5. The influence of increasing thelaser energy is to increase the level of dopant acti-vation, which is connected to an improved degree ofrecrystallization of the region amorphized by ionimplantation, thus lowering the sheet resistance.For laser energies above 1000 mJ/cm2 some meltingof the crystalline substrate also starts to occur,

driving the junction deeper.12 The optimum energyin our case is therefore in the range of 1000 mJ/cm2

since the amorphous layer is then fully melted andrecrystallized, while the LIPSS do not yet appear.Moreover, the spread in the sheet resistance valuesbecomes smaller at higher energy densities. Theminimum sheet resistances are obtained at thehighest laser energy density investigated of1000 mJ/cm2; namely 220 X/square, 275 X/square,and 311 X/square for 7�, 30�, and 45� tilt angles,respectively.

The junction depth predominantly depends on thedepth of the region amorphized by implantation,and the decrease in vertical range achieved byincreasing the tilt angle of the impinging ions is asuitable means of controlling the vertical dimen-sions of the junction, as seen in Table II. Moreover,the larger lateral overlap of the oxide isolation andthe implanted region reduces the junction leakagecaused by the enlargement of the contact openingduring the premetallization removal of the native

Table III. Ideality factors and activation energies extracted at 0.3 V and reverse leakage currents andactivation energies extracted at V = 22 V for the six diode measurements plotted in Fig. 6


ImplantationDose (cm22)

Size(lm2)

IdealityFactor

Ea

at V = 0.3 V (eV)Reverse Currentat V = 22 V (A) Ea at V = 22 V (eV)

7� 2 9 1015 2 9 40 1.13 0.56a 6.2 9 10�9 0.49a

4 9 20 1.12 0.55a 2.7 9 10�9 0.52a

7� 3 9 1015 2 9 40 1.05 0.82b 8.3 9 10�11 0.77b

4 9 20 1.04 0.83b 5.9 9 10�11 0.89b

30� 2 9 1015 2 9 40 1.04 0.80b 10.7 9 10�11 0.74b

4 9 20 1.04 0.80b 5.9 9 10�11 0.70b

The measurements used for extraction of ideality factors and leakage currents were performed at 100�C. Activation energies are extractedfrom measurements in the temperature range between 25�C and 125�Ca and between 75�C and 125�Cb

Table IV. Area component of the current extractedat V = 0.3 V at temperature of 100�C


ImplantationDose (cm22)

Area Componentat V = 0.3 V (A/lm2)

7� 2 9 1015 2.90 9 10�10

7� 3 9 1015 2.62 9 10�10

30� 2 9 1015 8.96 9 10�10

Fig. 9. Average sheet resistance over the wafer as a function oflaser energy density of n+p diodes implanted with 5-keV As+ to doseof 1015 cm�2 at different tilt angles. The vertical bars extend to theminimum and maximum measured value for each laser energydensity and implantation angle.


oxide in HF solution. On the other hand, if the sheetresistance needs to be minimized, then the deeperjunctions implanted in a more vertical directioncould be a better option. Attention must also be paidto the loss of the implantation dose from thereduction of the effective dose seen at the wafersurface, as well as the reflection of ions which aresignificant for the implantation at higher tilt angles.

Previous work has shown that the tilt angle of theimplant can also have an impact on the residualdefects after the implant/annealing in the regions inthe vicinity of the implanted region.18 Duringimplantation interstitials are injected into the sub-strate, and these are not completely annealed out at400�C, which is the maximum processing tempera-ture used after ion implantation. The effects of thishave been detected up to 0.6 lm away from theimplant itself, for example, as a reduced breakdownvoltage in devices such as back-wafer-contactedvaractors and bipolar transistors.21 When injectedinto boron-doped p-type silicon, the interstitials alsocause a significant level of dopant deactivation22

that is readily detected by C–V profiling, an exam-ple of which is shown in Fig. 10. The profiles of theactive boron concentration after implantation (solidcurves) show a strong dependence on the As+

implantation conditions. The boron deactivationincreases with dose and decreases with increasingimplant tilt. Therefore, using a 30� tilt is alsoadvantageous in situations where the backgrounddoping and defect density play a role in deviceperformance.

CONCLUSIONS

A simple, low-temperature process flow forachieving good-quality ultrashallow n+p junctiondiodes has been demonstrated for 5-keV As+

implants activated by excimer laser annealing.Several generally applicable guidelines for achiev-ing good diodes can be established on the basis ofthis work. With respect to the bulk, laterally uni-form part of the diode away from the perimeter, it isimportant that the Si surface to be implanted issmooth and free of native oxide before implantation.The implant should be so shallow that the meltregion encompasses the whole implanted region butdeep enough to avoid laser-induced surface struc-turing effects on the Si surface that may affect theperfection of the underlying metallurgic junctionregion. Tilted implants can reduce the final junctiondepth of the 5-keV implants to below 20 nm. More-over, they can also significantly reduce the numberof interstitials sent deep into the substrate, whichmay otherwise cause background dopant deactiva-tion and leakage currents.

With respect to the perimeter of the diode, the keyto achieving good-quality diodes is the ability toterminate the metallurgic junction at an oxide-to-silicon interface that is of good quality. In these

experiments this is achieved by using a thin layer ofthermal oxide to cover the Si under a thicker low-temperature isolation layer. After the growth of theisolation oxide, all processing steps are performed attemperatures below 400�C. Here a 30-nm-thinthermal oxide is applied, which is still sufficientlythick to avoid excessive widening of the contactwindow during the dip-etch used to remove nativeoxide before metallization. To localize the lasermelting of the silicon to the desired diode region andparticularly to protect the perimeter, a reflectivemask of Al is applied. A thin layer of Al is usedtogether with one-shot laser annealing to avoidproblems with the post-laser-annealing Al mor-phology. Tilted implants increase the overlap of theoxide isolation with the diode perimeter, thusmaking the process more robust and reducingperimeter leakage. The completeness of the lasermelt at the perimeter will depend on the thermalconductivity of the surroundings. In the presentexperiments, less melting of the perimeter withrespect to the bulk is identified by TEM analysis,and this may be a source of extra perimeter leakagethat should be taken into account when designing aspecific process flow and diode structure.

The best results are achieved here with animplant of 2 9 1015 cm�2 at tilt of 30�. For diodeswith an area of 80 lm2 this gives an ideality factorof 1.04 and reverse leakage at �2 V in the range of7.5 9 10�5 A/cm2 at 100�C and 1.9 9 10�7 A/cm2

at room temperature.

ACKNOWLEDGEMENTS

The authors wish to thank the staff of the DIMESIC-processing group for their assistance in devicefabrication. This work has been supported by theEU FP6 project D-DotFET, the Philips/NXP PACDproject, and the SmartMix MEMPHIS project.

Depth (nm)0 100 200 300 400 500

1016

1017

)mc(

noitartnecnocnor ob- evitc

A-3

w/o shallowimplantation(simulated)Tilt = 30°, Q = 2 1015 cm-2

Tilt = 30°Q = 3 1015 cm-2

Tilt = 7°, Q = 3 1015 cm-2

Fig. 10. C–V doping profiles of the p-region of an n+p diode fabri-cated with a 5-keV As+ implant at various tilt angles with differentdoses and laser annealed at 900 mJ/cm2. The simulated p-profilebefore implantation is given by the dashed curve.


2195

OPEN ACCESS

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