Lojik Devre Tasarimi Ders Notlari M UZAM

LOJIK DEVRE TASARIMI

DERS NOTLARI

Dog. Dr. Murat UZAM

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, G;r ;p dt4ir l r*" ter in in sqqrsrnrn b)aJV ol ,*r5o. &",,*rnJ.,- R.OM lr.llo^ît , PLA L,,ll""-1 ma3 a , [ rc Jahê eLanon. ' ,LI{r . FoL-e{, g, ' r is

td- f l lL-* lo-r i " ia s49 tsrnrn , ,oL olmrs t c latrumvnd)\ PLA'lar R.,C U'/oiJon tlt ha €jarrto,ytt 'Lt 'C

Oo)h/ q0n, J

= Ats+ AC

= B *Ac

= AB=Ac

mor*puIf ,n"/-'o *

roP F.(A.B,CJ'X*.( o,f,q,6 )-- Ft (,0, B,c)"e (2J,r., ,4,+)

FrU, B, c) = X,.( o,/, L,6)

% {o ,B,c) = 2.rn ( z,s,r, l ,?l+Be+B

- l*--,'r.'t/o.i (P,oolu.l /e.rms) GVa J.jzkr)"okl-\ Ji)zl*,r&l.i"* C" r Ptm

u4gun ,garle-z ot/ \nAl.a. la,t ta zlz--,nan lo. i i= ba-glan6. 'e,t ,u!q .qerr,eL/ ,ZFh ' , , .1 i r , .Ee^.* . i7 /z -nn 0e d j r le , * ind t

" ,L ,5 { -nLuS;qo, i l c - r ,nda

fzulla,,rlhal,L Azs<- 9 a,t"llt*t .1e-im/<r,' i<,'n & go p, l,'r, J

Br. PLA nnt,t

/, rh' l<L,' l ir.

AB 1 AEnc+BAg+BL

^- "_ .e"? ! ! .& ! "E .q . r .

A D ' - . . Ip*i i* cauple62a{.o f,

L1 ,'k- Aa1 f \o.

!-"3k Arr"y (nr-n)

ANbp /ar*

0(P f"u

,B;. PtA ,^ L^f , L0M_'un -gop fr3, , iFle, .ni giplc n g, ' r , 'S l ; , ve hg,LtSlt !,',

'P tA n ola,|b^N

' rh *ory foitr_s,l,lon, k_44s;l a&-Lil,'r.

Bl, PLA'n, n rq gopit) R-oM',afa'aafu) ' Q.Zl{J,r" R"'on4',j;L'

dc-codn., ( Lnd ,r+f.tJ yerir,z, g/rfp., {o4.|F/rzn /en'ni.-t Se+i/m,',1: !P,h, ! ,o,r tnt q. l qn b, ' . AN6 di , ,?*k.rrr i nM)ue)f fur , Pt4 'J; /u 'OR slUzk-it ' ise, q,hf, fo"hlTôa fa.,n., nu41d-nn .g"*r .*,oL r'+i^1c.e{u-n qarprm 1-e-im/eriai "02 , 's/<n,'.d k1,." /okn

i c,":i{i, loi,ih'r,'lîS Ll. Joprr/,r1. kb/"s, i/e /u-

Fro ducl*

-&^-fB

. = ,AC

";;:;p'f;*"ABc

ort/pr/s

n Ft f rF"

00- t t 01o

| 4 A01- 0B tc ( ol

Bd 4oo co,l 0.AC -4 -\{ i oo o 4

Fs: Ac+B

nol pr<sur/

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"o* cit^pleryankJLOJİK DEVRELER DERSİ --- DERS NOTLARI KISIM 2 http://host.nigde.edu.tr/muzam/ Doç. Dr. Murat UZAM

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PROGRAMMABLE LOGIC DEVICES

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PROGRAMMABLE LOGIC ARRAYS (PLA)

Yl . f qi 'b^t -Tas.?0wi "

A

B

c

BC Ac

gE AC

s\r. .-_k$*f_*- c \

B *p*l a= A.B I/

Fo

-Fz

Fs

t*o

r l

F.

fr

AB Ac

A

B


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PLA

,/

6le- P tA

plarC

cross - poinlI)iI\

t"1. bw.Ti,s. 3!.

PLA , F PL+, r )

,onhcl

Sigor{c

/vlasL -pro7ldrnma

Bosi| lelt ir i l rYI r S b i . FPLA

\

F;eld -p.t6rt^rnqb/e( - U S L

"

7iD',- r I

\

r"*r.$*1--t

I

- - \ .

ilonu tdl;Ll"-, n* BirqolL FPLA art*<n-l*"nole

f /nt n *e-s, 'ai ( e-t/ rt ' ; , 'n;) -

al/mqga

A -'--lt-.B +)L>AI7

(4 ) r lon t 'nWSba

' * B i rc ,o la FFLA'Jb," . bust lg /.onwnlu qrletSla r trqrdrn

I.o

I* ! - -

ie '

y,*t-0"

0'

0t

03

;

,'S/<n,' /u/" fia&-gdn#dn X0K

AB

\ fu.. t lo*^

(. b ) hvr'sion

' q ( L,^- l t") ta51/"ndg,

c,, Lr s ftnL-1,'tlon/n -

Lopi/ "", or*i-l lut

4 -lT\,_- C&-J)J

c = A-B +AE',{A | -_c-ool

-o ' -t l l {I o l 4I t l O

s c$larrra la f q in

e------


oc

^= AsA,+ ArArh+ A;EIIAA,I ,bo= IrFr*A.[r hilE rTs A,A"i#"fur-', u t-o

d=4 A^A,n*lr@rlriLtAsA-l,t A3A1A,

rfc7

!

t ft0

0

8tItt,0

t= ACa_* Fl A, + 4'4,!ao o\ t t t

9 l

t l

lo

4o= As A, Ao+ !tA, An f = h A"4* Arlrtr,* trrn,**7,As ArA,+ trrA,A"t Asfl"A,

'rJ0fl t

tO

Ctt l

l0

Q/'


LoJ, De^/, %s. %

f ,h,h'e,J )l r (^ ,b , c ,d )

= : ; ( t ,9, fn i , 2,1, lo , t t , !3,45)= x* (" ,3, i 6,?, 10,4f , l t r r ' t5)=2^ (6 ,77t7 , t3 t14, ,5)

.b

IT

III

J.4

f^L r , ' qo r r lo f rn t L - f . PLA/.v ll odn l- ge.qeL/e5lr'riniz.

cd o 0 \ t t l 0

0colr l

t0

0 t

l l

l a

( I

ab + bJ+Lc. fz= c+ 6'bJ fr= o[;+ q7.l+Le

PLA loblosu

ft

",8gdb.cc

6,b,eqbe

Icl ccl

bc

4 0 0laot o o040o10.a 04a 0 4oot

| 0 - --4-l-0 | ---t-0t - |400-4-04' { | .

1

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t.o".f,' ; fii;*{o' "L; f"J;'j, ",t il:

U:;Y; Io"'tlonJo'c"aLt*,

As

A2'

A, **J-

Ao

I

al

b

c-

Irg

ao?

aa


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/-"j. bo;t ' ks ' 331

s39 | PROCRAMMABLE LOCIC DEVICES (PLDs)

I coluntn is prognrrrrnctl in thc AND planc lor thc procluct tcrrn A.1A2z1 1Ae and con-nected in the OR plane to thc row lbr segments b and c. This procedure is repeated foreach product term and segment. A colored dot indicates that there is a contact at thecross point. The cross points for the XOR output gates are blown, so the functions areinverted and are thus active-LOW.

,u l i t 10 -7^ rvpical I:l'1.A.

A specific FPLA 'fhc

82S100, shown in Figure 10-12, is a good exanrple of a com-mercially available FPLA. lt has 16 input variables, 48 product terms, and 8 outputs,and it contains approximately 2000 cross-point fuses.

- o

" l

' 2

' 3

i , ,

t--

I-o

T

t^

13

I+

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13I?

r,oJrr't t 2

rtar,,

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L oj . be't- Tos. SlL

2- Frog.o-*otle *r.y |-ogic C PAL)

Br, PAL Ok d,|zle*,|ni,q sLi{ r'e AN b "t^:''.l**oi^,'.t largrenl'**

L;l;, olslr,,r i" / 'ztJ b,'r PL4 Jirtf ir. PAL', 'a .qaptst f"LA'fln ahatptstnt4 ctt ntoln S o 4.n AN A slhl*-; prqqrf,nfu,n$,'/,'r o I {niiu .''1'htifit

, PLrt'J" 96ro e?_'tutaofur vL "/^1e

kofug -prq,t.qnt lEnz6i/,'c

C

7r,,/* o,rp,u*' ; tP

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3 ]ar rz qqrPt r \

3 d*i,\ lr4; (ket'pti vqr

3 g'", i) Ya"'

L q ,h^h iv 3n[

y ' ^ ^ - - . YIt-- kyz*xg+y?+ Ygz+ xSz

r -- l,i \Yun "

'-- U::il- iarino "

l

i;

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PROGRAMMABLE ARRAY LOGIC (PAL)

Loj. b*,Tqs. 3sOrr"l, PAL l(a,nrL,*.-;rHLl"-,,

-TY ̂a No'

p$LtOHS

PAt lzH 6Pftt-t6c 4PnuzoLt

glh,mhsvelufi-

ser;a( Jo+c ou{

No. oFrapv4

,l 04z(o20

i lo ,o fa'{nvfl

5 nr[. !*. (r2,?, i,2, 4I 4^/a- o A/N,q " -'

' 'E A Na -NaR 't

P4LLi. va

"A,"at{l;r.,^ !. b qatlt/foz/" 0e- haftsr

i /e hso., o, (,r dpct.It-r .b,'r L- r, #; PhL', e-

/d;L l+

n 4ti,,l oo h -,,h-elvct-, I Au /rnon

s r$a roL_u S eJ*'/dn_ soit JoJi;V:[,'. PLA

'tt q/t'm frr&", J":, ,4-41 fu,'n,k-,' L,>ohn

pay{esttar+-ul,

PLS . gTqoL+ A;. pnL ;/q agntoltn TLL fr.tteL o la.o t

f ffitrfrllriZ"r n -', J7, ; / a, ffi' "t' :/* L7*', /ni rc,2t s

_" d n-

s i i,r/, tt Ytr *Hl;'- + ni/i,,:, # i,rt :r{ ,: , : ' :^^1,^:*t:

,4 b,"//,t< Po.ate.t sirfT /, ' - scri qohtslr

3' , hg^^*^n L/< Logic Sequ<."os ( p LS )

brr |h;f/ ,4t4lskr *otso.ldltntz.

\" \, Q. ,be

sh;ff f lo"A

c l oc lc

1r bi+,ro.ql lc. l ia

J"., ot I o" I


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sEcTloN 10-8REVIEW

TESTINC ANt)

10*9

f lcuRE 10-76Slock diagratn for c

{ 81 9-<o5 t,52] J

J 5

. l {w$wi f . ] j : -? l . " . " ' ] : { : , . i * l . f : ' ! i s i - ' - ' | . ;#* i .1 . - . l t . i , : } ' s r . j ' " i : : ! l . ' . t { j t : s . !w ; . j r {4 t i4ELOJİK DEVRELER DERSİ --- DERS NOTLARI KISIM 2 http://host.nigde.edu.tr/muzam/ Doç. Dr. Murat UZAM

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R-ug,'s /*.- T rantk- vL tlL,l..o iS futn lt (M|ct" '7"-h;",:)

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"r'iy k

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do;i's,'L- s{sl.-"bIL'i. L',-,'h/ L,'/e,iouo, oh!=o,l1"n,"0/a moal;h-. L,'-

i;^/"*' l ; l lî, l , i 8u u,nodsllt-" Lr"o.n Sa!/e.,,, s,aolu,-f,f /, 'r l<r i

ra<t s#r s .t oLr-q/us ( LoJ ,A;'..ikr) , o)itl"nA'L L,'.,'o, /t. tt\<- .l , - ; /* / t i ; ' , 'L.Ru el.eQ,"s, 'L tnorb//"- " . tbk

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s t t ^ ^ ?

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d?b;/, ;/n--/e -t1 ep,/a n is /-- /t) ; / "

f-a n rn /o n,..

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d! Jafo Ln-,s 9l/g; ;;t-erio&-,g.q,/1n /.-;21 ,Ltt ,, ';,f*oI r.)s /d- -v t t 'a soauc.( t b ,^ ; re-ê/sF-Q/ ' t , , 'bv /unan L i . o '44*r ,2 ' ' l ' (br ' .u ' . , .g)

d,'lg4q1 d4,^7/;n-L;/,.', ;""l^ ls.lo-,n,f"?uc-<r , LosAo .b[r ryrrry',*ro-î{.< u-d,'//.. /4,'Lrou;2/e-vt .6'r)Lff,?"frn tt!#7tl,W , @un *'(s,oXrr.â)

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t'e i a L- ll; n, I o n Setn b. l/L no/os.qon (rvo /.t*'on )' o r<'<,b /-<- /n"s fr-

/one uae4 ( "lr'/,,') J.-, /r, "Pt",'s {tt- /-'ens{'u'" frt,"m"

- bilr> /,'1"* m''Lt-

, '7 l r ) r r 'y^bb, ' l ; t tL Y( is /e- - t so4uct ,nvn. qgnl "zpfsk '1 F* . .

L,'. bea rtrs ry-p/s k 'q'

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tl---*$,7** . --*.JI PS(H)- l" PJ( L)J

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p".o /lo.( tnor&-

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A <-g

o"2r .,ii;, 8" "*":; \ii,e, ;, 7'zX r L "Ir!: r,*ti. 0L

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,to o/&iunoto u"*r" id 9"7;rr!tf: ; 7 - ;'/r'-g","4

,+J t ,4 <-- B

\-/-'v--J \-'----Y-

boof- m il,-t-Con lcs,'9oa,r it lot

(,t<-e1(r4 <-E)

P; A<-8 =,f(p=l)ttr^

=,f(x,,y=1) tlu,t

cloelz

P f ) P: '4<-B

I P=4 o 1.1..,3-u nda

A g" . lc{. . ' l rn

7x+l ; A-B

,zgo g'4aa Li . i

o lJ.,3u .o^- n B

5 " aLl.r'l'r.

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d.424 t <.-

L;r rapis/<r'ig tsl-..'",' .

P'l(o-r), P.2(L) iI

R2 <-- Q,l _T

Ij

A",R, iIJ

P: (;f p.t) ]-tA<-8, tse-A j

I

I

i^&'s 1". rj,\|v.,)t",'. 6,.h'

ih.-Ll< t

, - lr t aQe | | il"' a i L,o is h.','

bi r L in'a u^ dX 'r,r

- Wlii|*,,r*n

T; B?,*- 2l ., Rl<-K-2

se.-Z | /-_ ",A-Se-, l*^s{.-/2 An-^ -^ L.6.- L ( s,.t,,a.) hi-^ &_ a"_J"f (J"rt^, _

6on) r-e-jr'sl.-l.art sh''fl - Xt e,S*o /aro/'r. 8,,/q,, L.-u^, L r.4;:-lrotz n h. d-f r-<a,'51<-r< L,-. zz,vt-a zJ,q L,..

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- :-;- ;--T;A ^v-'P*t-iL=41!61b::*4; Pa='l ,

o lo I q T o x co lt I o I o x or\rl o lx'l ,rr l'r [ 4 I x o

il ft-1-,- e'-t

5) /g='1 1fi<- shl A i At-.,74^Jz Au-aLl5'i,ir l t -Ol'^" rr3lskr o laratz

i"to d-Bt<

50

clhilcna

43' in q ' lo l r

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A'2--"At 'Xe ; 4z rr ia +t* ' r '

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o r-r,Jq

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\ Ps tt..J

selc LtTl'r"'t i< I"

n;.? 7 rv ol^tl 'J' 'Yni.? )Jk,'Ltrfl;p-tt"r

b6\l-l;U"- s't' L4J'

T*i= Ai-l

Ku--E

N

/-rL YoLlor'

T*;=(Ai-)' Prg*rdE;'P'

-

AitA'/,.4'


6) Pt-- lrAe-sAtA

Jn--(At"). Pt. , - - .Kat e lAia). (6

7) P7--l , A <-A+l (syrc, gibi d$l"i i2 gr"1t.. '- i l

lnl. A*,Tis. e I

JOsr

SertLr-a ,a qs&aL".-n olrw/<- J >-.rt /L' l'J ' sa'J te1 t'dreiA Eun$

CP Xtr,'11n .i ol'{r lc aldagunCon seaLrcn soy'u /tsenmt gtp'/ma/'Jtn

fK Fltf-ft"fa"- ^lrr;l"i,,if,LL'oa (Pomtel) sogtc-t rlin b'{ sog's1

6,-.-, l" d4il J rr ' d'nj'''a

F[-t

.P

Kc--1 ,

Tt=Ao !z--- A"A,(1--Ao k1-= Ao A,

Ei-- €t4 . At,-l

Ft+t- €t, At s lu r'

Tet= €tt f ,KAi --€t-t J

A<- A-l isk^Itna m/. Ji2-e.r,'nin

4 s.A 'ct eLL eal

sulFo4 (

Eo=l

bil,z c

cta t I ra v

n t,il/;L

!n; " €t-tKnt=-€{-r

sa ol,t':, h*

3ini lzriat-

1 I l - |(o'nlc/) s"g'ctntn *4L'14t' '

| -a €o= P7

. , |

&;,'/ ( lr-^//.,'uat / q tuf leflh-

,^i baX/"\'U.' csait saganolan a3o. L,rc


8) Pa=f A r."sts{..,^/.1-' bi$i Q /s<- /al oto-L bi'L*'T"s' 67

,,,L7h"Jon biri sr QrJa n

parLlr isz Z=O oll r.

B,!y'in ettaf lqr stfir i.lz-z-tE=/ z-=i "tl.

frll-l L".o"lo na'1" atttttt-l 4 t L-c'amety tz'

AnCItski

Ai+r 4i*r

Z1?o=P3

?I+tZn*l

Zo=?8= | e t - - r t ' ' l ' - r - l ' r

Zn+l= ' l ise -> A=o'J'r ' ' , , l t* l=T ' 7i

,,, +:,g:i)= i: i tg'ra S ;;'lik ^i ̂ i'' " A"' b i' pa r q a !'l'l Q t n

a1^9,o1;L foatosisoataa ::*

-

+?r(A.-t)+ fuCAt*)+ Ei

tAi= A(Bi@o') * tt * ,0,** ,"ir;i. p6(ffii)+€i

KAi-- f,cB;ao')+P2'

fc-- eLr 'At-r

E" -- P? , 1-, ";rr,n

alz lr-o- bi'-s go'ol {e've

, r,,.h,ten !,liio,o,r,,", ̂ ',ik''"L:IL : :"';.'.; + B;' ci )

cl"S'* o (AlBi*Ci+l - - ' t ' -

zi' Zt-t ' k-l

Zo = Pt L ̂ - Jn. L, u -i/-"'F /*' lttl

, - h,^ L;bt d.r":AftLT,,|u,1,"

"-rfL,ff''' ^' &''/'te q /'-'"'1'r'''


f tcuR[ 10-75Th. PAL|bRl rost.rrDxtl)l. h,Nk s.lu(rQt


5-1

FAST AND LS TTL DATA

SERIAL-IN PARALLEL-OUTSHIFT REGISTER

The SN54/74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Regis-ter. Serial data is entered through a 2-Input AND gate synchronous with theLOW to HIGH transition of the clock. The device features an asynchronousMaster Reset which clears the register setting all outputs LOW independent ofthe clock. It utilizes the Schottky diode clamped process to achieve highspeeds and is fully compatible with all Motorola TTL products.

• Typical Shift Frequency of 35 MHz• Asynchronous Master Reset• Gated Serial Data Input• Fully Synchronous Data Transfers• Input Clamp Diodes Limit High Speed Termination Effects• ESD > 3500 Volts

CONNECTION DIAGRAM DIP (TOP VIEW)

14 13 12 11 10 9

1 2 3 4 5 6

8

7

VCC Q7 Q6 Q5 Q4 MR CP

A B Q0 Q1 Q2 Q3 GND

NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.

PIN NAMES LOADING (Note a)

HIGH LOW

A, BCPMRQ0–Q7

Data InputsClock (Active HIGH Going Edge) InputMaster Reset (Active LOW) InputOutputs (Note b)

0.5 U.L.0.5 U.L.0.5 U.L.10 U.L.

0.25 U.L.0.25 U.L.0.25 U.L.

5 (2.5) U.L.

NOTES:a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

Temperature Ranges.

SN54/74LS164

SERIAL-IN PARALLEL-OUTSHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 632-08

N SUFFIXPLASTIC

CASE 646-06

141

14

1

ORDERING INFORMATION

SN54LSXXXJ CeramicSN74LSXXXN PlasticSN74LSXXXD SOIC

141

D SUFFIXSOIC

CASE 751A-02

LOGIC SYMBOL

1

28

9 3 4 5 6 10 11 12 13

A

BCP

LS1648-BIT SHIFT REGISTER

MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

VCC = PIN 14GND = PIN 7

5-2


SN54/74LS164

LOGIC DIAGRAM

Q6 Q7

A

B

Q0 Q1 Q3Q2 Q5Q4

MR

CP

D Q

CD

D Q

CD

D Q

CD

D Q

CD

D Q

CD

D Q

CD

D Q

CD

D Q

CD

63 4 5 11 1210 13VCC = PIN 14GND = PIN 7

= PIN NUMBERS

1

2

8

9

FUNCTIONAL DESCRIPTION

The LS164 is an edge-triggered 8-bit shift register with seri-al data entry and an output from each of the eight stages. Datais entered serially through one of two inputs (A or B); either ofthese inputs can be used as an active HIGH Enable for dataentry through the other input. An unused input must be tiedHIGH, or both inputs connected together.

Each LOW-to-HIGH transition on the Clock (CP) input shiftsdata one place to the right and enters into Q0 the logical ANDof the two data inputs (A•B) that existed before the rising clockedge. A LOW level on the Master Reset (MR) input overridesall other inputs and clears the register asynchronously, forcingall Q outputs LOW.

MODE SELECT — TRUTH TABLE

OPERATINGMODE

INPUTS OUTPUTSMODE

MR A B Q0 Q1–Q7

Reset (Clear) L X X L L – L

H I I L q0 – q6Shift H I h L q0 – q6

H h I L q0 – q6H h h H q0 – q6

L (l) = LOW Voltage LevelsH (h) = HIGH Voltage LevelsX = Don’t Careqn = Lower case letters indicate the state of the referenced input or output oneqn = set-up time prior to the LOW to HIGH clock transition.

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 5474

4.54.75

5.05.0

5.55.25

V

TA Operating Ambient Temperature Range 5474

–550

2525

12570

°C

IOH Output Current — High 54, 74 –0.4 mA

IOL Output Current — Low 5474

4.08.0

mA

5-3


SN54/74LS164

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Symbol Parameter

Limits

Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs

VIL Input LOW Voltage54 0.7

VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage

74 0.8V

Guaranteed Input LOW Voltage forAll Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage54 2.5 3.5

VVCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth TableVOH Output HIGH Voltage

74 2.7 3.5V

VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table

VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN = VIH or VILper Truth Table

VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA

VIN = VIH or VILper Truth Table

IIH Input HIGH Current20 µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH Current0.1 mA VCC = MAX, VIN = 7.0 V

IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC Power Supply Current 27 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

Symbol Parameter

Limits


fMAX Maximum Clock Frequency 25 36 MHz

VCC = 5.0 VCL = 15 pF

tPHLPropagation DelayMR to Output Q 24 36 ns VCC = 5.0 V

CL = 15 pFtPLHtPHL

Propagation DelayClock to Output Q

1721

2732 ns

CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C)

Symbol Parameter

Limits


tW CP, MR Pulse Width 20 ns

VCC = 5.0 Vts Data Setup Time 15 ns

VCC = 5.0 Vth Data Hold Time 5.0 ns

VCC = 5.0 V

trec MR to Clock Recovery Time 20 ns

5-4


SN54/74LS164

AC WAVEFORMS

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delaysand Clock Pulse Width

Figure 2. Master Reset Pulse Width,Master Reset to Output Delay and

Master Reset to Clock Recovery Time

Figure 3. Data Setup and Hold Times

CONDITIONS: MR = H

1.3 V

1.3 V 1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tPHL tPLH

CP

Q CP

Q

MR

trectW

tPHL

tW

I/fmax

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V 1.3 V 1.3 VCP

D

Q

ts(H)th(H)

ts(L)th(L)

tW

1/fmax

1.3 V 1.3 V* 1.3 V

DATA SHEET

Product specificationFile under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT1658-bit parallel-in/serial-out shiftregister

For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT165

FEATURES

• Asynchronous 8-bit parallel load

• Synchronous serial input

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT165 are high-speed Si-gate CMOS devicesand are pin compatible with low power Schottky TTL(LSTTL). They are specified in compliance with JEDECstandard no. 7A.

The 74HC/HCT165 are 8-bit parallel-load or serial-in shiftregisters with complementary serial outputs (Q7 andQ7) available from the last stage. When the parallel load(PL) input is LOW, parallel data from the D0 toD7 inputs are loaded into the register asynchronously.

When PL is HIGH, data enters the register serially at theDs input and shifts one place to the right(Q0 → Q1 → Q2, etc.) with each positive-going clocktransition. This feature allows parallel-to-serial converterexpansion by tying the Q7 output to the DS input of thesucceeding stage.

The clock input is a gated-OR structure which allows oneinput to be used as an active LOW clock enable (CE) input.The pin assignment for the CP and CE inputs is arbitraryand can be reversed for layout convenience. TheLOW-to-HIGH transition of input CE should only takeplace while CP HIGH for predictable operation. Either theCP or the CE should be HIGH before theLOW-to-HIGH transition of PL to prevent shifting the datawhen PL is activated.

APPLICATIONS

• Parallel-to-serial data conversion

QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC

2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCCFor HCT the condition is VI = GND to VCC − 1.5 V


See “74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL PARAMETER CONDITIONSTYPICAL

UNITHC HCT

tPHL/ tPLH propagation delayCP to Q7, Q7PL to Q7, Q7D7 to Q7, Q7

CL = 15 pF; VCC = 5 V161511

141711

nsnsns

fmax maximum clock frequency 56 48 MHz

CI input capacitance 3.5 3.5 pF

CPD power dissipation capacitance perpackage

notes 1 and 2 35 35 pF

December 1990 3



PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 PL asynchronous parallel load input (active LOW)

7 Q7 complementary output from the last stage

9 Q7 serial output from the last stage

2 CP clock input (LOW-to-HIGH edge-triggered)

8 GND ground (0 V)

10 Ds serial data input

11, 12, 13, 14, 3, 4, 5, 6 D0 to D7 parallel data inputs

15 CE clock enable input (active LOW)

16 VCC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 4



FUNCTION TABLE

Note

1. H = HIGH voltage levelh = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transitionL = LOW voltage levelI = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transitionq = lower case letters indicate the state of the referenced output one set-up time prior to the

LOW-to-HIGH clock transitionX = don’t care↑ = LOW-to-HIGH clock transition

OPERATING MODES INPUTS Qn REGISTERS OUTPUTS

PL CE CP DS D0-D7 Q0 Q1-Q6 Q7 Q7

parallel load LL

XX

XX

XX

LH

LH

L - LH - H

LH

HL

serial shiftHH

LL

↑↑

lh

XX

LH

q0-q5q0-q5

q6q6

q6q6

hold “do nothing” H H X X X q0 q1-q6 q7 q7

Fig.4 Functional diagram.

Fig.5 Logic diagram.

December 1990 5



DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standardICC category: MSI

AC CHARACTERISTICS FOR HCGND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL PARAMETER

Tamb (°C)

UNIT

TEST CONDITIONS

74HCVCC(V)

WAVEFORMS+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

tPHL/ tPLH propagation delayCE, CP to Q7, Q7

521915

1653328

2054135

2505043

ns 2.04.56.0

Fig.6

tPHL/ tPLH propagation delayPL to Q7, Q7

501814

1653328

2054135

2505043

ns 2.04.56.0

Fig.6

tPHL/ tPLH propagation delayD7 to Q7, Q7

361310

1202420

1503026

1803631

ns 2.04.56.0

Fig.6

tTHL/ tTLH output transitiontime

1976

751513

951916

1102219

ns 2.04.56.0

Fig.6

tW clock pulse widthHIGH or LOW

801614

1765

1002017

1202420

ns 2.04.56.0

Fig.6

tW parallel load pulse width; LOW

801614

1454

1002017

1202420

ns 2.04.56.0

Fig.6

trem removal timePL to CP, CE

1002017

2286

1252521

1503026

ns 2.04.56.0

Fig.6

tsu set-up timeDs to CP, CE

801614

1143

1002017

1202420

ns 2.04.56.0

Fig.6

tsu set-up timeCE to CP;CP to CE

801614

1765

1002017

1202420

ns 2.04.56.0

Fig.6

tsu set-up timeDn to PL

801614

2286

1002017

1202420

ns 2.04.56.0

Fig.6

December 1990 6



th hold timeDs to CP, CEDn to PL

555

622

555

555

ns 2.04.56.0

Fig.6

th hold timeCE to CPCP to CE

555

−17−6−5

555

555

ns 2.04.56.0

Fig.6

fmax maximum clockpulse frequency

63035

175161

52428

42024

MHz 2.04.56.0

Fig.6

SYMBOL PARAMETER

Tamb (°C)

UNIT

TEST CONDITIONS

74HCVCC(V)

WAVEFORMS+25 −40 to +85 −40 to +125


December 1990 7



DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standardICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

DnDsCPCEPL

0.350.350.650.650.65

December 1990 8



AC CHARACTERISTICS FOR 74HCTGND = 0 V; tr = tf = 6 ns; CL = 50 pF

SYMBOL PARAMETER

Tamb (°C)

UNIT

TEST CONDITIONS

74HCTVCC(V)

WAVEFORMS+25 −40 to +85 −40 to +125


tPHL/ tPLH propagation delayCE, CP to Q7, Q7

17 34 43 51 ns 4.5 Fig.6

tPHL/ tPLH propagation delayPL to Q7, Q7

20 40 50 60 ns 4.5 Fig.6

tPHL/ tPLH propagation delayD7 to Q7, Q7

14 28 35 42 ns 4.5 Fig.6

tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6

tW clock pulse widthHIGH or LOW

16 6 20 24 ns 4.5 Fig.6

tW parallel load pulsewidth; LOW

20 9 25 30 ns 4.5 Fig.6

trem removal timePL to CP, CE

20 8 25 30 ns 4.5 Fig.6

tsu set-up timeDs to CP, CE

20 2 25 30 ns 4.5 Fig.6

tsu set-up timeCE to CP; CP to CE

20 7 25 30 ns 4.5 Fig.6

tsu set-up timeDn to PL

20 10 25 30 ns 4.5 Fig.6

th hold time Ds to CP, CE; Dn to PL

7 −1 9 11 ns 4.5 Fig.6

th hold timeCE to CP, CP to CE

0 −7 0 0 ns 4.5 Fig.6

fmax maximum clock pulsefrequency

26 44 21 17 MHz 4.5 Fig.6

December 1990 9



AC WAVEFORMS

Fig.6 Waveforms showing the clock (CP) to output (Q7 or Q7) propagation delays, the clock pulse width, theoutput transition times and the maximum clock frequency.

The changing to output assumes internal Q6opposite state from Q7.

(1) HC : VM = 50%; VI = GND to VCC.HCT: VM = 1.3 V; VI = GND to 3 V.

Fig.7 Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagationdelays, the parallel load to clock (CP) and clock enable (CE) removal time.

The changing to output assumes internal Q6opposite state from Q7.


Fig.8 Waveforms showing the data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW.


December 1990 10



PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds) to the clock (CP) and clockenable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP)to the clock enable input (CE).

CE may change only from HIGH-to-LOW while CPis LOW.

The shaded areas indicate when the input ispermitted to change for predictable outputperformance.


Fig.10 Waveforms showing the set-up and hold times from the data inputs (Dn) to the parallel load input (PL).


5-1


4-BIT BIDIRECTIONALUNIVERSAL SHIFT REGISTER

The SN54/74LS194A is a High Speed 4-Bit Bidirectional Universal ShiftRegister. As a high speed multifunctional sequential building block, it is usefulin a wide variety of applications. It may be used in serial-serial, shift left, shiftright, serial-parallel, parallel-serial, and parallel-parallel data register trans-fers. The LS194A is similar in operation to the LS195A Universal ShiftRegister, with added features of shift left without external connections andhold (do nothing) modes of operation. It utilizes the Schottky diode clampedprocess to achieve high speeds and is fully compatible with all Motorola TTLfamilies.

• Typical Shift Frequency of 36 MHz• Asynchronous Master Reset• Hold (Do Nothing) Mode• Fully Synchronous Serial or Parallel Data Transfers• Input Clamp Diodes Limit High Speed Termination Effects


14 13 12 11 10 9

1 2 3 4 5 6 7

16 15

8

VCC

MR

Q0 Q1 Q2 Q3 S1CP S0

DSR P0 P1 P2 P3 DSL GND


HIGH LOW

S0, S1 Mode Control Inputs 0.5 U.L. 0.25 U.L.P0–P3 Parallel Data Inputs 0.5 U.L. 0.25 U.L.DSR Serial (Shift Right) Data Input 0.5 U.L. 0.25 U.L.DSL Serial (Shift Left) Data Input 0.5 U.L. 0.25 U.L.CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.Q0–Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.

NOTES:a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)b. Temperature Ranges.

SN54/74LS194A

4-BIT BIDIRECTIONALUNIVERSAL SHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1



161

D SUFFIXSOIC

CASE 751B-03

5-2


SN54/74LS194A

LOGIC DIAGRAM

VCC = PIN 16GND = PIN 8

= PIN NUMBERS

S1

S0

DSR DSL

CP

MR

Q0 Q1 Q2 Q3

P0 P1 P2 P3

14

1

2

6

7

3 4 5

9

11

12

10

1315

S Q0

CP

RCLEAR

S Q1

CP

RCLEAR

S Q2

CP

RCLEAR

S Q3

CP

RCLEAR


The Logic Diagram and Truth Table indicate the functionalcharacteristics of the LS194A 4-Bit Bidirectional Shift Regis-ter. The LS194A is similar in operation to the Motorola LS195AUniversal Shift Register when used in serial or parallel dataregister transfers. Some of the common features of the twodevices are described below:

All data and mode control inputs are edge-triggered,responding only to the LOW to HIGH transition of the Clock(CP). The only timing restriction, therefore, is that the modecontrol and selected data inputs must be stable one set-uptime prior to the positive transition of the clock pulse.

The register is fully synchronous, with all operations takingplace in less than 15 ns (typical) making the device especiallyuseful for implementing very high speed CPUs, or the memorybuffer registers.

The four parallel data inputs (P0, P1, P2, P3) are D-typeinputs. When both S0 and S1 are HIGH, the data appearing onP0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and

Q3 outputs respectively following the next LOW to HIGHtransition of the clock.

The asynchronous Master Reset (MR), when LOW, over-rides all other input conditions and forces the Q outputs LOW.

Special logic features of the LS194A design which increasethe range of application are described below:

Two mode control inputs (S0, S1) determine the synchro-nous operation of the device. As shown in the Mode SelectionTable, data can be entered and shifted from left to right (shiftright, Q0 → Q1, etc.) or right to left (shift left, Q3 → Q2, etc.), orparallel data can be entered loading all four bits of the registersimultaneously. When both S0 and S1,are LOW, the existingdata is retained in a “do nothing” mode without restricting theHIGH to LOW clock transition.

D-type serial data inputs (DSR, DSL) are provided on boththe first and last stages to allow multistage shift right or shift leftdata transfers without interfering with parallel load operation.


OPERATING MODEINPUTS OUTPUTS

OPERATING MODEMR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3

Reset L X X X X X L L L L

Hold H I I X X X q0 q1 q2 q3

Shift Left H h I X I X q1 q2 q3 LH h I X h X q1 q2 q3 H

Shift Right H I h I X X L q0 q1 q2H I h h X X H q0 q1 q2

Parallel Load H h h X X Pn P0 P1 P2 P3L = LOW Voltage LevelH = HIGH Voltage LevelX = Don’t CareI = LOW voltage level one set-up time prior to the LOW to HIGH clock transitionh = HIGH voltage level one set-up time prior to the LOW to HIGH clock transitionpn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.

5-3


SN54/74LS194A




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA


S b l P

Limits

U i T C di iSymbol Parameter Min Typ Max Unit Test Conditions



VGuaranteed Input LOW Voltage for


Vp g

All Inputs


VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH Output HIGH Voltage74 2.7 3.5 V

CC , OH , IN IHor VIL per Truth Table


VIN = VIL or VIHVOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA

VIN = VIL or VIHper Truth Table








S b l P

Limits



V 5 0 VtPLHtPHL

Propagation Delay,Clock to Output

1417

2226 ns VCC = 5.0 V

CL = 15 pF

tPHLPropagation Delay,MR to Output 19 30 ns

CL = 15 pF

5-4


SN54/74LS194A


S b l P

Limits


tW Clock or MR Pulse Width 20 ns

V 5 0 V

ts Mode Control Setup Time 30 ns

V 5 0 Vts Data Setup Time 20 ns VCC = 5.0 V

th Hold time, Any Input 0 ns

trec Recovery Time 25 ns

DEFINITIONS OF TERMS

SETUP TIME(ts) —is defined as the minimum time requiredfor the correct logic level to be present at the logic input priorto the clock transition from LOW to HIGH in order to berecognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time followingthe clock transition from LOW to HIGH that the logic level mustbe maintained at the input in order to ensure continued

recognition. A negative HOLD TIME indicates that the correctlogic level may be released prior to the clock transition fromLOW to HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum timerequired between the end of the reset pulse and the clocktransition from LOW to HIGH in order to recognize and transferHIGH Data to the Q outputs.

AC WAVEFORMSThe shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays Clock PulseWidth and f max

Figure 3. Setup (t s) and Hold (t h) Time for Serial Data(DSR, DSL) and Parallel Data (P 0, P1, P2, P3)

Figure 2. Master Reset Pulse Width, Master Resetto Output Delay and Master Reset to Clock

Recovery Time

Figure 4. Setup (t s) and Hold (t h) Time for S Input

1.3 V

1.3 V

OTHER CONDITIONS: S1 = L, MR = H, S0 = H

OTHER CONDITIONS: S0, S1 = HOTHER CONDITIONS: PO = P1 = P2 = P3 = H

OTHER CONDITIONS: MR = HOTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLYOTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY

OTHER CONDITIONS: MR = H

S0

S1

DSR DSL

P0 P1 P2 P3

CLOCKOUTPUT*

(––– IS SHIFT LEFT)

CLOCK

CLOCK

CLOCK

OUTPUT

OUTPUT

S0 S1

ts(H)th(L) = 0 th(H) = 0

th(H) = 0ts(H)

th(L) = 0ts(L)

th = 0 th = 0

(STABLE TIME)

tPHL tPLH

1/fmax

tW

ts(L)

MR

tW trec

tPHL

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

ts ts

5-366


UNIVERSAL 4-BITSHIFT REGISTER

The SN54 /74LS195A is a high speed 4-Bit Shift Register offering typicalshift frequencies of 39 MHz. It is useful for a wide variety of register andcounting applications. It utilizes the Schottky diode clamped process toachieve high speeds and is fully compatible with all Motorola TTL products.

• Typical Shift Right Frequency of 39 MHz• Asynchronous Master Reset• J, K Inputs to First Stage• Fully Synchronous Serial or Parallel Data Transfers• Input Clamp Diodes Limit High Speed Termination Effects


NOTE:The Flatpak versionhas the same pinouts(Connection Diagram) asthe Dual In-Line Package.

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HIGH LOW

PE Parallel Enable (Active LOW) Input 0.5 U.L. 0.25 U.L.P0 – P3 Parallel Data Inputs 0.5 U.L. 0.25 U.L.J First Stage J (Active HIGH) Input 0.5 U.L. 0.25 U.L.K First Stage K (Active LOW) Input 0.5 U.L. 0.25 U.L.CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L.Q0 – Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.Q3 Complementary Last Stage Output (Note b) 10 U.L. 5 (2.5) U.L.

NOTES:a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)b. Temperature Ranges.

SN54/74LS195A

UNIVERSAL 4-BITSHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1



161

D SUFFIXSOIC

CASE 751B-03

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The Logic Diagram and Truth Table indicate the functionalcharacteristics of the LS195A 4-Bit Shift Register. The deviceis useful in a wide variety of shifting, counting and storageapplications. It performs serial, parallel, serial to parallel, orparallel to serial data transfers at very high speeds.

The LS195A has two primary modes of operation, shift right(Q0 º Q1) and parallel load which are controlled by the state ofthe Parallel Enable (PE) input. When the PE input is HIGH,serial data enters the first flip-flop Q0 via the J and K inputs andis shifted one bit in the direction Q0 º Q1 º Q2 º Q3 followingeach LOW to HIGH clock transition. The JK inputs provide theflexibility of the JK type input for special applications, and thesimple D type input for general applications by tying the two

pins together. When the PE input is LOW, the LS195A appearsas four common clocked D flip-flops. The data on the parallelinputs P0, P1, P2, P3 is transferred to the respective Q0, Q1,Q2, Q3 outputs following the LOW to HIGH clock transition.Shift left operations (Q3 º Q2) can be achieved by tying the QnOutputs to the Pn–1 inputs and holding the PE input LOW.

All serial and parallel data transfers are synchronous,occurring after each LOW to HIGH clock transition. Since theLS195A utilizes edge-triggering, there is no restriction on theactivity of the J, K, Pn and PE inputs for logic operation —except for the set-up and release time requirements.

A LOW on the asynchronous Master Reset (MR) input setsall Q outputs LOW, independent of any other input condition.


OPERATING MODESINPUTS OUTPUTS

OPERATING MODESMR PE J K Pn Q0 Q1 Q2 Q3 Q3

Asynchronous Reset L X X X X L L L L H

Shift, Set First Stage H h h h X H q0 q1 q2 q2Shift, Reset First H h I I X L q0 q1 q2 q2Shift, Toggle First Stage H h h I X q0 q0 q1 q2 q2Shift, Retain First Stage H h I h X q0 q0 q1 q2 q2

Parallel Load H I X X pn p0 p1 p2 p3 p3L = LOW voltage levelsH = HIGH voltage levelsX = Don’t CareI = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW toHIGH clock transition.

5-368


SN54/74LS195A




4.54.75

5.05.0

5.55.25

V


–550

2525

12570

°C



4.08.0

mA


Symbol Parameter

Limits




VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage

74 0.8V

Guaranteed Input LOW Voltage forAll Inputs


VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth TableVOH Output HIGH Voltage74 2.7 3.5 V

VCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth Table



VOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA









Symbol Parameter

Limits



VCC = 5.0 VCL = 15 pF

tPLHtPHL

Propagation Delay,Clock to Output

1417

2226 ns VCC = 5.0 V

CL = 15 pF

tPHLPropagation Delay,MR to Output 19 30 ns

CL = 15 pF


Symbol Parameter

Limits


tW CP Clock Pulse Width 16 ns

VCC = 5.0 V

tW MR Pulse Width 12 ns

VCC = 5.0 V

ts PE Setup Time 25 ns

VCC = 5.0 Vts Data Setup Time 15 ns VCC = 5.0 V

trec Recovery Time 25 ns

CC = 5.0 V

trel PE Release Time 10 ns

th Data Hold Time 0 ns

5-369


SN54/74LS195A

DEFINITIONS OF TERMS

SETUP TIME(ts) —is defined as the minimum time requiredfor the correct logic level to be present at the logic input priorto the clock transition from LOW to HIGH in order to berecognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time followingthe clock transition from LOW to HIGH that the logic level mustbe maintained at the input in order to ensure continued

recognition. A negative HOLD TIME indicates that the correctlogic level may be released prior to the clock transition fromLOW to HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum timerequired between the end of the reset pulse and the clocktransition from LOW to HIGH in order to recognize and transferHIGH Data to the Q outputs.

AC WAVEFORMSThe shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays andClock Pulse Width

Figure 3. Setup (t s) and Hold (t h) Time for Serial Data(J & K ) and Parallel Data (P 0, P1, P2, P3)

Figure 2. Master Reset Pulse Width, Master Resetto Output Delay and Master Reset to Clock

Recovery Time

Figure 4. Setup (t s) and Hold (t h) Time for PE Input

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Transcript of Lojik Devre Tasarimi Ders Notlari M UZAM