Logic Design Lab 3_100
14
1 Logic Design Lab 3: BCD Counter and 7-Segment Displayer Instructor: Kuan Jen Lin (林寬仁) E-Mail: [email protected] Web: http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htm Room: SF 727B
-
date post
30-Oct-2014 -
Category
Documents
-
view
14 -
download
2
Transcript of Logic Design Lab 3_100
Logic Design Lab 3: BCD Counter and 7-Segment DisplayerInstructor: Kuan Jen Lin () E-Mail: [email protected] Web: http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htm Room: SF 727B
1
BCD LED
2
Circuit Diagram
7-Segment LED controllerReset
BCD counter
3
BCD Ripple counter (Fig. 6-10)clock cycleQ1 Q1: 1->0Q2 Q8= 1, Q2 Q2: 1->0Q4 1110clock Q8->1 1001clock Q8->0
4
Synchronous BCD counter (Fig. 6-15)
5
BCD counter (7490) (Ripple)
0 9
VCC /GND
6
BCD counter (7490)1 clock 0 0 0 0 1
JKhigh clock ? Q2 clockQ1 (ripple) Q1, Q3(CP1Q0Fig. 6-10) Q31? counter1001->00001010)7
BCD Counter Waveform/Clock /CP0 Q0 /CP1 Q1 Q2 Q3 /CP0 Next Q0 1 2 3 4 5 6 7 8 9 10
8
Multi-digit BCD counterQ3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
/CP0
/CP0
9
IC 7447
ABCDa ~ f Lamp Test(LT)LEDLow High10
7 Segment LED
5V
()
11
BCD-To-7-Segment Decoder
12
13
Fig.3-3IC 7447
14
