Logic design Digital Integrated Circuits – EECS 312...
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Digital Integrated Circuits – EECS 312 http://ziyang.eecs.umich.edu/ ∼ dickrp/eecs312/ Teacher: Robert Dick Office: 2417-G EECS Email: [email protected] Phone: 734–763–3329 Cellphone: 847–530–1824 GSI: Myung-Chul Kim Email: [email protected] HW engineers SW engineers Year of announcement Power density (Watts/cm ) Bipolar CMOS IBM ES9000 IBM Z9 Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Midterm exam 1 I 0 1 2 3 4 5 50 55 60 65 70 75 80 85 90 95 100 Number of exams Score Histogram of scores for Midterm Exam 1 2 Robert Dick Digital Integrated Circuits Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Midterm exam 1 II Average: 80%. Common problems 1 Trouble interpreting layout: We can work on this a bit more in help sessions and class. 2 Maybe not enough time understanding some of the questions. Question: Was there a lot of time pressure? 3 Option: How about another short midterm after Thanksgiving break? Advantage: Less time pressure on final exam. Advantage: Less probability of a “bad day” messing up course score. Disadvantage: More stress and work. 3 Robert Dick Digital Integrated Circuits Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Homework 3 walkthrough Derive and explain. 4 Robert Dick Digital Integrated Circuits Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Review When are the advantages and disadvantages of fixed-voltage charging? When are the advantages and disadvantages of fixed-current charging? In what situation is each of the following models important? Ideal. C . RC . RLC . What are dI /dt effects? Under what circumstances do they cause the most trouble? Derive and explain. 5 Robert Dick Digital Integrated Circuits Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Rent’s rule T = ak p T : Number of terminals. a: Average number of terminals per block. k : Number of blocks within chip. p: Rent’s exponent, ≤ 1, generally around 0.7. 7 Robert Dick Digital Integrated Circuits Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Fringe vs. parallel plate capacitance Plot of C total for different gap ratios. 8 Robert Dick Digital Integrated Circuits Interconnect: Rent’s rule and coupling capacitance Elmore delay modeling Logic design Homework Inter-wire capacitance 9 Robert Dick Digital Integrated Circuits
Transcript of Logic design Digital Integrated Circuits – EECS 312...
Digital Integrated Circuits – EECS 312
http://ziyang.eecs.umich.edu/∼dickrp/eecs312/
Teacher: Robert DickOffice: 2417-G EECSEmail: [email protected]: 734–763–3329Cellphone: 847–530–1824
GSI: Myung-Chul KimEmail: [email protected]
HW engineers SW engineers
0
1
2
3
4
5
6
7
8
9
10
200 220 240 260 280 300
Curr
ent (m
A)
Time (seconds)
Typical Current Draw 1 sec Heartbeat
30 beats per sample
Sampling andRadio Transmission
9 - 15 mA
Heartbeat1 - 2 mA
Radio Receive for
Mesh Maintenance
2 - 6 mA
Low Power Sleep0.030 - 0.050 mA
Year of announcement
1950 1960 1970 1980 1990 2000 2010
Pow
er
de
nsity (
Watts/c
m2)
0
2
4
6
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10
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14
Bipolar
CMOS
VacuumIBM 360
IBM 370 IBM 3033
IBM ES9000
Fujitsu VP2000
IBM 3090S
NTT
Fujitsu M-780
IBM 3090
CDC Cyber 205IBM 4381
IBM 3081
Fujitsu M380
IBM RY5
IBM GP
IBM RY6
Apache
Pulsar
Merced
IBM RY7
IBM RY4
Pentium II(DSIP)
T-Rex
Squadrons
Pentium 4
Mckinley
Prescott
Jayhawk(dual)
IBM Z9
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Midterm exam 1 I
0
1
2
3
4
5
50 55 60 65 70 75 80 85 90 95 100
Nu
mb
er
of
exa
ms
Score
Histogram of scores for Midterm Exam 1
2 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Midterm exam 1 II
Average: 80%.
Common problems
1 Trouble interpreting layout: We can work on this a bit more inhelp sessions and class.
2 Maybe not enough time understanding some of the questions.Question: Was there a lot of time pressure?
3 Option: How about another short midterm after Thanksgivingbreak?
Advantage: Less time pressure on final exam.Advantage: Less probability of a “bad day” messing up coursescore.Disadvantage: More stress and work.
3 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Homework 3 walkthrough
Derive and explain.
4 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Review
When are the advantages and disadvantages of fixed-voltagecharging?
When are the advantages and disadvantages of fixed-currentcharging?
In what situation is each of the following models important?
Ideal.C .RC .RLC .
What are dI/dt effects? Under what circumstances do theycause the most trouble?
Derive and explain.
5 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Rent’s rule
T = akp
T : Number of terminals.
a: Average number of terminals per block.
k: Number of blocks within chip.
p: Rent’s exponent, ≤ 1, generally around 0.7.
7 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Fringe vs. parallel plate capacitance
Plot of Ctotal for different gap ratios.
8 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Inter-wire capacitance
9 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Impact of inter-wire capacitance
10 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Wire resistance
R = ρLHW
.
Consider fixed-height, fixed-ρ square material, i.e., L ∝ W .
R = k1/W
W, where k is a constant.
11 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Interconnect resistance
Material ρ (Ω m) ×10−8
Silver 1.6Copper 1.7Gold 2.2
Aluminum 2.7Tungsten 5.5
12 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Reducing resistance
Higher interconnect aspect ratios
Material selection
CopperSilicidesCarbon nanotubes
Structural changes
More interconnect layers3-D integration
13 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Silicides
14 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Resistances
Material Sheet resistance (Ω/)
n- or p-well diffusion 1,000–1,500n+ or p+ diffusion 50–150
silicided n+ or p+ diffusion 3–5doped polysilicon 150–200
doped silicides polysilicon 4–5Aluminum 0.05–0.1
15 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Multi-layer interconnect
16 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Side view of interconnect
17 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Interconnect summary
It is important to know which interconnect model to use in whichsituation.
Ideal.C .RC .RLC .
dI/dt effects are particularly important in power deliverynetworks.
Capacitive coupling complicates design.
Cu and silicides can be used to reduce resistance.
18 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Delay modeling
Single-node lumped model inaccurate.
Full detailed accurate model intractable for manual analysis andslow for automated analysis.
Elmore delay model permits rapid analysis with often adequateaccuracy.
20 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Elmore delay
Problem definition
Goal: Determine τ for RC path.
Note: Source node is implicit.
Ci : Self-capacitance of node i .
Rii : Path resistance from source to node i .
Rik : Shared resistance from source to both nodes i and k.
τi =
N∑
k=1
CkRik
Derive and explain.
21 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Special case: RC chains
Consider π network.
τn =∑n
i=1 Ci
∑ij=1 Rj .
Use homogeneous discretization.
∀Ni=2Ci = C1
τ =
N∑
k=1
CRnk
=L
Nc
L
NrN(N + 1)
2
= rcL2 N + 1
2N
What if N → ∞? τ → rcL2/2.
22 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Underlying continuous physical model
crδV
δt=
δ2V
δx2
23 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Power delivery network considerations
IR drop.
dI/dt effects.
Location of parasitic inductance.
Methods to correct power delivery network non-idealities.
24 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Response to step function over time and space
25 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Simplifying assumptions
Ignore wire RC delay when wire delay does not much exceed thatof the driving gate, i.e.,
Lcrit
√
tp,gate
0.38rc
Ignore wire RC when rise time greater than RC delay.
Ignore for high-resistance wires: R > 0.2C .
Ignore when time of flight is large compared to rise or fall time:trise,fall < 2.5tflight .
26 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Elmore delay summary
Pick simplest model for intended purpose: C , RC , or RLC .
Capacitive coupling complicates timing analysis.
Transition direction impacts C magnitude in simplifiedground-cap model.
Learn Elmore delay. It is a good first-order approximation ofnetwork delay.
27 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Static CMOS design styles and components
Logic gates
Switch-based design
MUX
DEMUX
Encoder
Decoder
29 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Transistor sizing review
Goal: equal τ for worst-case pull-up and pull-down paths.
Observations
Adding duplicate parallel path halves resistance.Adding duplicate series path doubles resistance.Doubling width halves resistance.
Consider logic gate examples.
30 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
CMOS transmission gate (TG)
B
C
C
A
32 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Other TG diagram
33 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Multiplexer (MUX) definitions
Also called selectors
2n inputs
n control lines
One output
34 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX functional table
C Z
0 I01 I1
35 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX truth table
I1 I0 C Z
0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1
36 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX using logic gates
A B
I0
I1
I2
I3
Z
37 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX using TGs
I3
I0
I2
I1
AA BB
ZZ
38 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX
2:1C
C
C
C
A
B
D
A
B
C C
D
39 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Hierarchical MUX implementation
4 :1
mux
4 :1
mux
8 :1
mux
2 :1
mux
0
1
2
3
0
1
2
3
S
S1
S0
S1
S0
Z
ACB
I0
I1
I2
I3
I4
I 5
I6
I7
0
1
40 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Alternative hierarchical MUX implementation
00
11SS
00
11SS
00
11 SS
00
11SS
00
11
S 1
22
33S 0
AA BB
II00
II11
II22
II33
II44
II55
II66
II77
CC
CC
CC
41 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX examples
2:1
m ux
I0
I1
A
Z
Z = AI0 + AI1
42 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX examples
I0
A
I1
I2
I3
B
Z4:1
m ux
Z = AB I0 + ABI1 + AB I2 + ABI3
43 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX examples
I0
A
I1
I2
I3
B
Z8:1
m ux
C
I4
I5
I6
I7
Z = AB C I0 + ABCI1 + ABC I2 + ABCI3+
AB C I4 + ABCI5 + ABC I6 + ABCI7
44 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX properties
A 2n : 1 MUX can implement any function of n variables
A 2n−1 : 1 can also be used
Use remaining variable as an input to the MUX
45 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX example
F (A,B,C ) =∑
(0, 2, 6, 7)
= AB C + ABC + ABC + ABC
46 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Truth table
A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
47 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Lookup table implementation
8:1
MUX
1
0
1
0
0
0
1
11
0
1
2
3
4
5
6
77 S2 S1 S0
AA BB CC
FF
48 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
MUX example
F (A,B,C ) =∑
(0, 2, 6, 7)
= AB C + ABC + ABC + ABC
Therefore,
AB → F = C
AB → F = C
AB → F = 0
AB → F = 1
49 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Truth table
A B C F0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
F=C
50 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Lookup table implementation
S1 S0
AA BB
4:1
MUX
0
1
2
33
00
11
FF
51 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Logic design summary
Logic gate, transmission gate, and pass transistor design eachhave applications.
MUX-based design provides a good starting point fortransmission gate and pass transistor based design.
52 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Examples
Instead of flying through a bunch of slides, let’s try examples.
f (a) = a.
f (a) = a
f (a, b) = ab
f (a, b) = ab (Check Figure 6-33 in J. Rabaey, A. Chandrakasan,and B. Nikolic. Digital Integrated Circuits: A Design Perspective.Prentice-Hall, second edition, 2003!)
f (a, b, c) = ab + bc (try both ways).
Derive and explain.
53 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Switch-based design
Upcoming topics
Alternative logic design styles.
Latches and flip-flops.
Memories.
54 Robert Dick Digital Integrated Circuits
Interconnect: Rent’s rule and coupling capacitanceElmore delay modeling
Logic designHomework
Homework assignment
9 November, Tuesday: Read Section 6.3 in J. Rabaey,A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A
Design Perspective. Prentice-Hall, second edition, 2003.
11 November, Thursday: Homework 3.
56 Robert Dick Digital Integrated Circuits
Special topic: Atomic layer deposition
Katherine Dropiewski, Matt Jansen, and Olga Rouditchenko
