Logic Circuit Families (2) - Docceptor.net
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Transcript of Logic Circuit Families (2) - Docceptor.net
Contents
• Pseudo nMOS
• Cascode Voltage Switch Logic
• Dynamic Circuit and Domino Logic
• Pass-Transistor Circuits
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Dynamic Circuit and Domino Logic Replacing always-pull-up of pseudo nMOS with “clocked” pull-up
Combinational Circuitsvs. Sequential Circuits
• Combinational circuit: output is a function of the current inputs.
• Sequential circuit: output depends on previous as well as currentinputs; such circuits are said to have state.
• Sequential logic is essential for today electronic system(Have you heard of pipeline or finite state machine?)
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Combinational
Logic
Combinational
LogicMemory
Combinational
LogicMemory
Combinational
LogicMemory… …
“Synchronous” Sequential Circuit
• The state of device changes only at discrete times dominated by a “clock” signal.
Besides the main CLK signal, many other dynamically changing “control” signals can be generated
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Combinational
LogicMemory
Combinational
LogicMemory
Combinational
LogicMemory… …
CLK
Dynamic InverterUtilizing Clocked Pull-up
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Static CMOS Pseudo NMOS Dynamic
A Y
A
Y
A
Y
Φ
Φ
Y
Precharge Evaluation Precharge
Operated in two phases:1) Precharge and 2) Evaluation
Dynamic Logic Gate
• Precharge (Φ=0) Clocked pMOS is ON, initializing Y high.
• Evaluation (Φ=1)• Clocked pMOS is turned off
• Y may remain high or e discharged low according to pulldown network controlled by inputs.
• Why is it faster than CMOS gate? Area?
• No static power as pseudo-nMOS.
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Φ
Y
Precharge Evaluation Precharge
A
Y
Φ
NAND2 NOR2 XOR2
Various Dynamic Logic Gates
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A
Y
B
Φ Φ
A B
Φ
A
B
/A
/B
Can You Find Potential Problems?
1) During precharge, there might be contention.
2) If A falls during evaluation, Y cannot be raised.(Monotonically falling output, monotonicity problem)
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Φ
Y
Precharge Evaluation Precharge
A
What would Y be like?A
Y
Φ
How Can You Resolve Contention Problem?
• State your goal verbally and specifically.
“When Φ = 0, the pull-down network should be disabled.”
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A =1
Y
Φ = 10
Supposed to rise
Condition Operation: MOSFET gate node : MOSFET drain current
Φ = 10
A =1
Footed Dynamic Inverter
Footed Dynamic Gates
• Width needs to be increased to achieve equal speed
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NAND2 NOR2 General logic
Unfooted
Footed
A
Y
B
ΦΦ
A B
YPull-
down
Network
ΦY
Pull-
down
Network
ΦYΦ
A BYA
B
Y
Φ
How Can You Handle Monotonicity Problem?
• What is the cause of the problem? A falls during the evaluation.Can’t we force A only to rise or kept low during evaluation?Can’t we make A monotonically rising during evaluation?
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Φ
Y
Precharge Evaluation Precharge
A
A
Y
Φ
How Can We Achieve an Input “Monotonically Rising” During Evaluation
• Dynamic gate output is monotonically falling during evaluation
Then, we can easily achieve a signal monotonically rising during evaluation by
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A
Φ
B
W
C
Y
CMOS static inverter
X
• Domino logic = Dynamic gate + static inverter
Domino Logic Gate
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A
Φ
B
W
C
YX
Domino OR
Operational Waveform
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A
Φ
B
W
C
YX
Domino OR
• Monotonicity problem is solved
8:1 MUX Using Domino Logic
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Potential Problem for A = 0
3) When A = 0, Y is floating high.“When Y is high, Y should be driven to VDD.”Who can drive Y to VDD?
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Φ
Y
Precharge Evaluation Precharge
AΦ
A =1
Y
Keeper Implementation for Noise Robustness
• Note that keeper pMOS should be sufficiently weak.
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Pull-
down
Network
Summary
• Clocked pull-up + pull-down network for logic implementation
• Contention during precharge can be solved through footed circuit
• Monotonicity problem is resolved by domino logic
• Keeper can be utilized to prevent output floating of the dynamic gate, but the strength should be carefully determined.
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