Advanced Digital Circuit Design - Synchronous Sequential Logic
Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M....
-
Upload
laurel-simon -
Category
Documents
-
view
278 -
download
0
Transcript of Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M....
![Page 1: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/1.jpg)
Logic and Sequential Circuit Design (EC – 201)
![Page 2: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/2.jpg)
Textbook
Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )
![Page 3: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/3.jpg)
Topics• Boolean Algebra and Logic Gates: Binary Logic and
Gates, Boolean Algebra and Functions, Canonical and Standard Forms, Logic Operations, Digital Logic Gates, and IC Digital Families.
• Simplification of Boolean Functions: K-Map Method and Simplification using Different Variables Map, Simplification of Product of Sums, Implementation with NAND and NOR Gates, Don’t Care Conditions, The Tabulation Method, Determination of Prime-Implicants, and Selection of Prime-Implicants.
![Page 4: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/4.jpg)
Continue…• Combinational Logic Design: Design Procedure,
Adders, Subtractors, Code Conversion, Analysis Procedure, Multilevel NAND Circuits, Multilevel NOR Circuits, Exclusive-OR, and Equivalence Functions
• Combinational Logic with MSI and LSI: Decimal Adder, Magnitude Comparator, Decoders, Encoders, Multiplexers, Demultiplexers, Binary Adders, Binary Subtraction, Binary Adder-Subtractors, Binary Multipliers and HDL Representation – VHDL/Verilog
![Page 5: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/5.jpg)
Continue…
• Sequential Logic/Circuits: Latches, Flip-Flops, Triggering of Flip-Flops, Clocked Sequential Circuits and their Analysis, State Reduction and Assignment, Flip-Flop Excitation Tables, Design Procedure, Designing with D & JK Flip-Flops, HDL/Verilog Representation for a Sequential Circuits – VHDL/Verilog
![Page 6: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/6.jpg)
Boolean Algebra &
Logic Gates
![Page 7: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/7.jpg)
Common Postulates (Boolean Algebra)• Closure
N={1,2,3,4,5,…..}It is closed w.r.t +
i.e. a+b=cas a,b,cΣN
• Associative Law(x*y)*z = x*(y*z)for all x,y,z,ΣS
• Commutative Lawx*y = y*x for all x,yΣSx+y = y+x
x+y = y+xx.Y = y.x
![Page 8: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/8.jpg)
Common Postulates (Boolean Algebra)• Identity Element
e*x = x*e = x x Σ Se+x = x+e = x0+x = x+0 = x1*x = x*1 = x
• Inversex*y = e a*1/a = 1x+y = ea+(-a) = 0
• Distributed Lawx*(y.z) = (x*y) . (x*z)x.(y+z) = (x.y) + (x.z)x+(y.z) = (x+y) . (x+z)
x+0 = 0+x = xx.1 = 1.x = x
x+x’ = 1x.x’ = 0
![Page 9: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/9.jpg)
Boolean Algebra and Logic Gatesx y x.y x y x+y x x’
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
x y z Y+z x.(y+z) x.y x.z (x.y)+x.z
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
x.(y+z) = (x.y)+(x.z)
![Page 10: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/10.jpg)
Postulates and Theorems of Boolean Algebra
Postulate 2 (a) x+0 = x (b) x.1 = x
Postulate 5 (a) x+x’ = 1 (b) x.x’ = 0
Theorem 1 (a) x+x = x (b) x.x = x
Theorem 2 (a) x+1 = 1 (b) x.0 = 0
Theorem3, involution (x’)’ = x
Postulate3, commutative (a) x+y = y+x (b) xy = yx
Theorem4, associative (a) x+(y+z)=(x+y)+z (b) x(yz) = (xy)z
Postulate4, distributive (a) x(y+z)=xy+xz (b) x+yz = (x+y)(x+z)
Theorem5, DeMorgan (a) (x+y)’ = x’y’ (b) (xy)’ = x’+y’
Theorem6, absorption (a) x+xy = x (b) x(x+y)=x
![Page 11: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/11.jpg)
Theorems1a. x+x = x
x+x = (x+x).1 = (x+x)(x+x’) = x+xx’ =x+0 =x
1b. x.x = x (Remember Duality of 1a)x.x = xx+0 = xx+xx’ = x(x+x’) = x.1 =x
![Page 12: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/12.jpg)
Theorems2a. x+1 = 1
x+1 =1.(x+1) = (x+x’)(x+1) = (x+x’) = x+x’ = 1
2b. X.0 = 0 (Remember Duality of of 2a)
![Page 13: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/13.jpg)
3. (x’)’ = xComplement of x = x’Complement of x’ = (x’)’ = x
6a x+xy = xx+xy = x.1+xy = x(1+y) = x.1 =x
6b. x(x+y) = x (Remember Duality of 6a)
Can also be proved using truth table method
![Page 14: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/14.jpg)
x y xy x+xy
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1
x y x+y (x+y)’ x’ y’ x’y’
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
x=x+xy
(x+y)’ = x’y’ DeMorgan’s Theorem (xy)’ = x’ +y’ DeMorgan’s Theorem
![Page 15: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/15.jpg)
Operator Precedence1.( )2.NOT3.AND4.OR
![Page 16: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/16.jpg)
x y
xy’ xy x’y
x y
x y
z
x+(y+z)
x y
z
xy+xz
VENN DIAGRAM FOR TWO VARIABLES VENN DIAGRAM ILLUSTRATION X=XY+X
VENN DIAGRAM ILLUSTRATION OF THE DISTRIBUTIVE LAW
x’y’
x y
![Page 17: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/17.jpg)
TRUTH TABLE FOR F1=xyz’, F2=x+y’z, F3=x’y’z+x’yz+xy’ and F4=xy’+x’z
x y z F1 F2 F3 F4
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 0 0 0 0
0 1 1 0 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 0
![Page 18: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/18.jpg)
xy
z
F1
z
y
F2x
(a) F1 = xyz’(b) F2 = x+y’z
(c) F3 = x’y’z+x’yz+xy’
F3z
y
x
![Page 19: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/19.jpg)
(c) F4 = xy’+x’z
F4
z
y
x
Implementation of Boolean Function with GATES
![Page 20: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/20.jpg)
Algebraic Manipulations for Minimization of Boolean Functions(Literal minimization)
1. x+x’y = (x+x’)(x+y) = 1.(x+y)=x+y
2. x(x’+y) = xx’+xy = 0+xy=xy
3. x’y’z+x’yz+xy’= x’z(y’+y)+xy’= x’z+xy’
4. xy+x’z+yz (Consensus Theorem)=xy+x’z+yz(x+x’)=xy+x’z+xyz+x’yz=xy(1+z)+x’z(1+y)=xy+x’z
5. (x+y)(x’+z)(y+z)=(x+y)(x’+z)by duality from function 4
![Page 21: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/21.jpg)
Complement of a Function
(A+B+C)’ = (A+X)’= A’X’= A’.(B+C)’= A’.(B’C’)= A’B’C’
(A+B+C+D+…..Z)’ = A’B’C’D’…..Z’ (ABCD….Z)’ = A’+B’+C’+D’+….+Z’Example using De Morgan’s Theorem (Method-1)F1 = x’yz’+x’y’zF1’ = (x’yz’+x’y’z)’ = (x+y’+z)(x+y+z’)F2 = x(y’z’+yz)F2’= [x(y’z’+yz)]’ = x’+(y+z)(y’+z’)
![Page 22: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/22.jpg)
Example using dual and complement of each literal (Method-2)
F1 = x’yz’ + x’y’zDual of F1 = (x’+y+z’)(x’+y’+z)Complement F1’ = (x+y’+z)(x+y+z’)
F2 = x(y’z’+yz)Dual of F2=x+[(y’+z’)(y+z]Complement =F2’= x’+ (y+z)(y’+z’)
![Page 23: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/23.jpg)
Minterm or a Standard Productn variables forming an AND term provide 2n possible combinations, called minterms or standard products (denoted as m1, m2 etc.).Variable primed if a bit is 0Variable unprimed if a bit is 1Maxterm or a Standard Sumn variables forming an OR term provide 2n possible combinations, called maxterms or standard sums (denoted as M1,M2 etc.).Variable primed if a bit is 1Variable unprimed if a bit is 0
![Page 24: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/24.jpg)
MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES
MINTERMS MAXTERMS
x y z Term Designation Term Designation
0 0 0 x’y’z’ m0 x+y+z M0
0 0 1 x’y’z m1 x+y+z’ M1
0 1 0 x’yz’ m2 x+y’+z M2
0 1 1 x’yz m3 x+y’+z’ M3
1 0 0 xy’z’ m4 x’+y+z M4
1 0 1 xy’z m5 x’+y+z’ M5
1 1 0 xyz’ m6 x’+y’+z M6
1 1 1 xyz m7 x’+y’+z’ M7
![Page 25: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/25.jpg)
FUNCTION OF THREE VARIABLES
x y z Function f1 Function f2
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
f1 = x’y’z+xy’z’+xyz =m1 + m4 + m7f2 = x’yz+xy’z+xyz’+xyz = m3 + m5 + m6 + m7
![Page 26: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/26.jpg)
MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES
f1 = x’y’z+xy’z’+xyzf1’ = x’y’z’+x’yz’+x’yz+xy’z+xyz’f1 =(x+y+z)(x+y’+z)(x+y’+z’)(x’+y+z’) (x’+y’+z)
= M0.M2.M3.M5.M6= M0M2M3M5M6
f2 = x’yz+xy’z+xyz’+xyzf2’ = x’y’z’+x’y’z+x’yz’+xy’z’f2 = (x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
= M0 M1 M2 M4Canonical FormBoolean functions expressed as a sum of minterms or product of maxterms are said to be in canonical form.M3+m5+m6+m7 or M0 M1 M2 M4
![Page 27: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/27.jpg)
Sum of Minterms (Sum of Products)Example: F = A+B’CF = A(B+B’)+B’C(A+A’)
= AB+AB’+AB’C+A’B’C= AB(C+C’)+AB’(C+C’)+AB’C+A’B’C= ABC+ABC’+AB’C+AB’C’+AB’C+A’B’C= A’B’C+AB’C’+AB’C+ABC’+ABC= m1+m4+m5+m6+m7
F(A,B,C)=(1,4,5,6,7)
ORing of term AND terms of variables A,B &CThey are minterms of the function
![Page 28: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/28.jpg)
Product of Maxterms (Product of sums)Example: F = xy+x’zF = xy+x’zF = (xy+x’)(xy+z) distr.law (x+yz)=(x+y)(x+z)
= (x+x’)(y+x’)(x+z)(y+z)= (x’+y)(x+z)(y+z)= (x’+y+zz’)(x+z+yy’)(y+z+xx’)= (x’+y+z)(x’+y+z’)(x+z+y)(x+z+y’)(y+z+x)(y+z+x’)= (x+y+z)(x+y’+z)(x’+y+z)(x’+y+z’)= M0 M2 M4 M5F(x,y,z) = (0,2,4,5)
ANDing of terms Maxterms of the function (4 OR terms of variables x,y&z)
![Page 29: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/29.jpg)
Conversion between Canonical FormsF(A,B,C) = (1,4,5,6,7)
sum of mintermsF’(A,B,C) = (0,2,3)
= m0+m2+m3F(A,B,C) = (m0+m2+m3)’
= m0’.m2’.m3’ = M0 M2 M3 = (0,2,3) Product of maxterms
SimilarlyF(x,y,z) = (0,2,4,5)F(x,y,z) = (1,3,6,7)
![Page 30: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/30.jpg)
Standard FormsSum of Products (OR operations)F1 = y’+xy+x’yz’ (AND term/product term)
Product of Sums (AND operations)F2=x(y’+z)(x’+y+z’+w)
(OR term/sum term)Non-standard formF3=(AB+CD)(A’B’+C’D’)
Standard form of F3F3=ABC’D’ + A’B’CD
![Page 31: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/31.jpg)
TRUTH TABLE FOR THE 16 FUNCTIONS OF TWO BINARY VARIABLES
x y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Operator symbols
+ , ,
F0 = 0 F1 = xy F2 = xy’ F3 = x
F4 = x’y F5 = y F6 = xy’ +x’y F7= x +y
F8 = (x+y)’ F9 = xy +x’y’ F10 = y’ F11 = x +y’
F12 = x’ F13 = x’ + y F14 = (xy)’ F15 = 1
![Page 32: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/32.jpg)
BOOLEAN EXPRESSIONS FOR THE 16 FUNCTIONS OF TWO VARIABLE
BOOLEAN OPERATOR NAME COMMENTS FUNCTIONS SYMBOL
F0 =0 NULL BINARY CONSTANT 0
F1=xy x.y AND x and y
F2=xy’ x/y inhibition x but not yF3=x transfer x F4=x’y y/x inhibition y but not xF5=y transfer yF6=xy’+x’y x y exclusive-OR x or y but not bothF7=x+y x+y OR x or yF8=(x+y)’ x y NOR not ORF9=xy+x’y’ x y *equivalence x equals y F10=y’ y’ complement not yF11=x+y’ x y implication if y then xF12=x’ x’ complement not xF13=x’+y x y implication if x then yF14=(xy)’ x y NAND not ANDF15=1 IDENTITY BINARY CONSTANT 1
![Page 33: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/33.jpg)
• *Equivalence is also known as equality, coincidence, and exclusive NOR
• 16 logic operations are obtained from two variables x &y• Standard gates used in digital design are: complement, transfer,
AND, OR , NAND, NOR, XOR & XNOR (equivalence).
![Page 34: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/34.jpg)
H and L LEVEL IN IC LOGIC FAMILIES
IC Family Voltage
Type Supply (V)
High-level voltage
(V)
Range Typical
Low-level voltage (V)
TTL Vcc=5
ECL VEE=-5.2
CMOS VDD=3--10
Positive Logic:
Negative Logic
2.4-5 3.5
-0.95- -0.7 -0.8
VDD VDD
Logic-1
Logic-0
0-0.4 0.2
-1.9-- -1.6 -1.8
0-0.5 0
Logic-0
Logic-1
Range Typical
![Page 35: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/35.jpg)
TYPICAL CHARACTERISTICS OF IC LOGIC FAMILIES
IC Logic
Family
Fan out Power
Dissipation (mw)
Propagation delay (ns)
Noise Margin (v)
Standard TTL
Shottky TTL
Low power
Shottky TTL
ECL
CMOS
10
10
20
25
50
10
22
2
25
0.1
10
3
10
2
25
0.4
0.4
0.4
0.2
3
TTL basic circuit : NAND gateECL basic circuit: NOR gateCMOS basic circuit: Inverter to construct NAND/NOR
![Page 36: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/36.jpg)
DIGITAL LOGIC GATESNAME GRAPHIC
SYMBOL
ALGEBRIC
FUNCTION
TRUTH
TABLE
AND F=XY X Y F
0 0 0
0 1 0
1 0 0
1 1 1
OR F=X+Y X Y F
0 0 0
0 1 1
1 0 1
1 1 1
XY
F
YX
F
![Page 37: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/37.jpg)
NAME GRAPHIC
SYMBOL
ALGEBRIC
FUNCTION
TRUTH
TABLE
Inverter
F=X’
X F
0 1
1 0
Buffer
F=X
X F
0 0
1 1
NAND F=(XY)’
X Y F
0 0 1
0 1 1
1 0 1
1 1 0
X F
X F
X FY
![Page 38: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/38.jpg)
NAME GRAPHIC
SYMBOL
ALGEBRIC
FUNCTION
TRUTH
TABLE
NOR F=(X+Y)’
X Y F
0 0 1
0 1 0
1 0 0
1 1 0
Exclusive-OR
(XOR)
F=XY’+X’Y
= X Y
X Y F
0 0 0
0 1 1
1 0 1
1 1 0
Exclusive-NOR
or
EquivalenceF=XY+X’Y’
=X Y
X Y F
0 0 1
0 1 0
1 0 0
1 1 1
FYX
X FY
FXY
![Page 39: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/39.jpg)
Y (X Y) Z=(X+Y) Z’
Y
x(X+Y)’
=XZ’+YZ’
[Z+(X+Y)’]’
(Y+Z)’
(X ( Y Z)=X’(Y+ Z)
=X’Y+X’Z
[X+(Y+Z)’]’
Z
X
Z
Demonstrating the nonassociativity of the NOR operator
(X Y) Z X (Y Z)
![Page 40: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/40.jpg)
XYZ
(X+Y+Z)’XYZ
(XYZ)’
(a) There input NOR gate (b) There input NAND gate
ABC
D
E
F=[(ABC)’. (DE)’]’=ABC+DE
(c) Cascaded NAND gates
Multiple-input AND cascaded NOR and NAND gates
![Page 41: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/41.jpg)
XY
Z F=X Y Z
(a) Using two input gates
XYZ
(b) Three input gates
(b) Three input exclusive OR gates
TRUTH TABLE
X Y Z F 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0
XOR
XNOROdd function
Even function
F=X Y Z
![Page 42: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/42.jpg)
IC DIGITAL LOGIC FAMILIESTTL Transistor- Transistor Logic
• Very popular logic family.• It has a extensive list of digital functions.• It has a large number of MSI and SSI devices, also has LSI devices.
ECL Emitter Coupled Logic• Used in systems requiring high speed operations.• It has a large number of MSI and SSI devices, also LSI devices.
MOS Metal-Oxide Semiconductor• Used in circuit requiring high component density• It has a large number of MSI and SSI devices, also LSI devices (mostly)
CMOS Complementary MOS• Used in systems requiring low power consumption.• It has a large number of MSI and SSI devices, also has LSI devices.
I2L Integrated - Injection Logic• Used in circuit requiring high component density.• Mostly used for LSI functions
![Page 43: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/43.jpg)
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC
GND1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC
GND
Some Typical IC Gates
7400 Quadruple 2-input NAND gates
7404 Hex Inverters
TTL gates
![Page 44: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/44.jpg)
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 2
VEE 2 (-5.2V)VCC 1
10107 Triple Exclusive – OR/ NOR gates
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 2
VCC 1VEE (-5.2V)
10102 Quadruple 2-Input NOR gate
Some Typical IC Gates
![Page 45: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/45.jpg)
1 2 3 4 5 6
NC
7
Vss (GND)
NC
8910111213
VDD
14
(3-15 V)
C MOS
GATES
4002 dual 4 input NOR gates
![Page 46: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/46.jpg)
NC
16
1
VDD
3 4 5 6 7 8 Vss
(GND)
91011121415
2
(3-15 V)
4050 Hex buffer
CMOS
GATES
NC
13
![Page 47: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/47.jpg)
0
1 H
L
0
1
H
L
LOGIC
VALUE
SIGNAL
VALUE
LOGIC
VALUE
SIGNAL
VALUE
Negative LogicPositive Logic
Signal amplitude assignment and type of logic
![Page 48: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/48.jpg)
X y z
L L H
L H H
H L H
H H L
TTL7400GATE
x
y
z
Gate block diagramGate block diagramTruth table in terms of
H and L
X y z
0 0 1
0 1 1
1 0 1
1 1 0
Truth table for positive logic
H=1, L=0
x
yz
Graphic symbol for positive logic NAND gate
![Page 49: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/49.jpg)
X y z
1 1 0
1 0 1
0 1 1
0 0 1
Truth table for negative logic
L=1 H=0
xz
y
Graphic symbol for negative logic NOR gate
+ive logic NAND or -ive logic NOR
+ive logic NOR or -ive logic NAND
Same gate can function
DEMONSTRATION OF POSITIVE AND NEGATIVE LOGIC
![Page 50: Logic and Sequential Circuit Design (EC – 201). Textbook Digital Logic and Computer Design by M. Morris Mano (Jan 2000 )](https://reader033.fdocuments.net/reader033/viewer/2022061607/56649ef05503460f94c002ee/html5/thumbnails/50.jpg)
Fan-outSpecifies the number of standard loads (the amount of current needed by an input of another gate in the same IC family) that the output of a gate can drive without impairing its normal operation. it is expressed by a number.Power dissipationIt is the supplied power required to operate the gate. It is expressed in mw.Propagation delay It is the average transition delay time for a signal to propagate from input to output when the binary signals change in value. It is expressed in ns.Noise marginIt is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts (v).
Characteristics of IC logic families(parameters)