LM555/NE555/SA555 Single Timer - Jameco Electronics · LM555/NE555/SA555 4 Application Information...

©2002 Fairchild Semiconductor Corporation

www.fairchildsemi.comwww.fairchildsemi.comwww.fairchildsemi.comwww.fairchildsemi.com

Rev. 1.0.3

FeaturesFeaturesFeaturesFeatures• High Current Drive Capability (200mA)• Adjustable Duty Cycle• Temperature Stability of 0.005%/°C• Timing From µSec to Hours• Turn off Time Less Than 2µSec

ApplicationsApplicationsApplicationsApplications• Precision Timing• Pulse Generation• Time Delay Generation• Sequential Timing

DescriptionDescriptionDescriptionDescriptionThe LM555/NE555/SA555 is a highly stable controllercapable of producing accurate timing pulses. With amonostable operation, the time delay is controlled by oneexternal resistor and one capacitor. With an astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.

8-DIP8-DIP8-DIP8-DIP

8-SOP8-SOP8-SOP8-SOP

1

1

Internal Block DiagramInternal Block DiagramInternal Block DiagramInternal Block Diagram

F/FF/FF/FF/FOutPutOutPutOutPutOutPutStageStageStageStage

1111

7777

5555

2222

3333

4444

6666

8888RRRR RRRR RRRR

Comp.Comp.Comp.Comp.

Comp.Comp.Comp.Comp.

Discharging Tr.Discharging Tr.Discharging Tr.Discharging Tr.

VrefVrefVrefVref

VccVccVccVcc

DischargeDischargeDischargeDischarge

ThresholdThresholdThresholdThreshold

ControlControlControlControlVoltageVoltageVoltageVoltage

GNDGNDGNDGND

TriggerTriggerTriggerTrigger

OutputOutputOutputOutput

ResetResetResetReset

LM555/NE555/SA555Single Timer

LM555/NE555/SA555

2222

Absolute Maximum Ratings (TAbsolute Maximum Ratings (TAbsolute Maximum Ratings (TAbsolute Maximum Ratings (TAAAA = 25 = 25 = 25 = 25°°°°C)C)C)C)ParameterParameterParameterParameter SymbolSymbolSymbolSymbol ValueValueValueValue UnitUnitUnitUnitSupply Voltage VCC 16 VLead Temperature (Soldering 10sec) TLEAD 300 °CPower Dissipation PD 600 mWOperating Temperature Range LM555/NE555SA555

TOPR 0 ~ +70-40 ~ +85

°C

Storage Temperature Range TSTG -65 ~ +150 °C

LM555/NE555/SA555

3333

Electrical CharacteristicsElectrical CharacteristicsElectrical CharacteristicsElectrical Characteristics(TA = 25°C, VCC = 5 ~ 15V, unless otherwise specified)

Notes:Notes:Notes:Notes:1. When the output is high, the supply current is typically 1mA less than at VCC = 5V.2. Tested at VCC = 5.0V and VCC = 15V.3. This will determine the maximum value of RA + RB for 15V operation, the max. total R = 20MΩ, and for 5V operation, the max.

total R = 6.7MΩ.4. These parameters, although guaranteed, are not 100% tested in production.

ParameterParameterParameterParameter SymbolSymbolSymbolSymbol ConditionsConditionsConditionsConditions Min.Min.Min.Min. Typ.Typ.Typ.Typ. Max.Max.Max.Max. UnitUnitUnitUnitSupply Voltage VCC - 4.5 - 16 V

Supply Current (Low Stable) (Note1) ICCVCC = 5V, RL = ∞ - 3 6 mAVCC = 15V, RL = ∞ - 7.5 15 mA

Timing Error (Monostable)Initial Accuracy (Note2)Drift with Temperature (Note4)Drift with Supply Voltage (Note4)

ACCUR∆t/∆T

∆t/∆VCC

RA = 1kΩ to100kΩC = 0.1µF

- 1.0500.1

3.0

0.5

%ppm/°C

%/V

Timing Error (Astable) Intial Accuracy (Note2)Drift with Temperature (Note4)Drift with Supply Voltage (Note4)

ACCUR∆t/∆T

∆t/∆VCC

RA = 1kΩ to 100kΩC = 0.1µF

- 2.251500.3

- %ppm/°C

%/V

Control Voltage VCVCC = 15V 9.0 10.0 11.0 VVCC = 5V 2.6 3.33 4.0 V

Threshold Voltage VTHVCC = 15V - 10.0 - VVCC = 5V - 3.33 - V

Threshold Current (Note3) ITH ---- - 0.1 0.25 µA

Trigger Voltage VTRVCC = 5V 1.1 1.67 2.2 VVCC = 15V 4.5 5 5.6 V

Trigger Current ITR VTR = 0V 0.01 2.0 µAReset Voltage VRST ---- 0.4 0.7 1.0 VReset Current IRST ---- 0.1 0.4 mA

Low Output Voltage VOL

VCC = 15VISINK = 10mAISINK = 50mA

- 0.060.3

0.250.75

VV

VCC = 5VISINK = 5mA - 0.05 0.35 V

High Output Voltage VOH

VCC = 15VISOURCE = 200mAISOURCE = 100mA 12.75

12.513.3

- VV

VCC = 5VISOURCE = 100mA 2.75 3.3 - V

Rise Time of Output (Note4) tR ---- - 100 - nsFall Time of Output (Note4) tF ---- - 100 - nsDischarge Leakage Current ILKG ---- - 20 100 nA

LM555/NE555/SA555

4444

Application InformationApplication InformationApplication InformationApplication InformationTable 1 below is the basic operating table of 555 timer:

When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage.When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.

1. Monostable Operation1. Monostable Operation1. Monostable Operation1. Monostable Operation

Table 1. Basic Operating TableTable 1. Basic Operating TableTable 1. Basic Operating TableTable 1. Basic Operating TableThreshold Voltage Threshold Voltage Threshold Voltage Threshold Voltage

(V(V(V(Vthththth)(PIN 6))(PIN 6))(PIN 6))(PIN 6)Trigger VoltageTrigger VoltageTrigger VoltageTrigger Voltage

(V(V(V(Vtrtrtrtr)(PIN 2))(PIN 2))(PIN 2))(PIN 2) Reset(PIN 4)Reset(PIN 4)Reset(PIN 4)Reset(PIN 4) Output(PIN 3)Output(PIN 3)Output(PIN 3)Output(PIN 3) Discharging Tr.Discharging Tr.Discharging Tr.Discharging Tr.(PIN 7)(PIN 7)(PIN 7)(PIN 7)

Don't care Don't care Low Low ONVth > 2Vcc / 3 Vth > 2Vcc / 3 High Low ON

Vcc / 3 < Vth < 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3 High - -Vth < Vcc / 3 Vth < Vcc / 3 High High OFF

10101010-5-5-5-5 10101010-4-4-4-4 10101010-3-3-3-3 10101010-2-2-2-2 10101010-1-1-1-1 101010100000 101010101111 10101010222210101010-3-3-3-3

10101010-2-2-2-2

10101010-1-1-1-1

101010100000

101010101111

101010102222

10M

10M

10M

10M

ΩΩΩΩ

1M1M1M1MΩΩΩΩ10

k10

k10

k10

kΩΩΩΩ10

0k10

0k10

0k10

0kΩΩΩΩ

RRRR AAAA=1k=1k=1k=1k

ΩΩΩΩ

C

apac

itanc

e(uF

)C

apac

itanc

e(uF

)C

apac

itanc

e(uF

)C

apac

itanc

e(uF

)

Time Delay(s)Time Delay(s)Time Delay(s)Time Delay(s)

Figure 1. Monoatable CircuitFigure 1. Monoatable CircuitFigure 1. Monoatable CircuitFigure 1. Monoatable Circuit Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs. Time delay(tTime delay(tTime delay(tTime delay(tdddd))))

Figure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable Operation

1

5

6

7

84

2

3

RESET VccDISCH

THRES

CONTGND

OUT

TRIG

+Vcc

RA

C1

C2RL

Trigger

LM555/NE555/SA555

5555

Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3 at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop, turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship based on RA and C. Figure 3 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such a timer output abnormality.

2. Astable Operation2. Astable Operation2. Astable Operation2. Astable Operation

Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)

100m100m100m100m 1111 10101010 100100100100 1k1k1k1k 10k10k10k10k 100k100k100k100k1E-31E-31E-31E-3

0.010.010.010.01

0.10.10.10.1

1111

10101010

100100100100

10M10M10M10M

ΩΩΩΩ

1M1M1M1MΩΩΩΩ

100k100k100k100kΩΩΩΩ

10k10k10k10kΩΩΩΩ

1k1k1k1kΩΩΩΩ

(R(R(R(R AAAA+2R+2R+2R+2R BBBB))))

Cap

acita

nce(

uF)

Cap

acita

nce(

uF)

Cap

acita

nce(

uF)

Cap

acita

nce(

uF)

Fr equency(Hz)Frequency(Hz)Frequency(Hz)Frequency(Hz)

Figure 5. Astable CircuitFigure 5. Astable CircuitFigure 5. Astable CircuitFigure 5. Astable Circuit Figure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. Frequency

1

5

6

7

84

2

3

RESET VccDISCH

THRES

CONTGND

OUT

TRIG

+Vcc

RA

C1

C2RL

RB

LM555/NE555/SA555

6666

An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C. When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges through the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the VC1 rises again. In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:

Since the duration of the timer output high state(tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,

Figure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable Operation

Vcc

RA RB

C1 Vc1(0-)=Vcc/3

C1dvc1

dt-------------

Vcc V 0-( )–

RA RB+-------------------------------= 1( )

VC1 0+( ) VCC 3⁄= 2( )

VC1 t( ) VCC 1 23---e

- tRA RB+( )C1

------------------------------------–

–

= 3( )

LM555/NE555/SA555

7777

The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:

Since the duration of the timer output low state(tL) is the amount of time it takes for the VC1(t) to reach Vcc/3,

Since RD is normally RB>>RD although related to the size of discharging Tr.,tL=0.693RBC1 (10)

Consequently, if the timer operates in astable, the period is the same with 'T=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies.

3. Frequency divider3. Frequency divider3. Frequency divider3. Frequency dividerBy adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.

VC1 t( ) 23---VCC V=

CC1 2

3---e

-tH

RA RB+( )C1------------------------------------–

–

= 4( )

tH C1 RA RB+( )In2 0.693 RA RB+( )C1== 5( )

C1

RB

RDVC1(0-)=2Vcc/3

C1dvC1

dt-------------- 1

RA RB+-----------------------VC1 0=+ 6( )

VC1 t( ) 23---V

CCe

- tRA RD+( )C1

-------------------------------------

= 7( )

13---VCC

23---V

CCe

-tL

RA RD+( )C1-------------------------------------

= 8( )

tL C1 RB RD+( )In2 0.693 RB RD+( )C1== 9( )

frequency, f 1T--- 1.44

RA 2RB+( )C1----------------------------------------= = 11( )

LM555/NE555/SA555

8888

4. Pulse Width Modulation4. Pulse Width Modulation4. Pulse Width Modulation4. Pulse Width ModulationThe timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit.When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control terminal. Figure 10 shows the example of pulse width modulation waveform.

5. Pulse Position Modulation5. Pulse Position Modulation5. Pulse Position Modulation5. Pulse Position ModulationIf the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11, the timer becomes a pulse position modulator.In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the timer output according to the modulation signal applied to the control terminal.Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave shape could be used.

Figure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider Operation

Figure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width Modulation Figure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width Modulation

84

7

1

2

3

5

6

CONTGND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc+Vcc+Vcc+Vcc

TriggerTriggerTriggerTrigger

RRRRAAAA

CCCC

OutputOutputOutputOutputInputInputInputInput

LM555/NE555/SA555

9999

6. Linear Ramp6. Linear Ramp6. Linear Ramp6. Linear RampWhen the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the generated linear ramp waveforms.

In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.

For example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V, VE=0.7V+10V=10.7VIc=(15-10.7)/20k=0.215mA

84

7

1

2

3

5

6

CONTGND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc+Vcc+Vcc+Vcc

RRRRAAAA

CCCC

RRRRBBBB

ModulationModulationModulationModulation

OutputOutputOutputOutput

Figure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position Modulation Figure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulation

Figure 13. Circuit for Linear RampFigure 13. Circuit for Linear RampFigure 13. Circuit for Linear RampFigure 13. Circuit for Linear Ramp Figure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear Ramp

1

5

6

7

84

2

3

RESET VccDISCH

THRES

CONTGND

OUT

TRIG

+Vcc

C2

R1

R2

C1

Q1

Output

RE

ICVCC VE–

RE---------------------------= 12( )

Here, VE is

VE VBER2

R1 R2+----------------------VCC+= 13( )

LM555/NE555/SA555

10101010

When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined as follows:

Here the Vp-p is the peak-to-peak voltage.If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:

V=Q/C (15)

The above equation divided on both sides by T gives us

and may be simplified into the following equation.

S=I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02µF, the gradient of the ramp function at both ends of the capacitor is S = 0.215m/0.022µ = 9.77V/ms.

SVp p–

T----------------= 14( )

VT---- Q T⁄

C------------= 16( )

LM555/NE555/SA555

11111111

Mechanical DimensionsMechanical DimensionsMechanical DimensionsMechanical DimensionsPackagePackagePackagePackage

Dimensions in millimetersDimensions in millimetersDimensions in millimetersDimensions in millimeters

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#1

#4 #5

#8

0.252 ±0.008

9.20

±0.

20

0.79

2.54

0.10

0

0.03

1(

)

0.46

±0.

10

0.01

8 ±0

.004

0.06

0 ±0

.004

1.52

4 ±0

.10

0.36

2 ±0

.008

9.60

0.37

8M

AX

5.080.200

0.330.013

7.62

0~15°

0.300

MAX

MIN

0.25+0.10–0.05

0.010+0.004–0.002

8-DIP8-DIP8-DIP8-DIP

LM555/NE555/SA555

12121212

Mechanical Dimensions Mechanical Dimensions Mechanical Dimensions Mechanical Dimensions (Continued)

PackagePackagePackagePackageDimensions in millimetersDimensions in millimetersDimensions in millimetersDimensions in millimeters

4.9

2 ±

0.2

0

0.1

94

±0.0

08

0.4

1 ±

0.1

0

0.0

16

±0.0

04

1.2

70

.05

0

5.720.225

1.55 ±0.20

0.061 ±0.008

0.1~0.250.004~0.001

6.00 ±0.30

0.236 ±0.012

3.95 ±0.20

0.156 ±0.008

0.50 ±0.20

0.020 ±0.008

5.1

30

.20

2M

AX

#1

#4 #5

0~8°

#8

0.5

60

.02

2(

)

1.800.071

MA

X0

.10

MA

X0

.00

4

MAX

MIN

+0.1

0-0

.05

0.1

5

+0.0

04

-0.0

02

0.0

06

8-SOP8-SOP8-SOP8-SOP

LM555/NE555/SA555

13131313

Ordering InformationOrdering InformationOrdering InformationOrdering InformationProduct NumberProduct NumberProduct NumberProduct Number PackagePackagePackagePackage Operating TemperatureOperating TemperatureOperating TemperatureOperating Temperature

LM555CN 8-DIP0 ~ +70°C

LM555CM 8-SOP

Product NumberProduct NumberProduct NumberProduct Number PackagePackagePackagePackage Operating TemperatureOperating TemperatureOperating TemperatureOperating TemperatureNE555N 8-DIP

0 ~ +70°CNE555D 8-SOP

Product NumberProduct NumberProduct NumberProduct Number PackagePackagePackagePackage Operating TemperatureOperating TemperatureOperating TemperatureOperating TemperatureSA555 8-DIP

-40 ~ +85°CSA555D 8-SOP

LM555/NE555/SA555LM555/NE555/SA555LM555/NE555/SA555LM555/NE555/SA555

11/29/02 0.0m 001Stock#DSxxxxxxxx

2002 Fairchild Semiconductor Corporation

LIFE SUPPORT POLICY LIFE SUPPORT POLICY LIFE SUPPORT POLICY LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

DISCLAIMER DISCLAIMER DISCLAIMER DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

© 2001 Fairchild Semiconductor Corporation DS006494 www.fairchildsemi.com

August 1986

Revised July 2001

DM

7404 Hex In

verting

Gates

DM7404Hex Inverting Gates

General DescriptionThis device contains six independent gates each of whichperforms the logic INVERT function.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function TableY = A

H = HIGH Logic LevelL = LOW Logic Level

Order Number Package Number Package Description

DM7404M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

DM7404N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Inputs Output

A Y

L H

H L

www.fairchildsemi.com 2

DM

7404 Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.

Recommended Operating Conditions

Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Note 2: All typicals are at VCC = 5V, TA = 25°C.

Note 3: Not more than one output should be shorted at a time.

Switching Characteristics at VCC = 5V and TA = 25°C

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range 0°C to +70°CStorage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 16 mA

TA Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions MinTyp

Max Units(Note 2)

VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max2.4 3.4 V

Output Voltage VIL = Max

VOL LOW Level VCC = Min, IOL = Max0.2 0.4 V

Output Voltage VIH = Min

II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA

IOS Short Circuit Output Current VCC = Max (Note 3) −18 −55 mA

ICCH Supply Current with Outputs HIGH VCC = Max 6 12 mA

ICCL Supply Current with Outputs LOW VCC = Max 18 33 mA

Symbol Parameter Conditions Min Max Units

tPLH Propagation Delay Time CL = 15 pF22 ns

LOW-to-HIGH Level Output RL = 400Ω

tPHL Propagation Delay Time15 ns

HIGH-to-LOW Level Output

3 www.fairchildsemi.com

DM

7404Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage Number M14A


DM

7404

Hex

Inve

rtin

g G

ates Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.

2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.



August 1986

Revised March 2000

DM

74LS

08 Qu

ad 2-In

pu

t AN

D G

ates

DM74LS08Quad 2-Input AND Gates

General DescriptionThis device contains four independent gates each of whichperforms the logic AND function.

Ordering Code:


Connection Diagram Function TableY = AB



DM74LS08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS08SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Output

A B Y

L L L

L H L

H L L

H H H


DM

74L

S08 Absolute Maximum Ratings(Note 1)



Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)



Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C









Max Units(Note 2)


VOH HIGH Level VCC = Min, IOH = Max,2.7 3.4 V


VOL LOW Level VCC = Min, IOL = Max,0.35 0.5

Output Voltage VIL = Max V

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA




ICCH Supply Current with Outputs HIGH VCC = Max 2.4 4.8 mA

ICCL Supply Current with Outputs LOW VCC = Max 4.4 8.8 mA

RL = 2 kΩ

Symbol Parameter CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time4 13 6 18 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time3 11 5 18 ns



DM

74LS


14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 NarrowPackage Number M14A


DM

74L

S08 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M14D


DM

74LS

08 Qu

ad 2-In

pu

t AN

D G

atesPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N14A


LIFE SUPPORT POLICY






June 1986

Revised March 2000

DM

74LS

32 Qu

ad 2-In

pu

t OR

Gate

DM74LS32Quad 2-Input OR Gate

General DescriptionThis device contains four independent gates each of whichperforms the logic OR function.

Ordering Code:


Connection Diagram Function TableY = A + B



DM74LS32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74LS32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Output

A B Y

L L L

L H H

H L H

H H H


DM

74L

S32 Absolute Maximum Ratings(Note 1)



Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)


Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.


Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C









Max Units(Note 2)


VOH HIGH Level VCC = Min, IOH = Max2.7 3.4 V


VOL LOW Level VCC = Min, IOL = Max0.35 0.5

Output Voltage VIL = Max V

IOL = 4 mA, VCC = Min 0.25 0.4

II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 mA




ICCH Supply Current with Outputs HIGH VCC = Max 3.1 6.2 mA

ICCL Supply Current with Outputs LOW VCC = Max 4.9 9.8 mA

RL = 2 kΩ

Symbol Parameter CL = 15 pF CL = 50 pF Units

Min Max Min Max

tPLH Propagation Delay Time3 11 4 15 ns

LOW-to-HIGH Level Output

tPHL Propagation Delay Time3 11 4 15 ns



DM

74LS


14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 NarrowPackage Number M14A


DM

74L

S32 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M14D


DM

74LS

32 Qu

ad 2-In

pu

t OR

Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 WidePackage Number N14A


LIFE SUPPORT POLICY





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