Licinio Sousa - MIPI Alliance

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Licinio Sousa Synopsys Why an Integrated MIPI C-PHY/ D-PHY IP is Essential

Transcript of Licinio Sousa - MIPI Alliance

Page 1: Licinio Sousa - MIPI Alliance

Licinio SousaSynopsys

Why an Integrated MIPI C-PHY/D-PHY IP is Essential

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© 2020 MIPI Alliance, Inc.

A G E N D A MIPI Camera and Display Market Trends

MIPI Camera & Display Standards

MIPI for Consumer & Automotive: Implementation Examples

MIPI CSI-2

D-PHY C-PHY

MIPI DSI/DSI-2

D-PHY C-PHY

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Camera Innovations for Growing Vision Processing NeedsFor Human Vision and Machine Vision

Image source: Qualcomm.com, Omnivision.com, NXP.com

• 100+ mega-pixel image sensors• AI-enabled image sensors • Mobile More pixels, more and bigger image sensors • Vision systems - the heart of automotive ADAS/IVI

– HDR, SNR, NIR, resolution, size, power, ASIL x /Grade x – Multiple IS combined with other sensing technologies

• IoT, edge, MCUs with machine vision capabilities – Face recognition for home appliances

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Dual Display, Foldable, 120Hz, Higher ResolutionsDisplay Innovations Driven by Mobile and Automotive

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MIPI CSI-2

D-PHY C-PHY

MIPI DSI/DSI-2

D-PHY C-PHY

MIPI Camera and Display SpecificationsEvolving to Address Growing Imaging Needs

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MIPI Physical Layers

M I P I D - P H Y M I P I C - P H Y

• Source synchronous architecture • High-speed and low-power modes for efficiency • Proven, mature and widely adopted

• Higher bandwidth transmission on restricted channels – CoG, CoF, CoP

• Key concepts: trios and 3-phase encoding• Bitrate ~2.28x the signaling rate• Single ended drivers; differential receivers

HS DP/DN

LP DPLP DN

HS CKP/CKN

LP CKPLP CKN

LP DPLP DN

LP CKPLP CKN

A

B

C

AB

BC

CA

Differential RxSingle-Ended Tx

CDRDEC

D-MAP

1.5G 2.5G 4.5GSSC

4.5GaLP/fBTA

9G

Timelinev1.2 v2.1 v2.5 v3.0v1.1

Timeline

2.5G 3.5G 6G

v1.2 v2.0v1.x

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• Electrical specs are similar • Low-power modes are identical • Most of the of the circuits are re-used

– Aside from line drivers/receivers,• C-PHY and D-PHY pins can co-exist in 10 pins

– 4 lanes and 3 trios

• Satisfies most important KPI– Maturity– Backwards compatibility– Flexibility– Performance– Power efficiency – EMI

The Best of Both WorldsIntegrated MIPI C-PHY/D-PHY Solution

MIPI CSI-2 and DSI/DSI-2 Controllers

Integrated MIPI C-PHY/D-PHY

Data Lane 0

Data Lane 1

Clklane Data Lane 2

Data Lane 3Trio 0 Trio 1 Trio 2

dp0 dn0 dp1 dn1 ckp ckn dp2 dn2 dp3 dn3

D-PHY or C-PHY/D-PHY devices

t0_1 t0_2 t0_3 t1_1 t1_2 t1_3 t2_1 t2_2 t2_3

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MIPI CSI-2 Going From Mobile to a Vision Platform Evolving to Address Growing Vision Processing Needs

MIPI CSI-2 V1.x

RES

FPS

BPP

CCI

MIPI CSI-2 V2.x

VCx

PSD

LRTE

DPCM

MIPI CSI-2 V3.x

USL

SROI

RAW24

MIPI CSI-2 V4.x

AOSC

FSAF

A-PHY

ISEC

RAW16/20

MIPI C-PHY

MIPI D-PHY

Mobile Vision Platform

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MIPI DSI/DSI-2: Defacto Interface for Embedded DisplaysMIPI DSI V1.x

RES

FPS

BPP

MIPI DSI-2 V1.1

PSD

VESA VDC-M

MIPI DSI-2 V1.2

CONTENT

MIPI A-PHY

MIPI D-PHY

MIPI C-PHY

Mobile Embedded Display

VESA DSC1.1

FSAF

OTHER

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Use Case with DesignWare MIPI C-PHY/D-PHY IP SolutionCase Studies: Enabling Camera ISP and Enhanced Mobile Display Quality

CSI-2 Host ComboController

CD-P

HY

Rx

CSI-2 Device Combo

Controller

CD-P

HY

Tx

Application Processor

AI enabled video/ image

processing pathCD

-PHY

Rx

CD-P

HY

Rx

CD-P

HY

TxCD

-PHY

Tx

MIPI CSI-2 Host ComboController

CD-P

HY

Rx

MIPI CSI-2 Device Combo

Controller

CD-P

HY

Tx

Application Processor

AI enabled Video/Image

processing pathCD-P

HY

RxCD

-PHY

Rx

CD-P

HY

TxCD

-PHY

Tx

DSI2 Device ComboControl

ler

CD-

PHY

Rx DSI-2 HostCombo

Controller

CD-

PHY

TxApplication Processor

Video/image

processing path

DSI2 Device Combo

ControllerCD-P

HY

Rx

DSI2 HostCombo

Controller CD-P

HY

TxApplication Processor

Video/Image processing

path

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Interop With State-Of-The-Art Image Sensor & DJI SoC Platform

• To satisfy challenging camera interface bandwidth requirements for the next generation camera drone products

• DJI’s SoC platform successfully interoperating with advanced 64 mega-pixel sensor up to 3.5 Gsps

DJI use case with DesignWare C-PHY/ D-PHY IP Solution

Synopsys DesignWare C-PHY/D-PHY IP in 12nm + 64MP image sensor

Synopsys HW setup

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Example of MIPI In An Automotive ApplicationMIPI CSI-2 Sensors & DSI Displays

Aggregator

Aggregator

ECU/ADAS/IVI

Long Reach

Long Reach

Long Reach

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Automotive Grade IP Essentials Reduce Risk and Accelerate Qualification for Automotive SoCs

Meet quality levels required for automotive applications

Reduce risk & development time for AEC-Q100 qualification of SoCs

Accelerate ISO 26262 functional safety assessments to help ensure designers reach target ASIL levels

Reliability

Functional Safety

Quality

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Valens use case with DesignWare C-PHY/D-PHY IP Solution

Valens automotive technology enables in-vehicle high-speed links for cameras and sensors with long-reach CSI-2

For Next-Generation Long-Reach CSI-2 Connectivity

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Summary

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DesignWare MIPI IP Solution for Camera & Display

CSI-2 TX

C-PH

Y/D

-PH

Y Tx

D-P

HY

Tx

CSI-2 RX

C-PH

Y/D

-PH

Y Rx

D-P

HY

Rx DSI-2TX+

DSC

C-PH

Y/D

-PH

Y Tx

D-P

HY

Tx

Image Sensor IC

Host Processor / SoC

Display Driver IC

DSI-2RX+

DSC

C-PH

Y/D

-PH

Y Rx

D-P

HY

Rx

D-PHY and C-PHY/D-PHY Solution

• D-PHY v1.2• Integrated C-PHY v1.2 / D-PHY v2.1• Controllers supporting key features

of the latest specifications • 2.5 Gbps & 4.5 Gbps / 3.5 Gsps• Available in 40-nm - 5-nm• ASIL B Ready ISO 26262 certified IP• 500+ licenses; 30+ test chips• Adopted by tier1s• Mobile/drone/DSC/ surveillance/IoT• interoperability with wide range of

devices

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