LIC Lab Manual

LABORATORY MANUAL

SHANMUGHA ARTS, SCIENCE, TECHNOLOGY AND RESEARCH ACADEMY

TIRUMALAISAMUDRAM, THANJAVUR - 613402

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

COURSE NAME: LINEAR INTEGRATED CIRCUIT LABORATORY COURSE CODE: BECCEC 408 SEMESTER: IV

REVISED DECEMBER 2007

We welcome your suggestions regarding the manual. If you find any errors or anything else that you think is an error, please feel free to mail us at [email protected]

TABLE OF CONTENTS

A. LABORATORY SAFETY INFORMATION

B. GUIDELINES FOR LABORATORY RECORD

C. TROUBLESHOOTING HINTS

D. EXPERIMENTS

1. INVERTING AND NON-INVERTING AMPLIFIER USING OP-AMP 2. SUMMER, SUBTRACTOR AND SCALE CHANGER USING OP-AMP 3. INTEGRATOR AND DIFFERENTIATOR USING OP-AMP 4. PRECISION HALF WAVE AND FULL WAVE RECTIFIER 5. RECTANGULAR AND TRIANGULAR WAVE GENERATOR 6. WEIN BRIDGE OSCILLATOR USING OP-AMP 7. RC PHASE SHIFT OSCILLATOR USNG OP-AMP 8. ASTABLE MULTIVIBRATOR USING OP-AMP 9. SECOND ORDER ACTIVE LOW PASS AND HIGH PASS FILTER 10. SAMPLE AND HOLD CIRCUIT USING OP-AMP 11. MONOSTABLE AND ASTABLE MULTIVIBRATOR USING IC 555 12. MEASURMENT OF CAPTURE RANGE AND LOCK-IN RANGE OF

A PHASE LOCKED LOOP USING IC 565

13. VOLTAGE REGULATION USING 78XX AND 79XX

E. APPENDIX

DATA SHEETS OF OP-AMP LM741, TIMER LM555 AND PLL LM565

LABORATORY SAFETY INFORMATION Introduction The danger of injury or death from electrical shock, fire or explosion is present while conducting experiments in this laboratory. To work safely, it is important that you understand the prudent practices necessary to minimize the risks and what to do if there is an accident. Electrical Shock Avoid contact with conductors in energized electrical circuits. Electrocution has been reported at DC voltages as low as 42 volts. Just 100 mA of current passing through the chest is usually fatal. Muscle contractions can prevent the person from moving away while being electrocuted. Do not touch someone who is being shocked while still in contact with the electrical conductor or you may also be electrocuted. Instead, switch off the power supply to the workbench (switch is located on the side of workbench.). This shuts off all the power to the workbench. Make sure your hands are dry. The resistance of dry, unbroken skin is relatively high and thus reduces the risk of shock. Skin that is broken, wet or damp with sweat has a low resistance. When working with an energized circuit, work with only your right hand, keeping your left hand away from all conductive material. This reduces the likelihood of an accident that results in current passing through your heart. Be cautious of rings, watches and necklaces. Skin beneath a ring or watch is damp, lowering the skin resistance. Wear rubber soul shoes. Shoes covering the feet are much safer than sandals. If the victim isn’t breathing, find someone for CPR. Immediately contact the laboratory instructor and call an ambulance. Fire Transistors and other components can become extremely hot and cause severe burns if touched. If resistors or other components on your breadboard catch fire, turn off the power supply and notify the instructor. If electronic instruments catch fire, switch off the power supply to the workbench. These small electrical fires extinguish quickly after the power is shut off. Avoid using fire extinguisher on electronic instruments. Explosion When using electrolytic capacitors, be careful to observe proper polarity and do not exceed the voltage rating. Electrolytic capacitors can explode and cause injury.

GUIDELINES FOR LABORATORY RECORD This laboratory manual is a record of all work pertaining to the experiment. This record should be sufficiently complete so that you or anyone else of similar technical background can duplicate the experiment and data by simply following your record notebook. Record everything directly into the notebook during the experiment. Do not use scratch paper for recording the data. Do not trust your memory to fill in the details at a later time. Organization in your notebook is important. Record data in chronological order. The experiment number and date should be at the top of each page. A neat, organized and complete record of an experiment is just as important as the experimental work. Each experiment is organized through the following sections.

1. Introduction: An explanatory section at beginning of each experiment. Defines key terms in the experiment and describes its scope.

2. Objective: Brief but complete statements of what you intend to find out or verify

in the experiment.

3. Circuit diagram: An example circuit diagram for the experiment’s circuitry. You are encouraged to design circuits on your own that fulfill the given objectives.

4. Design: Space for the design of the circuit and related calculations. You are

expected to write down all the calculations and equations related to your design, as part of the pre-lab work. ‘Design’ includes your choice of specific values for the components in the circuit. Attach an extra sheet if the provided space is insufficient. It is highly recommended that you simulate and test the designed circuits before coming to the lab.

5. Procedure: Modus operandi of the experiment. A brief description of the various

steps involved in the experiment.

6. Tabulation: Data tables to record the measurements directly.

7. Questions: Questions to make you probe deeper into the experiment. Draws your attention to finer details of the experiment.

8. Notes: Space for recording any related observations or questions you have

regarding the experiment.

9. Result and Inferences: Space to write down the result of the experiment and your inferences from the observations and the result.

TROUBLESHOOTING HINTS

When a circuit does not perform as expected, look for simple reasons. Do not design a new circuit, correct the old one. A circuit will perform as expected at first only 10% of the time (With experience, this figure may go as high as 30%). The reason for failure lies not in the central idea, which of course you worked out impeccably; it always lies in some secondary consideration like biasing, loose connections etc. Occasionally the cause is not simple. In such a case, the only hope is a brand new circuit. However, simple causes usually masquerade as complicated ones until they are found.

1. Be sure that the power is turned on.

2. Be sure the ground connections are common.

3. Be sure the circuit you built is identical to that in the diagram. Do a node-by-node check.

4. Be sure that the supply voltages are correct.

5. Be sure that the equipment is set up correctly and you are measuring the correct

parameter.

6. If steps 1 through 5 are correct, then you probably have used a component with the wrong value or one that doesn’t work. It is also possible that the equipment does not work (although this is not probable) or the breadboards you are using may be faulty and have some unwanted paths between the nodes. To find your problem, you must trace through the voltages in your circuit node by node and compare the signal you have to the signal you expect to have. Then if they are different use your engineering judgment to decide what is causing the different or ask your lab instructor.

CIRCUIT DIAGRAMS

vo

vin

R3

R1

RL

R2

vin

vo

R3 RL

R1

R2

Fig 1.1 Inverting amplifier Fig. 1.2 Non-inverting amplifier

DESIGN

Experiment 1 Date: _____________ INVERTING AND NON-INVERTING AMPLIFIER USING OP-AMP

INTRODUCTION

In an inverting amplifier, the input signal is amplified and inverted at the output i.e. Vo = A .Vi. For inverting amplifier, A takes a negative value and is called the Voltage Gain of the amplifier. A non-inverting amplifier, like its inverting counterpart, amplifies the input signal. But the voltage gain A is positive in this case. This exercise concerns itself with the design of direct-coupled amplifier only. You are encouraged to study and perform experiments on capacitor-coupled amplifiers too.

OBJECTIVE

1. To design, construct and test a Direct-coupled inverting amplifier of voltage gain ______.

2. To design, construct and test a Direct-coupled non-inverting amplifier of voltage gain ______.

3. To study the designed amplifiers and establish the relationship between input and output waveforms.

PROCEDURE

Inverting amplifier 1. Design and construct the inverting amplifier circuit shown in Fig 1.1. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply a 1 KHz sinusoidal signal and adjust the signal amplitude to give an output

of peak to peak amplitude of 0.1 V as displayed on an oscilloscope. 4. Measure the input peak amplitude, calculate the voltage gain, and compare it to

the designed gain. 5. Connect a 1KΩ resistor in series with the amplifier input. Note the output voltage

change and calculate the input impedance Zin. 6. Adjust the signal to give a peak output of 1V. Then, connect a 100Ω resistor in

parallel with the output. Check that the output voltage is unaffected to demonstrate that the output impedance Zout « 100Ω.

7. Repeat Procedures 3 through 6 with a non-sinusoidal input waveform of different amplitude and frequency.

Non-inverting amplifier

1. Design and construct the non-inverting amplifier circuit shown in Fig 1.2. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply a 1 KHz sinusoidal signal and adjust the signal amplitude to give an output

of peak to peak amplitude of 0.1 V as displayed on an oscilloscope.

4. Measure the input peak amplitude, calculate the voltage gain, and compare it to the designed gain.

5. Connect a 1MΩ resistor in series with the amplifier input. Check that the output voltage is unaffected to demonstrate that Zin » 1MΩ.

6. Connect a 100Ω resistor in parallel with the output. Check that the output voltage is unaffected to demonstrate that Zout « 100Ω.

7. Repeat Procedures 3 through 6 with a non-sinusoidal input waveform of different amplitude and frequency.

You are encouraged to study the gain/frequency response and phase/frequency response of the designed amplifiers to demonstrate the effect of bandwidth and slew rate of op-amp on the output waveforms. You are also encouraged to determine the Gain-Bandwidth Product of the op-amp used.

TABULATION

Inverting Amplifier

No. of divisions Observation parameter Waveform X-axis Y-axis

Timediv.

Volts div.

Amplitude Freq.

Voltage at input Sinusoidal

0.1 Vp-p 1 KHz

Voltage at output

Voltage Gain = _______ Zin = _______ Tick if Zout « 100Ω


Timediv.

Volts div.

Amplitude Freq.

Voltage at input

Voltage at output

Voltage Gain = _______ Zin = _______ Tick if Zout « 100Ω

Non- Inverting amplifier


Timediv.

Volts div.

Amplitude Freq.


0.1 Vp-p 1 KHz

Voltage at output

Voltage Gain = _______ Tick if Zin » 1MΩ Tick if Zout «100Ω


Timediv.

Volts div.

Amplitude Freq.

Voltage at input

Voltage at output

Voltage Gain = _______ Tick if Zin » 1MΩ Tick if Zout « 100Ω

QUESTIONS

1. An amplifier if designed to have a voltage gain of 10 for a 1 KHz input sinusoid signal. What would be the observed gain if 1 KHz signal is replaced by a 1 MHz signal? Would it be equal to the designed value of gain?

2. What would be the output waveform if a 500 KHz triangular wave is given as input?

3. For a voltage gain of 2 in an inverting amplifier, R2 should be twice of R1. What prevents us from making a choice of R2 = 100 MΩ and R1 = 50 MΩ?

RESULT AND INFERENCES

CIRCUIT DIAGRAMS

R2

R5

RL

R f R1

R3

R4 Vi4

Vi3

Vi1

Vi2 Vo

RL R

R

R

R R

R

Vi4

Vi3

Vo

Fig. 2.1 Differential configuration Fig. 2.2 Non-inverting summer

R

RL R

R

R

R R

Vi2

Vi1

Vo

R

RL R

R

R

R R

Vi4

Vi1

Vo

Fig. 2.4 Subtractor Fig. 2.3 Inverting summer

Experiment 2 Date: _____________

SUMMER, SUBTRACTOR AND SCALE CHANGER USING OP-AMP

INTRODUCTION

The differential op-amp configuration, as shown in Fig. 2.1, can be used to sum or subtract the input signals. The circuit is then known as summer or subtractor respectively. Input signals can be scaled to the desired values by selecting appropriate values for the external resistors R1, R2, R3 and R4; when this is done, the circuit is referred to as scaling amplifier or scale changer.

OBJECTIVE

1. To design, construct and test a non-inverting summer circuit that implements an equation Vo = Vi3 + Vi4

2. To design, construct and test an inverting summer circuit that implements an equation Vo = – ( Vi1 + Vi2 )

3. To design, construct and test a subtractor circuit that implements an equation Vo = Vi1 – Vi4.

4. To design, construct and test a scaling amplifier that implements an equation Vo = ___Vi1 + ___Vi2 – ___Vi3 – ___Vi4.

5. To study the designed circuits and compare the experimental and calculated results.

PROCEDURE

Design and construct the differential op-amp circuit in Fig. 2.1. Use R1 = R2 = R3 = R4 = R. Non-inverting summer 1. Connect input 1 and input 2 to signal ground. See Fig. 2.2 2. Connect adjustable dc voltage sources to input 3 and input 4 and connect dc

voltmeters to monitor the levels of Vi3 and Vi4. You may use potential dividers to give the desired dc voltage at inputs. Multi-meter configured as dc voltmeter can be used to monitor voltage levels.

3. Set each input to several voltage levels between 0.1 V to 2V and measure the output level for each case to check for accuracy of the equation.

Inverting summer 1. Connect input 3 and input 4 to signal ground. See Fig. 2.3 2. Connect adjustable dc voltage sources to input 1 and input 2 and connect dc

voltmeters to monitor the levels of Vi1 and Vi2. 3. Set each input to several voltage levels between 0.1 V to 2V and measure the

output level for each case to check for accuracy of the equation.

DESIGN

Subtractor 1. Connect input 2 and input 3 to signal ground. See Fig. 2.4 2. Connect adjustable dc voltage sources to input 1 and input 4 and connect dc

voltmeters to monitor the levels of Vi1 and Vi4. 3. Set each input to several voltage levels between 0.1 V to 2V and measure the

output level for each case to check for accuracy of the equation. Scaling Amplifier 1. Design the differential op-amp circuit in Fig. 2.1 so that it satisfies the given

equation. Construct the designed circuit. 2. Connect adjustable dc voltage sources to each input and connect dc voltmeters to

monitor their levels. 3. Set each input to several voltage levels between 0.1 V to 2V and measure the

output level for each case to check for accuracy of the equation. You are encouraged to repeat the above exercises with ac input sources and study the resulting output waveforms.

TABULATION

Non-inverting summer

Measured value Observation parameter

Set 1 Set 2 Set 3

Input voltage Vi3 Input voltage Vi4

Output voltage Vo

Calculated output voltage Average error: ________ % error

Inverting summer

Measured value

Observation parameter Set 1 Set 2 Set 3


Output voltage Vo

Calculated output voltage Average error: __________% error

Subtractor


Set 1 Set 2 Set 3


Output voltage Vo

Calculated output voltage Average error: ________ % error

Scaling amplifier


Set 1 Set 2 Set 3 Input voltage Vi1

Input voltage Vi2 Input voltage Vi3 Input voltage Vi4 Output voltage Vo

Calculated output voltage Average error: ________

% error

QUESTIONS

1. What is the input impedance of a non inverting summer for the input signal source 3? Is it equal to the input impedance for the input signal source 4?

2. What would be the effect of an asymmetrical power supply ( |VCC| ≠ |VEE| ) on the output of a differential configuration?


CIRCUIT DIAGRAMS

VoutVin

R2

R3

R1

C

VoutVin C

R3

R2

R1

Fig 3.1 Integrator Fig. 3.2 Differentiator

DESIGN


INTEGRATOR AND DIFFERENTIATOR USING OP-AMP

INTRODUCTION

Differentiation and integration can be performed by op-amp circuits. In an integrating circuit, the output waveform is proportional the integral of the input voltage waveform. Thus an integrator produces an output, proportional to the area under the input waveform. A differentiator circuit produces the output amplitude proportional to the rate of change of an input voltage.

OBJECTIVE

1. To design, construct and test an integrating circuit that produces a triangular output waveform with peak to peak amplitude (Vp-p) of ____ V in response to the input of a ____ V peak to peak square wave with a frequency of ______ Hz.

2. To design, construct and test a differentiating circuit that gives an output of ______ V when the rate of change of the input is _____ V/ms.

3. To study the designed integrator and differentiator circuits and establish the relationship between input and output waveforms.

PROCEDURE

Integrator 1. Design and construct the op-amp integrating circuit shown in Fig. 3.1. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply the given square wave input. 4. Observe the input and output waveforms on an oscilloscope. Draw them for a

comparison with the theoretically expected waveforms. Also measure the positive and negative output voltage peaks.

5. Replace the square wave with a 0.1 Vp-p sine wave of the same given frequency. Observe the input and output waveforms. Slowly reduce the frequency to discover the minimum frequency fmin at which sine wave integration occurs.

6. Repeat Procedure 4 for a different input waveform. You are encouraged to choose a non sinusoidal waveform with different frequency and amplitude.

Differentiator

1. Design and construct the op-amp integrating circuit shown in Fig. 3.2. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply a triangular waveform that has the given rate of change of voltage. 4. Observe the input and output waveforms on an oscilloscope. Draw them for a

comparison with the theoretically expected waveforms. Also measure the positive and negative output voltage peaks.

5. Replace the triangular input with a 0.1 Vp-p, 100 Hz square wave. Observe the input and output waveforms.

6. Replace the square wave with a 0.1 Vp-p, 100 Hz sine wave. Observe the input and output waveforms. Slowly increase the frequency to discover the maximum frequency fmax at which sine wave differentiation occurs.

TABULATION

Integrator


Timediv.

Volts div.

Amplitude Freq.

Voltage at input

Square wave

Voltage at output

fmin = _______

Differentiator


Timediv.

Volts div.

Amplitude Freq.

Voltage at input

Voltage at output

fmax = ______

QUESTIONS

1. Which of the two circuits, integrator or differentiator, is more sensitive to noise at the input? What modifications can be done to desensitize the circuit towards noise? 2. Justify the observed values of fmax and fmin, theoretically.


CIRCUIT DIAGRAMS

Vout

D1

D2

RL R3

R2

Vin R1

D1

Vin

R1 R2

RL

Vout

Fig. 4.1 Saturating precision half wave rectifier with voltage gain

Fig. 4.2 Non-saturating precision half wave rectifier with voltage gain

Precision rectifier Summing circuit

Vout Vin

D1

D1

R7

R5

R6

R4

R3

R2

R1

Fig. 4.3 Full-wave precision rectifier with voltage gain


PRECISION HALF WAVE AND FULL WAVE RECTIFIER

INTRODUCTION

Unlike conventional diode rectifiers, precision half wave and full wave rectifiers can rectify signals with peak value down to few millivolts. An op-amp non-inverting amplifier can be converted into a saturating precision half wave rectifier by including a diode at its output. An inverting op-amp amplifier can be converted into a Non-saturating precision half wave rectifier by the inclusion of two diodes. Non saturating precision rectifier has a better frequency response. A Full-wave precision rectifier can be constructed using a summing circuit and a precision half wave rectifier.

OBJECTIVE

1. To design, construct and test a Saturating precision rectifier with a voltage gain of ____

2. To design, construct and test a Non-saturating precision rectifier with a voltage gain of ____.

3. To design, construct and test a Full wave precision rectifier with a voltage gain of ____.

4. To study the designed rectifiers and establish the relationship between input and output waveforms.

PROCEDURE

Saturating half wave precision rectifier

1. Design and construct the saturating half wave precision rectifier circuit shown in Fig 4.1.

2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply a 0.1 Vp-p, 1 KHz sine wave signal input. Observe the output waveform and

carefully measure the peak amplitude of the output voltage. 4. Gradually increase the input signal frequency to discover the maximum frequency

at which the circuit is still operating correctly without any distortion in the output.

Non-saturating half wave precision rectifier

1. Design and construct the non-saturating half wave precision rectifier circuit shown in Fig 4.2.

2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply a 0.1 Vp-p, 1 KHz sine wave signal input. Observe the output waveform and

carefully measure the peak amplitude of the output voltage. 4. Gradually increase the signal frequency to discover the maximum frequency at

which the circuit is still operating correctly without any distortion in the output.

DESIGN

Full-wave precision rectifier 1. Design and construct the non-saturating full wave precision rectifier circuit shown

in Fig 4.3. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply a 0.1 Vp-p, 1 KHz sine wave signal input. Observe the output waveform and

carefully measure the peak amplitude of the output voltage. 4. Gradually increase the signal frequency to discover the maximum frequency at

which the circuit is still operating correctly without any distortion in the output. You are encouraged to repeat the above procedures for conventional diode rectifier circuits and compare the output waveforms with that of precision op-amp rectifiers.

TABULATION

Saturating half wave precision rectifier


Timediv.

Volts div.

Amplitude Freq.


0.1 Vp-p 1 KHz

Voltage at output

fmax = ______ Non-saturating half wave precision rectifier


Timediv.

Volts div.

Amplitude Freq.


0.1 Vp-p 1 KHz

Voltage at output

fmax = ______

Full wave precision rectifier


Timediv.

Volts div.

Amplitude Freq.


0.1 Vp-p 1 KHz

Voltage at output

fmax = ______

QUESTIONS

1. Diode reverse recovery time (trr) is an important parameter of diodes. In what way you think, trr is going to limit the frequency response of the precision op-amp rectifiers?

2. Input impedance of non saturating precision rectifiers as shown in Fig. 4.2 and Fig. 4.3 is quite ordinary. Design precision rectifiers with high input impedance.


CIRCUIT DIAGRAM

Recatangular output

Triangular output D2

D1 C1

R3

R4

R2

R1

Fig. 5.1 Triangular / Rectangular waveform generator

DESIGN


RECTANGULAR AND TRIANGULAR WAVE GENERATOR

INTRODUCTION

Waveform generator circuits, continuously produce a particular waveform without any given input signal (except the power supply to energize the circuit). Op-amps are widely used in circuits for generating various waveforms. A triangular and rectangular waveform generator can be constructed simply by using a integrating circuit and a Schmitt trigger circuit. The integrator produces a triangular output waveform when it has a square wave input, and the Schmitt trigger produces a square wave output for a triangular wave input (it is assumed that the triangular wave is crossing the trigger levels). So if the Schmitt output is applied as an input to the integrator and the integrator output is the Schmitt circuit input, both the waveforms would be produced continuously.

OBJECTIVE

1. To design, construct and test a Rectangular waveform generator of frequency _____ KHz with a duty cycle of _____ %.

2. To design, construct and test a Triangular waveform generator of frequency _____ KHz with peak to peak amplitude of ______ V.

3. To study the designed circuit and compare the experimental and calculated results.

PROCEDURE

Rectangular waveform generator 1. Design and construct the Rectangular/Triangular wave generator circuit in

Fig.5.1, to fulfill objective 1. 2. Connect an oscilloscope to node A to monitor the output waveform. 3. Measure the output amplitude, frequency and duty cycle, and compare to the

designed values.

Triangular waveform generator 1. Design and construct the Rectangular/Triangular wave generator circuit in

Fig. 5.1, to fulfill objective 2. 2. Connect an oscilloscope to node B to monitor the output waveform. 3. Measure the output amplitude and frequency, and compare to the designed values.

You are encouraged to modify the circuit in Fig. 5.1 to provide a provision for frequency and duty cycle adjustment.

TABULATION

Integrator

No. of divisions Observation parameter

Waveform X-axis Y-axis

Timediv.

Volts div.

Amplitude Freq.

Voltage at output node A

TON ----- ----- ----- ----- -----

TOFF ----- ----- ----- ----- -----

TON: _______ TOFF: _______ Duty cycle: _______ Differentiator



Timediv.

Volts div.

Amplitude Freq.

Voltage at output node B

QUESTION

1. What is the total power consumed by the rectangular/triangular generator? What modifications in the design can be done to minimize the consumed power under the same load conditions?


CIRCUIT DIAGRAM

Vout

Fig. 6.1 Wein bridge oscillator

R2 C2

C1

R1

R3

R4

DESIGN

NOTES


WEIN BRIDGE OSCILLATOR USING OP-AMP

INTRODUCTION

Oscillators, like waveform generators, continuously produce a sinusoidal waveform without any given input signal. For oscillations to be sustained in any sinusoidal oscillator, certain conditions, known as Barkhausen criteria, must be fulfilled. These are that the loop gain around the circuit must be equal to one, and the phase shift around the circuit must be zero. Wein bridge oscillator consists of a non-inverting amplifier and a passive feedback network. The output voltage from the amplifier is attenuated but not phase shifted by the feedback network, and the feedback voltage is amplified to produce the output. The Barkhausen criteria for zero-loop phase shift are fulfilled, in this case, by the amplifier and the feedback network each having a zero phase shift. This occurs at only one particular frequency. At all other frequencies, the bridge output and feedback voltages do not have the correct phase or amplitude relationship to sustain oscillations.

OBJECTIVE

1. To design, construct and test a Wein bridge oscillator of frequency _____ KHz. 2. To study the designed circuit and compare the experimental and calculated

results.

PROCEDURE

1. Design and construct the Wein bridge oscillator circuit in Fig. 6.1. 2. Connect an oscilloscope to the output node to monitor the output waveform. 3. Measure the output amplitude, frequency, and compare to the designed quantities.

You are encouraged to modify the circuit for amplitude stabilization.

TABULATION

No. of divisions Observation

parameter Waveform

X-axis Y-axis Timediv.

Volts div.

Amplitude Freq.

Voltage at output node

QUESTION

1. Can you justify Barkhausen criteria for sustained oscillations? Why oscillations cannot be sustained if there is a non- zero loop phase shift?


CIRCUIT DIAGRAM

Vout

R R

C C C

R2

R1

Fig. 7.1 RC phase shift oscillator

DESIGN

NOTES


RC PHASE SHIFT OSCILLATOR USNG OP-AMP

INTRODUCTION

The RC phase shift oscillator circuit consists of an inverting amplifier and an RC phase shift network. The RC network feeds a portion of the amplifier ac output back to the amplifier input. The amplifier has an internal phase shift of −180° for all the frequencies but the phase shift network provides +180° of phase shift only to a single frequency. It is at this frequency that the Barkhausen criteria are satisfied and the signal fed back to the input is amplified to reproduce the output. The circuit is hence generating its own input signal, which means it is oscillating.

OBJECTIVE

1. To design, construct and test a RC phase shift oscillator of frequency _____ KHz. 2. To study the designed circuit and compare the experimental and calculated

results.

PROCEDURE

1. Design and construct the RC phase shift oscillator circuit in Fig. 7.1. 2. Connect an oscilloscope to the output node to monitor the output waveform. 3. Measure the output amplitude, frequency, and compare to the designed quantities. You are encouraged to modify the circuit for amplitude stabilization.

TABULATION


parameter Waveform


Volts div.

Amplitude Freq.

Voltage at output node

QUESTIONS

1. The RC feedback network in Fig. 7.1 gives a total phase shift of 180°. What is the phase shift due to each RC combination? Is it 60° each?

2. A sinusoid of a particular frequency can sustain itself in a closed loop that satisfies Barkhausen criteria. But how this sinusoid is produced in the first place?


CIRCUIT DIAGRAM

C

R4

R3

D2

D1

R2

R1

Fig. 8.1 Astable multivibrator

DESIGN


ASTABLE MULTIVIBRATOR USING OP-AMP

INTRODUCTION

An astable multivibrator is a circuit that is continuously switching its output voltage between high and low levels. It has no stable state. An astable multivibrator using an op-amp is shown in Fig. 8.1.The op-amp together with resistor R2 and R3 constitute an inverting Schmitt trigger circuit. The input voltage to the Schmitt circuit is the voltage across capacitor C1, which is charged and discharged from the op-amp output via resistor R1. The circuit is a square wave generator with an output that swings between the op-amp positive and negative saturation levels.

OBJECTIVE

1. To design, construct and test an Astable multivibrator of frequency _______KHz with a duty cycle of _____%.

2. To study the designed circuit and compare the experimental and calculated results.

PROCEDURE

1. Construct the astable multivibrator circuit shown in Fig. 8.1. 2. Connect a dual-trace oscilloscope to monitor the output and capacitor C1

waveforms. 3. Measure the output amplitude, frequency of the two waveforms and compare to

the designed quantities.

TABULATION


parameter Waveform


Volts div.

Amplitude Freq.

Voltage at output node A

Voltage across the

capacitor C1

TON ----- ----- ----- ----- -----

TOFF ----- ----- ----- ----- -----

TON: _______ TOFF: _______ Duty cycle: _______

QUESTION

1. What all factors restrict you from designing an astable multivibrator of 500 KHz frequency using IC 741?


CIRCUIT DIAGRAM

Vin

C2 C1

R2 R1

R4

R3 Vout

R4

R3

R2 R1

C2 C1 Vin

Vout

Fig. 9.1 Second order active low pass filter Fig. 9.2 Second order active high pass filter

DESIGN

Experiment 9 Date: _____________ SECOND ORDER ACTIVE LOW PASS AND HIGH PASS FILTERS

INTRODUCTION

An electric filter is a frequency selective circuit that has a desired gain and phase profile over a frequency range. In a low pass filter , the frequencies between 0 Hz and a high cutoff frequency (fh) experience a constant gain and are known as the pass band frequencies, whereas the range of frequencies, those beyond fh, that are attenuated includes the stop band frequencies. High pass filter is complementary to low pass filter. In high pass filter, frequencies below low cutoff frequency (fl) are attenuated and those beyond fl experience a constant gain. Order of the filter in the above considered cases determines the steepness of transition from stop band to pass band or vice versa.

OBJECTIVE

1. To design, construct and test an Active second order low pass filter with a high cutoff frequency fh of _______KHz.

2. To design, construct and test an Active second order high pass filter with a low cutoff frequency fl of _______KHz.

3. To study the designed circuits and compare the experimental and calculated cutoff frequencies and roll-off rates.

PROCEDURE

Low pass filter 1. Design and construct the second order low pass filter circuit shown in Fig. 9.1. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Vary the input frequency over a range and observe the output to establish the

general response of a low pass filter. Plot the frequency response. 4. Apply a 0.1 Vp-p sine wave input of a frequency, at least 10 times less than the

designed low cutoff frequency. Monitor the input and output waveforms on an oscilloscope.

5. Increase the signal frequency until the output amplitude falls to approximately 0.0707 Vp-p. Note the frequency and compare it to the designed cutoff frequency.

6. Double the signal frequency and measure the level of the output and calculate the rate of output roll-off.

High Pass Filter 1. Design and construct the second order high pass filter circuit shown in Fig. 9.2. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Vary the input frequency over a range and observe the output to establish the

general response of a high pass filter. Plot the frequency response.

4. Apply a 0.1 Vp-p sine wave input of a frequency, at least 10 times more than the designed high cutoff frequency. Monitor the input and output waveforms on an oscilloscope.

5. Reduce the signal frequency until the output amplitude falls to approximately 0.0707 Vp-p. Note the frequency and compare it to the designed cutoff frequency.

6. Half the signal frequency and measure the level of the output and calculate the rate of output roll-off.

7. Increase the signal frequency to discover the high cutoff frequency for the circuit. Compare it to the estimated high cutoff frequency.

You are encouraged to study the phase/frequency response of the designed second order active filters.

TABULATION

Second order low pass filter Input signal amplitude (Vin): 0.1 Vp-p

Output amplitude

(Vo) Frequency Gain in

dB

fh = _______ Roll-off rate: _______

Second order high pass filter Input signal amplitude (Vin): 0.1 Vp-p

Output amplitude

(Vo) Frequency Gain in

dB

fl = _____ fh = ______ Roll-off rate: _________

QUESTIONS

1. Ideal low-pass or high-pass filters with infinite roll-off and infinite attenuation in Stop-band cannot be realized physically. Why?

2. Why there is a high cutoff frequency for the active high pass filters, when no such cutoff frequency is there for passive high pass filters?


CIRCUIT DIAGRAM

Fig. 10.1 Sample-and-hold circuit

Input Output

E-MOSFET as switch

Control voltage

C

DESIGN

NOTES


SAMPLE-AND-HOLD CIRCUIT USING OP-AMP

INTRODUCTION

The sample-and-hold circuit, as its name implies, samples instantaneous amplitude of an input signal voltage and holds the voltage level constant until the next sample is acquired. In the circuit shown in Fig. 10.1 E-MOSFET (Enhancement MOSFET) works as a switch that is controlled by the sample-and-hold control voltage Vs, and the capacitor C serves as a storage element. The time period TS of the sample-and-hold control voltage Vs during which E-MOSFET is on and the voltage across the capacitor is equal to the input voltage, is called sample period or acquisition time. The time period TH of VS during which E-MOSFET is off and the voltage across the capacitor is constant is called hold period. Devices other than E-MOSFET can also be to act as an on-off switch.

OBJECTIVE

1. To design, construct and test a sample-and-hold circuit. 2. To study the designed circuit and establish the relationship between input, control

and output signal.

PROCEDURE

1. Design and construct the sample-and-hold circuit shown in Fig 10.1. Proper choice of capacitance value of C and on and off voltage levels of control signal is very crucial to the designing of sample-and-hold circuit.

2. Connect a storage oscilloscope to monitor the input, control and output waveforms.

3. Apply a 0.1 V, 1 KHz sinusoidal signal as the input. 4. Set the frequency of the control voltage to around 2 KHz (twice of the input

signal frequency). It is suggested to select a low value for the duty cycle of the control voltage signal.

5. Observe the output waveform and study its relationship with input and control voltage waveform. Draw the waveforms.

6. Increase the control signal frequency and observe the output waveform. 7. Repeat Procedures 4 through 6 for a different input waveform. You are

encouraged to choose a non sinusoidal waveform with different frequency and amplitude.


CIRCUIT DIAGRAMS

Fig. 11.1 Internal Block diagram of 555 timer

+VCC

C2

C1

R4 8

76

51

3

2

+VCC

C2

RA

RB

C1

78

6

51

3

2

4

Fig. 11.2 Circuit for monostable multivibrator Fig. 11.3 Circuit for astable multivibrator


MONOSTABLE AND ASTABLE MULTIVIBRATOR USING IC 555 TIMER

INTRODUCTION

A 555 timer is a versatile analog-digital integrated circuit. The IC is made of a combination of linear comparators and digital flip-flops as described in Fig. 11.1. A monostable multivibrator, often called a one-shot multivibrator, is a pulse generating circuit. A pulse of fixed, pre-determined duration is generated at the output in response to short lived trigger pulse at the input. The output stays low until the trigger pulse is applied. The monostable circuit has only one stable state (output low), hence the name monostable. An astable multivibrator, often called a free running multivibrator, is a rectangular wave generating circuit. Unlike monostable multivibrator, this circuit does not require an external trigger to change the state of the output, hence the name free-running. And since neither of its state (high or low) is stable, it is also called an astable multivibrator.

OBJECTIVE

1. To design, construct and test a monostable multivibrator using 555 timer. Pulse duration at the output should be ________ ms.

2. To design, construct and test an astable multivibrator using 555 timer, having a frequency of ________ KHz and a duty cycle of ______%.

3. To study the designed circuits and establish the relationship between input trigger (for monostable) and output waveforms.

PROCEDURE

Monostable multivibrator

1. Design and construct the circuit shown in Fig 11.2. 2. Connect a dual-trace oscilloscope to monitor the input trigger and output

waveform. 3. Apply a periodic trigger pulse to the circuit and observe the pulse duration at the

output. The pulse width of the trigger input must be smaller than the expected pulse width of the output waveform.

4. Adjust the frequency of the trigger pulse to a value, where not more than one trigger pulse is applied when the output is high. Measure the pulse amplitude and duration and note it down. Compare it with the calculated value.

5. Now increase the frequency of the input trigger pulse to show that there is no change in the output state for multiple triggers during a pulse period (output high).

DESIGN

Astable multivibrator 1. Construct the astable multivibrator circuit shown in Fig. 11.3. 2. Connect a dual-trace oscilloscope to monitor the voltage signal at the output pin

and capacitor C1. 3. Measure the output amplitude and frequency of the two waveforms and compare

to the designed quantities. Also note down the TON and TOFF for the rectangular waveform at the output pin and calculate the duty cycle.

TABULATION

Monostable Multivibrator



Timediv.

Volts div.

Amplitude Freq.

Input trigger voltage signal

Voltage at output pin

Output pulse duration -----

-----

----- ----- -----

Pulse duration: _______ Astable multivibrator



Timediv.

Volts div.

Amplitude Freq.

Voltage at output pin

Voltage across the

capacitor C1

TON ----- ----- ----- ----- -----

TOFF ----- ----- ----- ----- -----

TON: _______ TOFF: _______ Duty cycle: _______

QUESTIONS

1. What is the function of control pin (pin 5) in a 555 timer? Can you think of some applications where control pin is playing an active role instead of being left open or signal grounded?

2. What is the market price of a commercially available IC 555 timer? What are the major factors that decide the market price of an IC?


CIRCUIT DIAGRAM

5 6 5 VCO Output

Reference output

−Vcc

+ Vcc

R1

R2 C3

C2

C1

3

7 8 10

2 Input Demodulated output 6 4 5

9 1

Fig. 12.1 PLL circuit using IC 565-in range

DESIGN

Experiment 12 Date: _____________ MEASURMENT OF CAPTURE RANGE AND LOCK-IN RANGE OF

A PHASE LOCKED LOOP USING IC 565

INTRODUCTION

A typical Phase Locked Loop (PLL) consists of a Voltage Controlled Oscillator (VCO), a phase detector and a low pass filter. The PLL under normal conditions attempts to make the VCO output frequency exactly equal (also referred to as ‘lock’) to a second frequency that is applied to the PLL, the reference frequency. ‘Lock’ is achieved by feeding both the VCO output and the reference frequency into a phase detector. The phase detector compares the phase of the two waves, and outputs a pulsating DC waveform with a duty-cycle proportional to the phase difference between the two signals. The pulsating DC from the phase detector is fed into a low-pass filter before feeding it to the VCO input. Low pass filter ‘smoothes’ the rough phase detector output into a fairly steady DC voltage for the VCO. The output frequency of the VCO is directly proportional to a control voltage that is applied to its input terminal. A PLL has three operating states. These are the free-running, capture, and locked conditions. In the free-running state, there is no reference input frequency being provided to the PLL. Design constants within the system determine what frequency the VCO will run at. In the capture state, the PLL has just been given a reference frequency, and it is in the process of trying to ‘lock’ onto it. The PLL cannot lock onto all frequencies; only a certain range of frequencies, within the capture range can be locked onto, if the PLL is initially in the free-running state. In locked state, the PLL has its VCO accurately ‘locked’ onto the input reference frequency. The PLL cannot remain locked for all frequencies, and if the input reference frequency moves outside the lock-in range, the PLL will drop out of lock.

OBJECTIVE

1. To design, construct and test a Phase Locked Loop using IC 565. 2. To measure, capture range and lock-in range of the constructed PLL and compare

with calculated quantities.

PROCEDURE

1. Construct the circuit shown in Fig. 12.1, using a 10μF capacitor for C2. You can choose C3 to be 1 nF.

2. Connect an oscilloscope to monitor the waveform at the VCO output (pin 4 of IC 565).

3. Apply power to the circuit, but don’t apply a reference signal yet. Adjust R1 until the free-running output frequency of VCO is 1 KHz.

4. Connect an oscilloscope (use second channel) to monitor the input reference signal.

5. Apply the reference frequency to the reference input of the circuit.

DESIGN

6. Set the reference frequency to 600 Hz, approximately. Observe the two waveforms on the oscilloscope.

7. Slowly increase the frequency of the generator until the PLL just locks. Both the waveforms should appear stable in this ‘lock’ condition. Note this frequency. This frequency is the lower end of the capture range, fc(min).

8. Slowly increase the frequency until the PLL again drops out of lock. Note this frequency. This frequency is the upper end of the lock-in range, fl(max).

9. Slowly decrease the reference frequency until the PLL locks again. Note this frequency. This frequency is the upper end of the capture range fc(max).

10. Finally, decrease the reference frequency until the PLL drops out of the lock again. Note this frequency. This frequency is the lower end of the lock-in range, fl(min).Measure the input peak amplitude, calculate the voltage gain, and compare it to the designed gain.

11. Calculate capture range and lock-in range. Capture range = fc(max) – fc(min)Lock in range = fl(max) – fl(min)

12. Repeat Procedures 1 through 10 for a different free running frequency of PLL. You are encouraged to study the DC output from the low pass filter of PLL and comment on it, in three different operating conditions of the PLL.

TABULATION

Free running frequency: ___________ Observed parameter Observed value

fc(max) fc(min) fl(max) fl(min)

Capture range: __________ Lock-in range: __________

Free running frequency: ___________

Capture range: ___________ Lock-in-range: ___________

Observed parameter Observed valuefc(max) fc(min) fl(max) fl(min)

QUESTIONS

1. Lock-in range is more than the capture range for a PLL. Why? 2. Design a phase detector that gives an output voltage proportional to the phase

difference between two periodic digital signals.


TABLES

Device Type

Output Voltage (Vo)

Maximum input voltage (Vin)

7805 7806 7808 7812 7815 7818 7824

5.0 6.0 8.0 12.0 15.0 18.0 24.0

35 35 35 35 35 35 40

Device Type

Output Voltage (Vo)

Maximum input voltage (Vin)

7902 7905 7905.2 7906 7908 7912 7915 7918 7924

-2.0 -5.0 -5.2 -6.0 -8.0 -12.0 -15.0 -18.0 -24.0

-35 -35 -35 -35 -35 -35 -35 -35 -40

Table 13.1 78xx series voltage regulators Table 13.2 79xx series voltage regulators

CIRCUIT DIAGRAMS

Input 78XX 79XX

Fig. 13.1 Standard application of 78XX voltage regulator

Fig. 13.2 Standard application of 79XX voltage regulator

Output Input Output

C1

0.33 μF

C2

0.1 μF

C1

0.33 μF

C2

0.1 μF


VOLTAGE REGULATION USING 78XX AND 79XX

INTRODUCTION

A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load currents or line voltage. The 78xx series consists of three-terminal positive voltage regulators with seven voltage options (see Table 13.1). These IC’s are designed as fixed voltage regulators and with adequate heat sinking can deliver output currents in excess of 1 A. These IC’s also have internal thermal overload protection and internal short-circuit current limiting. The 79xx series of fixed output negative voltage regulators are complementary to the 78xx series devices. These negative voltage regulators are available in the same seven voltage options as the 78xx devices, In addition, two extra voltage options, -2V and -5.2 V. are also available (see Table 13.2).

OBJECTIVE

1. To test an 78xx IC for voltage regulation under various load conditions. 2. To test an 79xx IC for voltage regulation under various load conditions.

PROCEDURE

78xx positive voltage regulator

1. Construct the circuit shown in Fig 13.1. Use a DRB as load. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply the input signal. The input DC signal may or may not have ripples. But at

no point of time, the difference between the input and output voltages (Vin – Vout), should fall below the specified dropout voltage (Refer online

datasheet for the parameter’s value. Typical value is 2V). 4. Keep the input voltage constant and measure the output voltage for various load

conditions and note it down. Start with no load condition and increase the load (decrease the resistance) in suitable steps.

5. Keep a constant load and measure the output voltage for various levels of input voltage.

6. Calculate line regulation and load regulation using any two suitable readings. 79xx negative voltage regulator

1. Construct the circuit shown in Fig 13.2. Use a DRB as load. 2. Connect a dual-trace oscilloscope to monitor the input and output waveforms. 3. Apply the input signal. The input DC signal may or may not have ripples. But at

no point of time, the difference between the input and output voltages (Vin – Vout), should fall below the specified dropout voltage (Refer online datasheet for the parameter’s value. Typical value is -2V).

DESIGN

4. Keep the input voltage constant and measure the output voltage for various load conditions and note it down. Start with no load condition and increase the load (decrease the resistance) in suitable steps.

5. Keep a constant load and measure the output voltage for various levels of input voltage.

6. Calculate line regulation and load regulation using any two suitable readings.

TABULATION

78xx voltage regulator Load (RL): ________

Input voltage

Regulated output

Input voltage: ________

Load (RL) Regulated output

Line regulation: ____________ Load regulation: ____________

79xx voltage regulator Load (RL): ________

Input voltage

Regulated output

Input voltage: ________

Load (RL) Regulated output

Line regulation: ____________ Load regulation: ____________

QUESTION

1. 78XX and 79XX voltage regulators can also be used as a constant current source.

How and under what load conditions?


February 2007

©2LM

LM741 Single O

perational Am

plifier

LM741Single Operational AmplifierFeatures

Short Circuit ProtectionExcellent Temperature StabilityInternal Frequency CompensationHigh Input Voltage RangeNull of Offset

Description The LM741 series are general purpose operational amplifiers. It is intended for a wide range of analog applications. The high gain and wide range of operatingvoltage provide superior performance in intergrator, summing amplifier, and general feedback applications..

Ordering Information

Internal Block Diagram

8-DIP

1

8-SOP

1

Part NumberOperating Temp.

Range Pb-Free Package Packing MethodMarking

CodeLM741CN

0 ~ +70°CYES 8-DIP Rail LM741CN

LM741CM YES 8-SOP Rail LM741CMLM741CMX YES 8-SOP Tape & Reel LM741CM

8

7

6

5

1

2

3

4

NC

OUTPUT

VEE

IN1 (-)

IN1 (+)

VCC

OFFSETNULL

OFFSETNULL

007 Fairchild Semiconductor Corporation www.fairchildsemi.com741 Rev. 2.0.0

LM

LM741 Single O

perational Am

plifier

Schematic Diagram

Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Thedevice should not be operated at these limits. The parametric values defined in the Electrical Characteristics tablesare not guaranteed at the absolute maximum ratings. TA=25°C, unless otherwise specified.

Symbol Parameter Value UnitVCC Supply Voltage ±18 V

VI(DIFF) Differential Input Voltage 30 V

VI Input Voltage ±15 V

- Output Short Circuit Duration Indefinite -

PD Power Dissipation 500 mW

TOPR Operating Temperature Range 0 ~ +70 °C

TSTG Storage Temperature Range -65 ~ +150 °C

Q1 Q2

Q3 Q4

Q5 Q6

Q7

Q8 Q9

Q10 Q11

Q12 Q13Q14

Q15

Q16

Q17

Q18

Q19

Q20

Q21

Q22 Q24

Q23

R1 R2R3 R4

R5

R6

R7

R8R9

R10

R11

R12

C1

VCC

OUTPUT

VEE

IN (+)

IN (-)

OFFSETNULL

2 www.fairchildsemi.com741 Rev. 2.0.0

LM

LM741 Single O

perational Am

plifier

Electrical Characteristics(VCC = 15V, VEE = -15V, TA = 25°C, unless otherwise specified)

Note:1. Guaranteed by design.

Parameter Symbol Conditions Min. Typ. Max. UnitInput Offset Voltage

VIORS ≤ 10kΩ - 2.0 6.0

mVRS ≤ 50Ω - - -

Input Offset VoltageAdjustment Range VIO(R)

VCC = ±20V - ±15 - mV

Input Offset Current IIO - - 20 200 nA

Input Bias Current IBIAS - - 80 500 nA

Input Resistance (Note1) RI VCC = ±20V 0.3 2.0 - MΩ

Input Voltage Range VI(R) - ±12 ±13 - V

Large Signal Voltage Gain

GV

RL ≥ 2kΩ VCC = ±20V,VO(P-P) = ±15V - - -

V/mVVCC = ±15V,VO(P-P) = ±10V 20 200 -

Output Short Circuit Current ISC - - 25 - mA

Output Voltage Swing

VO(P-P)

VCC = ±20V RL ≥ 10kΩ - - -

VRL ≥ 2kΩ - - -

VCC = ±15V RL ≥ 10kΩ ±12 ±14 -

RL ≥ 2kΩ ±10 ±13 -

Common Mode Rejection Ratio CMRR

RS ≤ 10kΩ, VCM = ±12V 70 90 -dB

RS ≤ 50Ω, VCM = ±12V - - -

Power Supply Rejection Ratio

PSRR

VCC = ±15V to VCC = ±15VRS ≤ 50Ω

- - -dB

VCC = ±15V to VCC = ±15VRS ≤ 10kΩ

77 96 -

Transient Rise Time TR Unity Gain - 0.3 - µs

Response Overshoot OS - 10 - %

Bandwidth BW - - - - MHz

Slew Rate SR Unity Gain - 0.5 - V/µs

Supply Current ICC RL= ∞Ω - 1.5 2.8 mA

Power Consumption PC

VCC = ±20V - - -mW

VCC = ±15V - 50 85


LM

LM741 Single O

perational Am

plifier

Electrical Characteristics (Continued)

( 0°C ≤ TA ≤ 70 °C, VCC = ±15V, unless otherwise specified)The following specification apply over the range of 0°C ≤ TA ≤ +70°C for the LM741C

Note :1. Guaranteed by design.

Parameter Symbol Conditions Min. Typ. Max. UnitInput Offset Voltage VIO RS ≤ 50Ω - - -

mVRS ≤ 10kΩ - - 7.5

Input Offset Voltage Drift ∆VIO/∆T - - - µV/°C

Input Offset Current IIO - - - 300 nA

Input Offset Current Drift ∆IIO/∆T - - - nA/°C

Input Bias Current IBIAS - - - 0.8 µA

Input Resistance (Note1) RI VCC = ±20V - - - MΩ

Input Voltage Range VI(R) - ±12 ±13 - V

Output Voltage Swing VO(P-P) VCC =±20V RS ≥ 10kΩ - - -

VRS ≥ 2kΩ - - -

VCC =±15V RS ≥ 10kΩ ±12 ±14 -

RS ≥ 2kΩ ±10 ±13 -

Output Short Circuit Current ISC - 10 - 40 mA

Common Mode Rejection Ratio CMRR RS ≤ 10kΩ, VCM = ±12V 70 90 -dB

RS ≤ 50Ω, VCM = ±12V - - -

Power Supply Rejection Ratio PSRR VCC = ±20V to±5V

RS ≤ 50Ω - - -dB

RS ≤ 10kΩ 77 96 -

Large Signal Voltage Gain GV RS ≥ 2kΩ VCC = ±20V,VO(P-P) = ±15V - - -

V/mVVCC = ±15V,VO(P.P) = ±10V 15 - -

VCC = ±15V,VO(P-P) = ±2V - - -


LM

LM741 Single O

perational Am

plifier

Typical Performance Characteristics

Figure 1. Output Resistance vs Frequency Figure 2. Input Resistance and Input Capacitance vs Frequency

Figure 3. Input Bias Current vs Ambient Temperature

Figure 4. Power Consumption vs Ambient Temperature

Figure 5. Input Offset Current vs Ambient Temperature

Figure 6. Input Resistance vs Ambient Temperature


LM

LM741 Single O

perational Am

plifier

Typical Performance Characteristics (Continued)

Figure 7. Normalized DC Parameters vs Ambient Temperature

Figure 8. Frequency Characteristics vs Ambient Temperature

Figure 9. Frequency Characteristics vs Supply Voltage

Figure 10. Output Short Circuit Current vs Ambient Temperature

Figure 11. Transient Response Figure 12. Common-Mode Rejection Ratiovs Frequency


7 www.fairchildsemi.comLM741 Rev. 2.0.0

LM741 Single O

perational Am

plifier


Figure 1. Voltage Follower Large Signal Pulse Response

Figure 2. Output Swing and Input Range vs Supply Voltage

LM555TimerGeneral DescriptionThe LM555 is a highly stable device for generating accuratetime delays or oscillation. Additional terminals are providedfor triggering or resetting if desired. In the time delay mode ofoperation, the time is precisely controlled by one external re-sistor and capacitor. For astable operation as an oscillator,the free running frequency and duty cycle are accuratelycontrolled with two external resistors and one capacitor. Thecircuit may be triggered and reset on falling waveforms, andthe output circuit can source or sink up to 200mA or driveTTL circuits.

Featuresn Direct replacement for SE555/NE555n Timing from microseconds through hoursn Operates in both astable and monostable modesn Adjustable duty cyclen Output can source or sink 200 mAn Output and supply TTL compatiblen Temperature stability better than 0.005% per ˚Cn Normally on and normally off outputn Available in 8-pin MSOP package

Applicationsn Precision timingn Pulse generationn Sequential timingn Time delay generationn Pulse width modulationn Pulse position modulationn Linear ramp generator

Schematic Diagram

DS007851-1

February 2000LM

555Tim

er

© 2000 National Semiconductor Corporation DS007851 www.national.com

Connection Diagram

Ordering InformationPackage Part Number Package Marking Media Transport NSC Drawing

8-Pin SOIC LM555CM LM555CM RailsM08A

LM555CMX LM555CM 2.5k Units Tape and Reel

8-Pin MSOP LM555CMM Z55 1k Units Tape and ReelMUA08A

LM555CMMX Z55 3.5k Units Tape and Reel

8-Pin MDIP LM555CN LM555CN Rails N08E

Dual-In-Line, Small Outlineand Molded Mini Small Outline Packages

DS007851-3

Top View

LM55

5

www.national.com 2

Absolute Maximum Ratings (Note 2)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage +18VPower Dissipation (Note 3)

LM555CM, LM555CN 1180 mWLM555CMM 613 mW

Operating Temperature RangesLM555C 0˚C to +70˚C

Storage Temperature Range −65˚C to +150˚C

Soldering InformationDual-In-Line Package

Soldering (10 Seconds) 260˚CSmall Outline Packages

(SOIC and MSOP)Vapor Phase (60 Seconds) 215˚CInfrared (15 Seconds) 220˚C

See AN-450 “Surface Mounting Methods and Their Effecton Product Reliability” for other methods of solderingsurface mount devices.

Electrical Characteristics (Notes 1, 2)(TA = 25˚C, VCC = +5V to +15V, unless othewise specified)

Parameter Conditions Limits Units

LM555C

Min Typ Max

Supply Voltage 4.5 16 V

Supply Current VCC = 5V, RL = ∞VCC = 15V, RL = ∞(Low State) (Note 4)

310

615 mA

Timing Error, Monostable

Initial Accuracy 1 %

Drift with Temperature RA = 1k to 100kΩ, 50 ppm/˚C

C = 0.1µF, (Note 5)

Accuracy over Temperature 1.5 %

Drift with Supply 0.1 %/V

Timing Error, Astable

Initial Accuracy 2.25 %

Drift with Temperature RA, RB = 1k to 100kΩ, 150 ppm/˚C

C = 0.1µF, (Note 5)

Accuracy over Temperature 3.0 %

Drift with Supply 0.30 %/V

Threshold Voltage 0.667 x VCC

Trigger Voltage VCC = 15V 5 V

VCC = 5V 1.67 V

Trigger Current 0.5 0.9 µA

Reset Voltage 0.4 0.5 1 V

Reset Current 0.1 0.4 mA

Threshold Current (Note 6) 0.1 0.25 µA

Control Voltage Level VCC = 15VVCC = 5V

92.6

103.33

114

V

Pin 7 Leakage Output High 1 100 nA

Pin 7 Sat (Note 7)

Output Low VCC = 15V, I7 = 15mA 180 mV

Output Low VCC = 4.5V, I7 = 4.5mA 80 200 mV

LM555

www.national.com3

Electrical Characteristics (Notes 1, 2) (Continued)

(TA = 25˚C, VCC = +5V to +15V, unless othewise specified)

Parameter Conditions Limits Units

LM555C

Min Typ Max

Output Voltage Drop (Low) VCC = 15V

ISINK = 10mA 0.1 0.25 V

ISINK = 50mA 0.4 0.75 V

ISINK = 100mA 2 2.5 V

ISINK = 200mA 2.5 V

VCC = 5V

ISINK = 8mA V

ISINK = 5mA 0.25 0.35 V

Output Voltage Drop (High) ISOURCE = 200mA, VCC = 15V 12.5 V

ISOURCE = 100mA, VCC = 15V 12.75 13.3 V

VCC = 5V 2.75 3.3 V

Rise Time of Output 100 ns

Fall Time of Output 100 ns

Note 1: All voltages are measured with respect to the ground pin, unless otherwise specified.

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-tional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar-antee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit isgiven, however, the typical value is a good indication of device performance.

Note 3: For operating at elevated temperatures the device must be derated above 25˚C based on a +150˚C maximum junction temperature and a thermal resistanceof 106˚C/W (DIP), 170˚C/W (S0-8), and 204˚C/W (MSOP) junction to ambient.

Note 4: Supply current when output high typically 1 mA less at VCC = 5V.

Note 5: Tested at VCC = 5V and VCC = 15V.

Note 6: This will determine the maximum value of RA + RB for 15V operation. The maximum total (RA + RB) is 20MΩ.

Note 7: No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.

Note 8: Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.

LM55

5

www.national.com 4


Minimuim Pulse WidthRequired for Triggering

DS007851-4

Supply Current vs.Supply Voltage

DS007851-19

High Output Voltage vs.Output Source Current

DS007851-20

Low Output Voltage vs.Output Sink Current

DS007851-21


DS007851-22


DS007851-23

LM555

www.national.com5


Output Propagation Delay vs.Voltage Level of Trigger Pulse

DS007851-24

Output Propagation Delay vs.Voltage Level of Trigger Pulse

DS007851-25

Discharge Transistor (Pin 7)Voltage vs. Sink Current

DS007851-26

Discharge Transistor (Pin 7)Voltage vs. Sink Current

DS007851-27

LM55

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LM565/LM565CPhase Locked LoopGeneral DescriptionThe LM565 and LM565C are general purpose phase lockedloops containing a stable, highly linear voltage controlled os-cillator for low distortion FM demodulation, and a double bal-anced phase detector with good carrier suppression. TheVCO frequency is set with an external resistor and capacitor,and a tuning range of 10:1 can be obtained with the samecapacitor. The characteristics of the closed loopsystem — bandwidth, response speed, capture and pull inrange — may be adjusted over a wide range with an externalresistor and capacitor. The loop may be broken between theVCO and the phase detector for insertion of a digital fre-quency divider to obtain frequency multiplication.

The LM565H is specified for operation over the −55˚C to+125˚C military temperature range. The LM565CN is speci-fied for operation over the 0˚C to +70˚C temperature range.

Featuresn 200 ppm/˚C frequency stability of the VCOn Power supply range of ±5 to ±12 volts with 100 ppm/%

typical

n 0.2% linearity of demodulated outputn Linear triangle wave with in phase zero crossings

availablen TTL and DTL compatible phase detector input and

square wave outputn Adjustable hold in range from ±1% to > ±60%

Applicationsn Data and tape synchronizationn Modemsn FSK demodulationn FM demodulationn Frequency synthesizern Tone decodingn Frequency multiplication and divisionn SCA demodulatorsn Telemetry receiversn Signal regenerationn Coherent demodulators

Connection Diagrams

Metal Can Package

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Order Number LM565HSee NS Package Number H10C

Dual-in-Line Package

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Order Number LM565CNSee NS Package Number N14A

May 1999

LM565/LM

565CP

haseLocked

Loop

© 1999 National Semiconductor Corporation DS007853 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage ±12VPower Dissipation (Note 2) 1400 mWDifferential Input Voltage ±1V

Operating Temperature RangeLM565H −55˚C to +125˚CLM565CN 0˚C to +70˚C

Storage Temperature Range −65˚C to +150˚CLead Temperature

(Soldering, 10 sec.) 260˚C

Electrical CharacteristicsAC Test Circuit, TA = 25˚C, VCC = ±6V

Parameter ConditionsLM565 LM565C

UnitsMin Typ Max Min Typ Max

Power Supply Current 8.0 12.5 8.0 12.5 mA

Input Impedance (Pins 2, 3) −4V < V2, V3 < 0V 7 10 5 kΩVCO Maximum OperatingFrequency

Co = 2.7 pF300 500 250 500 kHz

VCO Free-Running Frequency Co = 1.5 nFRo = 20 kΩfo = 10 kHz

−10 0 +10 −30 0 +30 %

Operating FrequencyTemperature Coefficient

−100 −200 ppm/˚C

Frequency Drift withSupply Voltage

0.1 1.0 0.2 1.5 %/V

Triangle Wave Output Voltage 2 2.4 3 2 2.4 3 Vp-p

Triangle Wave Output Linearity 0.2 0.5 %

Square Wave Output Level 4.7 5.4 4.7 5.4 Vp-p

Output Impedance (Pin 4) 5 5 kΩSquare Wave Duty Cycle 45 50 55 40 50 60 %

Square Wave Rise Time 20 20 ns

Square Wave Fall Time 50 50 ns

Output Current Sink (Pin 4) 0.6 1 0.6 1 mA

VCO Sensitivity fo = 10 kHz 6600 6600 Hz/V

Demodulated Output Voltage(Pin 7)

±10% Frequency Deviation250 300 400 200 300 450 mVp-p

Total Harmonic Distortion ±10% Frequency Deviation 0.2 0.75 0.2 1.5 %

Output Impedance (Pin 7) 3.5 3.5 kΩDC Level (Pin 7) 4.25 4.5 4.75 4.0 4.5 5.0 V

Output Offset Voltage|V7 − V6|

30 100 50 200 mV

Temperature Drift of |V7 − V6| 500 500 µV/˚C

AM Rejection 30 40 40 dB

Phase Detector Sensitivity KD 0.68 0.68 V/radian

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-tional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guar-antee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit isgiven, however, the typical value is a good indication of device performance.

Note 2: The maximum junction temperature of the LM565 and LM565C is +150˚C. For operation at elevated temperatures, devices in the TO-5 package must bederated based on a thermal resistance of +150˚C/W junction to ambient or +45˚C/W junction to case. Thermal resistance of the dual-in-line package is +85˚C/W.

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Power Supply Current as aFunction of Supply Voltage

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Lock Range as a Functionof Input Voltage

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VCO Frequency

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Oscillator OutputWaveforms

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Phase Shift vs Frequency

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VCO Frequency as aFunction of Temperature

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Loop Gain vs LoadResistance

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Hold in Range as aFunction of R 6–7

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Schematic Diagram

DS

0078

53-1

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LIC Lab Manual

Documents

Transcript of LIC Lab Manual