LHCb upgrade Electronics Architecture Review General Architecture & Front-end
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Transcript of LHCb upgrade Electronics Architecture Review General Architecture & Front-end
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1Ken Wyllie, CERN Architecture Review, 5th Dec 2012
LHCb upgrade
Electronics Architecture Review
General Architecture & Front-end
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Architecture Review, 5th Dec 20122Ken Wyllie, CERN
HLT
Current
HLT++
Upgrade
1MHzeventrate
40MHzeventrate
Readout Supervisor
L0 Hardware Trigger
Readout Supervisor
Low-level Trigger
Electronics architecture
Front-end electronics: transmit data from every 25ns BX
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Architecture Review, 5th Dec 20123Ken Wyllie, CERN
Electronics architecture
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Architecture Review, 5th Dec 20124Ken Wyllie, CERN
FE
DAQ network
100 m rock
BE modules
Compute Units
‘CLASSICAL’ view from Niko
GBT: custom radiation- hard link over MMF, 3.2 Gbit/s (about 10000)
Input into DAQ network (10/40 Gigabit Ethernet or Infiniband)
(1000 to 4000) Output from DAQ network into
compute unit clusters (100 Gbit Ethernet / EDR IB) (200 to 400 links)
Electronics with DAQ
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Architecture Review, 5th Dec 20125Ken Wyllie, CERN
General architecture:highlights & open issues
Adopted generic link for FEGBT chipset + Versatile Link (VL) optics
All BE hardware will be common (carrierboard + AMCs)TELL40 for dataFE TFC/ECS interface (SOL40)TFCLLT interface
(more from Jean-Pierre)
ATCA baseline technology
Location of TELL40 + switch not yet decided (pit or surface)
Long distance transmission with VL under study
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Architecture Review, 5th Dec 20126Ken Wyllie, CERN
Details of FE architecture
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Architecture Review, 5th Dec 20127Ken Wyllie, CERN
Sub-detector specific blocks 1
Data compressionDriven by cost (minimise links)Zero-suppression => clear advantage in low occupancy detectorsBUT some have high occupancy => no ZS, buy linksCompression recipes vary: little common overlap
FE bufferUse link bandwidth efficientlyRiskiest part of system (eg unforeseen background fills up
bandwidth)Sub-detectors must make best estimate from
simulationsuse safety factormake system scale-able?
If buffer overflow => truncation of payload data
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Architecture Review, 5th Dec 20128Ken Wyllie, CERN
Sub-detector specific blocks 2
Non-ZS dataRequested by some sub-detectors (for tuning/diagnostics)Send as part of normal data stream (controlled by TFC)Buffering implications to be understood
BXIDData tagged with BXID earlyBXID reset is main tool for overall synchronisationAll synch-checks, event building, LLT based on BXIDTune-able preset of BXID counterBXID is ALWAYS transmitted as part of header
(even during truncation)
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Architecture Review, 5th Dec 20129Ken Wyllie, CERN
Sub-detector specific blocks 3
Fast commands from TFC (see Federico)Pre-delayed to match transmission latencyResets & other special fast commandsStoring instantaneous state of FE (then read thru ECS)
Running modesConfigured by ECS (ie not on-the-fly)Diagnostic patterns for measuring link latencies
Test featuresElectrical pulse, triggered light source, cosmicsDigital patterns generated by FE
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Architecture Review, 5th Dec 201210Ken Wyllie, CERN
Generic Sub-Detector Readout & Control
Common Electronics
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Architecture Review, 5th Dec 201211Ken Wyllie, CERN
FEC formatOrwideBus
FEC format
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Architecture Review, 5th Dec 201212Ken Wyllie, CERN
Common items 1
GBTXGood contact with design teamBut schedule is a worryPrototypes not yet available
GBT-SCASchedule not clear yet: worryPrototypes not yet available
Versatile LinkProposed schedule OK for LHCb (2014 –
2015)Prototypes available
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Architecture Review, 5th Dec 201213Ken Wyllie, CERN
Common items 2
DC-DCTests done with prototypes: successfulLHCb deciding on flavours & quantitiesCan we start producing in 2013?
Low Voltage Power SuppliesPlan is to re-use existing systemsEstimated quantities of new purchases are
small…… but obsolescence ……..
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Architecture Review, 5th Dec 201214Ken Wyllie, CERN
Spare slidesSub-detector details
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Architecture Review, 5th Dec 201215Ken Wyllie, CERN
VELO pixel
VeloPix chip: 256 x 256 array, 55 x 55 mm pixels•Strong overlap with TimePix3 (under design)•3 or 4 bits TOT•Architecture to minimise bandwidth (hottest chip = 12
Gbit/s)•Serial readout
A A
A A
A A
A A
Super pixelDigital
A A
A A
A A
A A
220 um
220
um
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Architecture Review, 5th Dec 201216Ken Wyllie, CERN
VELO strips & Silicon Tracker
SALT ASIC under design128-channels, each with 6-bit ADCOn-chip data compression planned
(pedestal subtraction, common-mode correction)
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Architecture Review, 5th Dec 201217Ken Wyllie, CERN
Tracker
SciFi tracker
Fibres coupled to SiPMSiPM Radiation tolerance?
ASIC design starting SiPM array SiPM cell coverage
LHCC upgrade session, 16th February 2010Re
-use
R
epla
ce
Outer trackerRe-use front end
Implement TDC (1ns) in ACTEL ProASIC FPGA: prototype already working
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Architecture Review, 5th Dec 201218Ken Wyllie, CERN
RICH Calorimeter
MaPMT (baseline) option
CLARO ASIC under design:
•Gain compensation•Binary output
Digital functions in ACTEL
MaPMT gain reductionÞReduce electronics noiseÞActive termination in ASIC (à la ATLAS LAr)
Interleaved integrators
ICECAL in AMS 0.35mm SiGe
Muons40MHz data transmission already – re-use
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Architecture Review, 5th Dec 201219Ken Wyllie, CERN
Common developments
ACTEL Flash FPGA for front-end modules•Advantages over ASICs: re-programmable!!!
•Can they survive the radiation…..?
•Irradiation programme on-going on A3PE1500
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Architecture Review, 5th Dec 201220Ken Wyllie, CERN
BCnt
Synchroniser
Constant latency
logic
Delay line = 24 x 16 x 3 bitsTFC command
24
TFC filterRaw data
delay1delay2
delay16
Non-Constant latency
logic
Link
Preset ECS
BXID reset