Lg 37lc2r 42lc2r 32lb1r 37lb1r 42lb1r Hurricane3 High Chassis Guide Training [ET][1]

Great Company Great People Blue Ocean P³ Innovation-1/53-

Table of contents

Hurricane3 High chassis guide

Great Company Great People

2006.05.03DDC PA Gr

1. Specification

2. Block Diagram

3. Trouble Shooting

4. Debugging Method

5. Adjustment UI Specification

6. Document


Model Concept

• New XD Engine • 10 Bit• HDMI• 3D Surround (Royalty Free)• 1Tuner(EU), 2Tuner(Non-EU)• AV Input Navigation• Stand-by Power consumption 1W• On Screen Equalizer

• Clear Filter• Brightness : 1,200 ㏅/㎡• Contrast : 10,000 : 1 • ASIC : 4025적용

42PC1R 37LC2R

• Brightness : 500 ㏅/㎡• Contrast : 1600 : 1 • View Angle : 178 ˚

DesignDesign

FeatureFeature

ModuleModule

H&CH&C 2 Tone 2 Tone


LC2

PC1/PC3

▶▶ PB2 Tool(Better High) All H&CPB2 Tool(Better High) All H&C

▶▶ LB2 Tool(Better High) All H&CLB2 Tool(Better High) All H&C

구분

H & C

2 Tone

26” 32” 37” 42”

PB2

LB2

Type

H & C

42X 50X

●●

Model Concept

Tool line up


2-Tuner

N-EU

E/C/F/G/S

/Arab/Parsi

Multi

16.7 Mil

178˚Min

1200:1

500

1366X768

(WXGA)

940.3

0.2 × 0.6

16:9

37LB1R-TH

2-Tuner

N-EU

E/C/F/G/S

/Arab/Parsi

Multi

16.7 Mil

178˚Min

1200:1

500

1366X768

(WXGA)

1067.3

0.227 ×0.681

16:9

42LC2R-TH

2-Tuner

N-EU

E/C/F/G/S

/Arab/Parsi

Multi

16.7 Mil

178˚Min

1200:1

500

1366X768

(WXGA)

800.4

0.17 × 0.51

16:9

32LB1R-TH

V

I

D

E

O

2-Tuner1-Tuner2-Tuner1-TunerRemark

N-EUEUN-EUEUMarket place

E/C/F/G/S

/Arab/Parsi

E/F/G/S/I/SW/N/D

E/C/F/G/S

/Arab/Parsi

E/F/G/S/I/

SW/N/D

OSD Language

PAL

16.7 Mil

178˚Min

1200:1

500

1366X768

(WXGA)

1067.3

0.227 × 0.681

16:9

42LC2R-ZH

MultiMultiPALInput Signal

16.7 Mil16.7 Mil16.7 MilColor(R,G,B)

178˚Min178˚Min178˚MinView Angle

1200:11200:11200:1Contrast Ratio

500500500Luminance (cd/㎡)

1366X768

(WXGA)

1366X768

(WXGA)

1366X768

(WXGA)

Resoultion

1067.3940.3940.3Screen size(mm)

0.227 ×0.6810.2 × 0.60.2 × 0.6Cell Pitch(mm)

16:916:916:9Aspect Ratio

42LB1R-TH 37LC2R-TH37LC2R-ZHModel

Model Specification


1111111RGB Input

1111111RS-232C

22.6

911.4×599

×259

140

110-240V 50/60Hz

1

1

1

2

2

1

2

1

32LB1R-TH

31.6

1045.8×693.8

×260.4

190

110-240V 50/60Hz

1

1

1

2

2

1

2

1

37LB1R-TH

42.3

1054×813

×286

230

110-240V 50/60Hz

1

1

1

2

1

1

2

1

42LC2R-TH

AC Input

J

A

C

K

41.442.335.535.5Weight with Packing(kg)

1175×768×300

1054×813×286

944×729

×286

944×729

×286

SIZE (W x H x D) (mm)

:with stand

230

110-240V 50/60Hz

1

1

1

1

1

1

4

1

42LC2R-ZH

230190190Power Consumption

110-240V 50/60Hz

110-240V 50/60Hz

110-240V

50/60Hz

111Remote control

111PC Audio In

111Variable

Audio out

221Component Input(Y,Pb,Pr)

211S-Video in

111Monitor out

224AV in

111RF In

42LB1R-TH 37LC2R-TH37LC2R-ZHModel

Model Specification


2-Tuner

N-EU

10000:1

(1% full white window

in dark room)

280(400)

1366X768

(WXGA)

270(um) ×810(um)

16:9

50PC1R-TH

1-Tuner

EU

10000:1


in dark room)

340(540)

1024X768

(XGA)

270(um)

× 810(um)

16:9

42PC3R-ZH

2-Tuner

EU

10000:1


in dark room)

280(400)

1366X768

(WXGA)

270(um) ×810(um)

16:9

50PC1R-ZH

V

I

D

E

O

1-Tuner1-Tuner1-Tuner1-TunerRemark

ChinaChinaN-EUEUMarket place

10000:1


in dark room)

340/ 540)

1024X768

(XGA)

300(um) ×676(um)

16:9

42PC1R-CH

10000:1


in dark room)

10000:1


in darkroom)

10000:1


in dark room)

Contrast Ratio

280(400)340 / 540 340 /540 Peak White

/special (cd/㎡)

1366X768

(WXGA)

1024X768

(XGA)

1024X768

(XGA)

Resolution

270(um) ×810(um)

300(um) ×676(um)

300(um) ×676(um)

Cell Pitch

16:916:916:9Aspect Ratio

50PC1R-CH42PC1R-TH42PC1R-ZHModel

Model Specification


1111111RGB Input

1111111RS-232C

51.5

1302.6×872

×355.8

430

110-240V 50/60Hz

1

1

1

1

1

1

4

1

50PC1R-ZH

51.5

1302.6×872

×355.8

430

110-240V 50/60Hz

1

1

1

2

1

1

2

1

50PC1R-TH

31.3

1129×748.5

×336.6

330

110-240V 50/60Hz

1

1

1

2

1

1

3

1

42PC3R-ZH

AC Input

J

A

C

K

51.529.329.329.3Weight with Packing(kg)

1302.6×872

×355.8

1129×748.5

×380

1129×748.5

×380

1129×748.5

×380

SIZE (W x H x D) (mm)

:with stand

330

110-240V 50/60Hz

1

1

1

2

1

1

2

1

42PC1R-CH

430330330Power Consumption

110-240V 50/60Hz

110-240V 50/60Hz

110-240V

50/60Hz

111Remote control

111PC Audio In

111Variable

Audio out

221Component Input(Y,Pb,Pr)

111S-Video in

111Monitor out

224AV in

111RF In

50PC1R-CH42PC1R-TH42PC1R-ZHModel

Model Specification


Main Feature Compare with H2

Platform Version Up (H2→H3)Platform Version Up (H2→H3)

• LCD Board & PDP Board is different

à Same PCB Board (With option)

• Main/Sub IC is separate

à Main/Sub Picture IC were merging

(Only One Main IC : XD8662)

• Support DMS Full process(Productivity will be very higher thenprevious model)

• Sub Picture 3D Comb Filter

• 8Bit à10 Bit Signal Processing

(Decoder, ADC, de-interlacer, Output)

• New XD Engine

-. Adaptive NR

-. No noise boosting Sharpness

-. Sub Picture Y/C Separate Sharpness

Control

• Blue-tone stretch (Only White region)

New Feature of PDP ModuleNew Feature of PDP Module

Added features in circuitAdded features in circuit

Improved Function from H2Improved Function from H2

ProductivityProductivity

• Decrease the reflection of eternal light

-> increase the clarity and contrast

(XGA Grade extended)

• 10 Bit Input and Processing

• Adopt Low Contour noise Algorithm


H3 High Whole Block Diagram

HDMI_DATA

HDMI_CLK/DE

HDMI_IIS

HDMI_VS/HS

HDMI_DATA : 3.3VHDMI_CLK/DE : 3.3V

HDMI_IIS : 3.3VHDMI_VS/HS : 3.3V

Variable_audio_out L/R : 500mVrms

TX

ST3232CTx/Rx : ±15Vpp

74HC14

DSUB_SCL / DSBU_SDA

DS_VS / DS_HS

PC_Audio_L/R : 700mVrms

PC_Audio_L/R

TU_MAIN : 1Vpp

TU_SUB : 1Vpp

S I FAM_Audio

AM_Audio / S I F

MNT_OUT : 1Vpp

AV3_SW/S3_SW

COMP1,2_RIN/LIN

TV_L/R OUT : 500mVrms

VIN4/YIN4/CIN4 : 1/0.285Vpp

LIN4/RIN4 : 500mVrms

AV_LOUT/ROUT

SUB_V : 2Vpp

MAIN_V or Y/C OUT : 2Vpp

OUTPUT31P_LVDS

K4D261638F-LC50X2DDRRAM(128MB X2)

AT49BV160CF-ROM(2MB)

L_CH

R_CH

L_SPK_OUT

R_SPK_OUT

24C02

I2C

Variable_audio_out L/R

SCL/SDA

SCART2_ID

Comp_SW

Comp2_SW

Comp_L/R : 500mVrms

Comp2_L/R : 500mVrms

TUNER(SUB)

TUNER(MAIN)

유선IR

RS232

RGB_PCRGB_DTV

PC_Audio

RF

COMP

Rear AV (AV3)

VariableAudio_out

HDMI1/2

COMP2

MNT_OUT

Scart1

(TV_out)

Scart2

(MNT_OUT)

24C02

HDMI RxANX9021

VIN3/YIN3/CIN3 : 1/0.285Vpp

SCART1_ID

SCART1_VIN : 1Vpp

SCART1_LIN/RIN : 500mVrms

SCART2_ID SCART2_LIN/RIN : 500mVrms Audio S/W

& CONTROLMSP4450K

Comp_SW

SCART1_FB

SCART1_ID

Comp2_SW

SCART1,2_LIN/RIN

LIN3/RIN3 : 500mVrms

AV4_SW/S4_SW

MAIN SCALER XD8662

TXD /RXD : 5V Digital

VGA_RGB : 0.7Vpp

COMP_Y/Pb/Pr : 1/0.7Vpp

AIP_RAW_VS / AIP_RAW_HS_CS : 5V High/Low

COMP2_Y/Pb/Pr : 1/0.7VppSCART1_RGB : 0.7Vpp

IR

CN_IIS MC_IIS

PWMNTP2000H

AMPTAS5122

I2 C

I2 C

I2C

I2C AV SWITCHCXA2069Q

MNT_OUT MNT_LOUT/ROUT

SCART2_VIN/YIN/CIN : 1/0.285Vpp

I2 C I2 C

MNT_LOUT/ROUT : 500mVrms

Tx0/1/2/3/4/C±DISP_EN

SCL/SDA_Part

I2S (SCK/WCK/DATA)

Video Signal

Audio Signal


Main Scaler(XD8668) Features


Main Scaler(XD8668) Block Diagram

• The FLI8668 chip has a flexible Analog Front End (AFE) with 13 configurable inputs through an analog multiplexer before the Analog to Digital Converters (ADCs).

• It also contains an embedded Multi-Standard Video Decoder. This decoder contains a digital comb filter for optimum Y/C separation. A 3D comb filter is available for optimum Y/C separation, that reduces or eliminates any artifacts due to poor Y/C separation seen on standard 2D video decoders on composite inputs, most commonly found on TV tuners.

• The FLI8668 microprocessor can process a wide range of Vertical Blanking Interval (VBI) data and display this data with the bitmap OSD processor. The microprocessor can support VBI data processing in the Main or PIP channels as well as in the background when the corresponding video stream is not present on the output stream. The VBI dataslicer can extract data encoded into the VBI of the input video stream. Decoded data bytes from the VBI dataslicerare stored in a memory buffer for subsequent processing by the microprocessor. The microprocessor decodes the different formats of the VBI data and passes the information to the OSD controller for output to the display controller. The VBI decoding process can run continuously in the background for inputs that contain VBI data.


Main Scaler(FLI8668) Block Diagram Explanation

• The Digital Input Port is a 48-bit data input with flexible configuration to support a wide range of digital sources. It consists of two 24-bit ports (PORTA and PORTB),two sets of control signals (VS,HS,ODD,etc.), and 4 input clocks. Up to 4 different inputs are supported as long as at least 2 of these inputs are 8-bit CCIR656. The digital input port can also be configured to support one 30-bit input with a second 16-bit input port. Bit 7 to 0 of PORTA can be configured as a bidirectional interface for media card applications.

• DCDi (Directional Correlation De-Interlacing) is an algorithm from Genesis Microchip’s Faroudja division, that is used to deinterlace video content (convert from interlaced to progressive scan). DCDi is known for its smooth interpolation of video content as it fills in the missing lines. Its purpose is to eliminate jagged edges (jaggies) along diagonal lines caused by interpolation, resulting in the projection of cinema-like images with exceptional picture quality.

• The FLI8668 allows a very flexible PIP display configuration whereby either the graphics or video channel may act as the PIP source to overlay over the other channel. Any one of the inputs (analog RBG, 24-bit digital, 8-bit digital, YPbPr, composite video, etc) may be multiplexed to either channel. The PIP can be from any of the AIP (Analog Input Port) 1 or 2 or DIP (Digital Input Port) 1 or 2. Single PIP allows the PIP display to be placed arbitrarily in the display window. It can be placed within the Main display, partially overlapped with Main display, or fully detached from Main display. Multiple PIPs display allows a number of PIP windows to be displayed at the same time depending on display pixel resolution. The Main and one PIP window will be running in real time. There are up to 16 PIP windows available at the same time, however only one might be active. All of them should be aligned to the 4x4 grid. Default S/W application uses multiple PIP windows to display different RF channels.

• Two LVDS channels (A and B) are available on the output of the FLI8668 to transmit data and timing information to the display device. FLI8668 directly drives the standard LVDS interface panels, supporting all standard data formats—single and dual bus, 18- or 24-bit data output. The 24-bit data may be mapped as either standard receiver formats.

• The FLI8668 has a fully programmable, true color bitmapped OSD controller capable of displaying up to 16 “tiles” or bitmap windows on the display. The individual tiles are programmable for location, size and bits per pixel, and have a precedence determining which tiles appear when overlapping occurs on the display. Tile data is stored in the external frame store memory by the OCM in either : 1, 2, 4, or 8-bit per pixel format. On-chip table registers point to the start of tiles in external memory. A programmable on-chip 256x24-bit color lookup table is provided to map the OSD pixels onto a true 24-bit color space.

• The FLI8668 on-chip microcontroller (OCM) serves as the system microcontroller. It programs the FLI8668 and manages other devices in the systemsuch as the keypad and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can address a 22-bit address space to utilize 4 MB external ROM.


H3 High Power

A

B

C


H3 High Power - A

Power Sequence :

1. Power Cord connect to set. Power b/d supplies 5VSTCON from wafer P1000 pin 3 and 8. This is also distributed as +5VST_CORTEZ, that connect to Regulator IC1001, IC1004, and IC1005, which regulate 1.8, 2.5, and 3.3V for Cortez (turns ON). Also distributed as +5VST, that connect to Transistors Q1000,1001,1004, and 1005.

2. AC_DET signal are sent by Power b/d from pin 1 wafer P1000 to pin N23 of IC800(Cortez). Then Cortez send 3.3V_ON from pin M2 to Power b/d via pin 13 P1000.

3. IC800 send RL_ON from pin U24, this switches the transistor Q1004 ON so +5VST grounded, this makes the transistor Q1000 OFF, so other +5VST supplies RL_ON on pin 2 wafer P1000. So Relay on Power b/d turns on to supplies 3.4, 6, 12, and 19V.(section 2)

4. 5VDet is sent by Power b/d to Cortez. Then Cortez send command to turn on VaVs from pin U25 that switches ON transistor Q1005, so +5VST grounded, this makes transistor Q1001 OFF, and this make another +5VST supplies to pin 5 wafer P1000. The Power b/d supplies X b/d and Y b/d.

1

2

3

4

+5VST

AC_DETRL_ON


H3 High Power - B

5Và3.3V

3Và1.8V

12Và9V

Power Sequence :

1. The +5VST_Cortez as an input on pin 1 of IC1001(BA033T), a LOW SATURATION VOLTAGE REGULATOR, is being step-down to 3.3V. Then this output act as input and enable for IC1003 pin 2 and pin 1 (SC1565-1.8TR), a VERY LOW DROP OUT 1.5 Amp REGULATOR WITH ENABLE, the output 1.8V is in pin 4, that is regulated to +1.8V_ADC_CTZ,+1.8V_CORE_CTZ, +1.8V_DLL_CTZ, and +1.8V_PLL_CTZ.

2. The P_12 (from section 2), as an input on pin 1 of IC1002 (KA7809R), a 3-TERMINAL 1A POSITIVE VOLTAGE REGULATOR, regulated to be 9V output on pin 3, distributed as +9V_CXA2069, +9V_MSP4450, +9V, and +9V_TK1184.

3. The VAVS_ON from Cortez switches ON transistor Q1006, and makes +12V_panel grounded and supply pin1-4 IC1006(SI925DY), a DUAL P-CHANNEL LOGIC LEVEL POWER TRENCH MOSFET, minimized ON state resistance, and the output is on pin 5-8 a 12V_LCD. The VAVS_ON also enable IC1007 pin 7, to step-down an input +12V_PANEL on pin 2 into 5V_LCD on pin 1 and 3.


H3 High Power - C

5Và3.3V

3.3Và2.5V

5Và3.3V

Power Sequence :

1. The+5V_CORTEZ acts as input on pin 1 of IC1005(BA033T) a LOW SATURATION VOLTAGE REGULATOR, which step-down into 3.3V output on pin 3. This outputs then is distributed as +3.3V_PLL_CTZ, +3.3V_LBADC_CTZ, +3.3V_LVDS_CTZ, +3.3V_LVDS_PLL_CTZ, and +3.3V_IO_CTZ.

The 3.3V output from IC1005 also acts as input on pin 1 of IC1000 (MIC39100-2.5WS), a 2.5V/1A REGULATOR, step down the 3.3V into 2.5V output on pin 3 as a +2.5V_DDR_CTZ.

2. The+5V_CORTEZ also acts as input on pin 1 of IC1004(BA033T, a LOW SATURATION VOLTAGE REGULATOR, which step-down into 3.3V output on pin 3. This outputs then is distributed as +3.3V_ADDC1_CTZ, and +3.3V_ADDC2_CTZ


1. No power

◈ Symptom

1) Minute discharge doesn’t occur at module.

2) Front LED doesn’t come into action.

Start check

Is inserted a plug

in power cord?

Is connected the Line Filter and PSU?

Is normal the fuse of PSU? Plasma(F101),

LCD(F111)

Plug in a power cord

Connect a cable.Plasma (EL11), LCD(SC100)

Replace the fuse

Is it connected that PSU and 13pin cable

in VSC board?

Connect the 13pin cable.

YES

YES

YES

YES

NO

NO

NO

NO

After remove all cables connected to PSU(except the CN101), authorizes the AC voltage marking on manual. When ST-by 5V doesn’t operate, replace PSU

Trouble Shooting Guide


◈ Symptom

1) After once shining, it doesn’t discharge minutely from module.

2) The relay falls.( The sound is audible “ Click”)

3) It is converted with the color where the front LED is red from white.

2. Protection mode

Start check

Is the PSU normal?

Is the each connector normal?

Is the Y- Board normal ?

Is output the normality Low/High Voltage except Stand-by 5V?

Replace the power board

After connecting well each connector the normality it operates?


Is normal the output voltage after remove P1connector of Y-B/D?

Replace Y-B/DIs normal the fuse

(FS2,FS3) on Y-B/D?

Replace the fuse

Is the Z- Board normal ?

Is normal the output voltage after remove P1 connector of Z-B/D?

Replace Z-B/DIs normal the fuse

(FS1,FS2) on Z-B/D?

Replace the fuse

Is the X- Board normal ?

After remove P100,110 output voltage normality: Replace Right X-B/D After remove P200,210 output voltage normality: Replace Left X-B/D

Is normal the output voltage after remove P100,110,200, 210

connector of X-B/D?

YES

YES

YES

YES

YES

YES

NO

NO

NO

NO

NO

NO

NO



3. No Raster

◈ Symptom

1) No OSD and image occur at screen.

2) It maintains the condition where the front LED is white

Start check

Is the link cable normal?

Reconnect the link cable in P803(Plasma)/P804(LCD)

NO

Is the IC800’s output normal?

NO Replace the VSC

Does minute discharge at

Module?

NO Is the inverter/VaVs

on?

Check the PDP/LCD Module

Is output the normality Low/High Voltage except Stand-by 5V?



YES

YES

YES

NO


4. In case of becomes unusual display from RF mode(Main)

A

Is normal video outputof the Tuner?

(Check TU201_Pin14)

Is normal the I2C communication ?(Check Pin5, Pin4)

Is normal the Input voltage ?(Check L308)

Is normal the Input voltage ?(Check Pin8, Pin6)

Is normal video output of CXA2069Q?

(Check R324, In case of S-Videocheck R324, R328)

Is the Tuner Cableconnected well?

Change the TunerCheck the power

( L1103)Cable inserts well.

Is normal the I2C communication ?(Check R309, R310)

Change the IC(IC300)Check the power( Check L1004)

Change the IC(IC800)

Is the LVDS Cableconnected well?

Cable inserts well


NO NO NO

YES

NO YES YES

YES

YES

YES

NO

NO NO

NO


5. In the case of becomes unusual display from rear AV mode(main)

6. In the case of becomes unusual display from rear S-Video mode(main)

7. In the case of becomes unusual display from side AV mode(main)

Is normal video inputof the A/V jack?(Check R343)

Is normal video inputof the A/V jack?

(Check R198, R199, R2100)


Check the input source)

Same as Block A

Same as Block A

Same as Block A




YES

NO

YES

NO

YES

NO


8. In the case of becomes unusual display from side S-Video mode(main)

9. In the case of becomes unusual display from SCART 1 mode(main)

10. In the case of becomes unusual display from SCART 1_RGB mode(main)


(Check R339, R341, L310)Check the input source


(Check L111, L112, L106)


Same as Block A

Check the input source


Same as Block A

Same as Block A


YES

NO

YES

NO

YES

NO


11. In the case of becomes unusual display from SCART 2 mode(main)

12. In the case of becomes unusual display from SCART 2_YC mode(main)




(Check R115, R149)Check the input source

Same as Block A

Same as Block A


YES

NO

YES

NO


13. In case of becomes unusual display from RF mode(Sub)

Is normal video outputof the Tuner?

(Check TU200_Pin14)

Is normal the I2C communication ?(Check Pin5, Pin4)

Is normal video output of CXA2069Q?

(Check R312, In case of S-Videocheck R312, R314)

Is the Tuner Cableconnected well?

Is normal the Input voltage ?(Check Pin8, Pin6)

Is normal the Input voltage ?(Check L308)

Is normal the I2C communication ?(Check R309, R310)

Change the IC(IC300)Check the power( Check L1004)

Change the IC(IC800)

Is the LVDS Cableconnected well?

Cable inserts well

Change the TunerCheck the power

( L1103)Cable inserts well.

B


NO

NO NO

NO NONO

NO

YES

YES

YES

YES YES

YES YES

14. In case PIP doesn’t display from other modes(Sub)

▷ Same as the case of main except block A should be change to B


15. In case of becomes unusual display from component1 mode(main/sub)

16. In case of becomes unusual display from component 2 mode(main/sub)

17. In case of becomes unusual display from RGB mode(main/sub)

Is normal video inputof the JK102?

(Check L126, L127, L128)Check the input source

Is normal video inputof the JK103?

(Check L129, L130, L131)

Is normal R, G, B inputand H,V sync of the JK500?(Check R509, R511, R512

R513, R515)



Change IC(IC800)

Change IC(IC800)

Change IC(IC800)


YES

NO

YES

NO

YES

NO


◈ Symptom

LED is White

Screen is existent, but sound isn’t

◈ Check follow

18. No Sound

All input (mode)is no sound?

Is the speakeron in menu?

Is the speakercable normal?

IC400 operatenormally?

Set on speaker in menu

Check the Speaker cable

Replace IC400


Replace IC401


Replace IC402

Replace VSC B/D

Only HDMI isno Sound?

Download the EDID data

Only AV input isno Sound?

Is the output of IC300(pin52,53)

normal?

Check the signalafter IC300

refer to circuit diagram

Replace IC300

Only RF isno Sound?

Check the Tuner In/Out

YES

YES

YES

YES

YES

YES

YES

YES

YES

NO

NO

NO

NO

NO NO

NO

NO

NO

NO



No

Is normal only video ?

Is normal only audio?

Check TMDS line wave.(R1215 ~ R1222/ R1226 ~ R1233)

Download EDID data each port.

1. Check TV input mode.(HDMI1 port support HDMI and DVI. So if you input DVI signal and PC audio from phone jack,You can hear PC audio. )2. Unplug and plug HDMI cable.(sometimes ESD surge occurred at HDMI port.)3. Check HDMI Mute register. (0x68, offset 0x37)4. Check Audio-out channel mute register (0x68, offset 0x32)

is appropriately enabled.

Check HDMI source. Change another source or cable.Is wave continuous?

1. Check HDMI receiver’s status register. (0x60, offset 0x06)- If the value is 0xf or 0x8, it is normal.

2. Check HDCP register. (0x60, offset 0x32)- Enable bit 6: HDCP key loaded- Enable bit 5: HDCP decryption active- Enable bit 4: HDCP authen. attempted

No

No

Replace IC1200Reset TMDS power down/on register.- 0x60, offset 0x3f : 0xf7 => 0xff

Yes

Yes

Normal video, Normal audio?

Yes

No

19. HDMI mode



GProbe 5.2.0.2.exe

Install the GProbe Software from the Desktop using the GProbe 5.2.0.2.exe file.

Gprobe5 Install & Download Guide


CGProbe Redistributable 5.2.0.4

After installing GProbe 5.2.0.2 install the CGProbe from CGProbe Redistributable 5.2.0.4.exe as shown in the figure.



Select the Icon named GProbe 5 Tool for downloading the software in T.V. from the desktop.

GProbe 5



Verify the GProbe UI Version: 5.2.02 and CGProbe Version: 5.2.0.4 from the Help menu under About GProbe.. .

Help Menu



Choose the appropriate chip from Select Chip: FLI8638

Check Connection settings.

Connection Settings

Select Chip:



Set the Connections as shown in figure:Device: Serial Protocols: SERIAL1 Scheme: Serial connection for all Genesis Chips



Set the Connections as shown in figure:Port: COM1 Data Bits: 8 Baud Rate: 115200 Parity: None

Stop Bits: 1



Set the Connections as shown in figure:Port: 0x378Clock Frequency: 60000 Hz Scheme: Standard Speed LPT1(0x378)



Set the Connections as shown in figure:I/p Pin: 15(active high) O/p Pin: 17(active high) SDA Signal I/p Pin: 11(active high) SDA Signal O/p Pin: 9 (active high)Scheme: Default Pin Assignments



Set the Connections as shown in figure:

Scheme: Default USB Setting



Set the Connections as shown in figure:Short Timeout: 1000 ms Long Timeout: 15000 msAddress: 4096 Size: 4096 Scheme: Default Setting



Select the “Commands” Option and then select the “Batch” option to locate the Path from where the “.text file” has to be downloaded which contains the information regarding the location of final “.hex file”.



Browse the .txt file from its specified location in the directory such as:

C:\clearcase_rohit\rohit_view2\CC_HURRICANE3_H\10_Source\FLI8668\Isp\batch\CORTEZ_A.txt

browse



After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for downloading the software other wise it generate an Error.RS232 Host: Gprobe.Baud Rate: 115200bps(T.V in Power on state)/9600bps (T.V in stand by Power off).



After selecting the Appropriate Batch file Check that the T.V is in GProbe Mode for downloading the software other wise it generate an Error.

Error: Timeout while waiting for Response.



If the connections between T.V Board and C.P.U are not proper or T.V is not in the GProbemode it will give “Error Message” as shown in figure.Error Message: Timeout while waiting for Response.So Check the connection properly and GProbe condition & again Start Downloading.



After Downloading complete its shows :Execution time: XXX.XX second (~~Approx)Batch: Command Successful.



Gprobe5 Debugging

GPIO port debugging

appstest 0 input

appstest funtion help


Gprobe5 Debugging

Register Bit Types

After value change,

Input 0xe000 = 0xff in command window

è Execute (Real value change)

After value change,

è Directly Real value change

PAA,CRW,CRO,RO,WO type èWe could not change the register value using the Gprobe5


Gprobe5 Debugging

appstest 61CXA2069 Status : read

appstest 60 Main Pip MonitorOutCXA2069 register : writeCXA2069

appstest 31 Addr1 Addr2 DataMSP Specific register : value write

appstest 32 Addr1 Addr2MSP Specific register : value read

appstest 33MSP initialization

MSP

appstest 76 SubAddr Addr DataHDMI Specific register : value write

appstest 75 SubAddr AddrHDMI Specific register : value read

appstest 4HDMI initialization

HDMI

appstest 23 Addr DataEEPROM Specific address : Word write

appstest 24 AddrEEPROM Specific address value : Word read

appstest 21 Addr DataEEPROM Specific address : Byte write

appstest 22 AddrEEPROM Specific address value : Byte read

appstest 1 99EEPROM initialization (Include adjustment Data)

appstest 1 0EEPROM initialization (Except adjustment Data)

EEPROM

IC control Example


EDID data Download Guide.

1. Required Test Equipment

1) Adjusting PC with S/W for writing EDID Data.(S/W : EDID TESTER Ver.2.5)2) A Jig for EDID Download3) Cable : Serial(9Pin or USB) to D-sub 15Pin cable, D-sub 15Pin cable, DVI to HDMI cable.

2. Setting of the device

Connection Diagram of DDC download


3. Preparation for Adjustment

1) As above Fig. 5, Connect the Set, EDID Download Jig,, PC & Cable2) Turn on the PC & EDID Download Jig. And Execute the S/W : EDID TESTER Ver.2.53) Set up the S/W option .

Repeat Number : 5Device Address : A0PageByte : 8

4) Power on the Set



4. Example Data of EDID(42PC1R-ZH)

1) 42PC1R-ZH DDC data of Analog-RGB (Check Sum : CE )

[BLOCK0]

2) 42PC1R-ZH DDC data of Digital_HDMI (Check Sum : 0B2B)

[BLOCK0] [BLOCK1]



5. Sequence of Adjustment

1) Init the data 2) Load the EDID data.( Open File : Analog ,Digital)3) Push the “Write Data & Verify” button. And confirm “Yes”.4) If the writing is finished, you will see the “ OK” message5) It is important that PP62A/C has two HDMI

so digital DDC downloading must be performed two times(HDMI 1 , HDMI 2)



Owner’sManual

Module CAS

Document

Circuit Diagram

AdjustmentUI

Specification

Area OptionTable

Gprobe5

50X3_PDP 32LCD_LPL 37LCD_LPL 42LCD_LPL 37LCD_AUO42X3_PDP

Circuit Diagram_VSC

Circuit Diagram _ Local key

Circuit Diagram _ Side AV

Circuit Diagram _ PreAMP

Adj_UI Specification

CGProbe5.2.0.4GProbe5.2.0.2

Owner's manual _ EU

Owner's manual _ Non EU

LCD H3 High Option Table

PDP H3 High Option Table

Lg 37lc2r 42lc2r 32lb1r 37lb1r 42lb1r Hurricane3 High Chassis Guide Training [ET][1]

Documents

Transcript of Lg 37lc2r 42lc2r 32lb1r 37lb1r 42lb1r Hurricane3 High Chassis Guide Training [ET][1]