lfsr

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Linear Feedback Shift Register v3.0DS257 (v1.0) March 28, 20030 0

Product Specification

FeaturesThe LFSR core has the following features: Drop-in module for Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE, and Spartan-3 FPGAs Optional SRL-16 implementation Choice of LFSR type (Fibonacci or Galois) Choice of feedback gate type (XOR or XNOR) Configurable LFSR length Configurable initial tap positions Serial or parallel output Optional clock enable input Optional maximum length logic Optional load with configurable load type Optional data valid output Optional asynchronous reset Optional synchronous reset Optional counter implementation for maximum length logic Optional new seed output Uses relationally placed macro (RPM) mapping and placement technology, for maximum and predictable performance Incorporates Xilinx Smart-IP technology for utmost parameterization and optimum implementation To be used with v5.2i and later of the Xilinx CORE Generator System

LFSR Type (Fibonacci or Galois)The LFSR can be created using the Galois or Fibonacci configuration of gates and registers.

Fibonacci FunctionalityIn the Fibonacci implementation, the outputs from some of the registers are exclusive-ORed with each other and fed back to the input of the shift register. Figure 1 shows a 3-bit Fibonacci LFSR.

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Figure 1: 3-bit LFSR When the shift register is loaded with a seed value (any value except all zeros) and then clocked, the output from the LFSR (Q2) will be a pseudo-random sequence of 1s and 0s. For example, Table 1 shows the sequence that is produced from the circuit in Figure 1 when the seed is 111. Table 1: LFSR Sequence for Initial Seed 111 Q2 1 1 1 0 0 1 0 1 Q1 1 1 0 0 1 0 1 1 Q0 1 0 0 1 0 1 1 1

Functional DescriptionThe linear feedback shift register (LFSR) is a shift register which, using feedback, modifies itself on each rising edge of the clock. The feedback causes the value in the shift register to cycle through a set of unique values. The choice of LFSR length, gate type, LFSR type, maximum length logic, and tap positions allows the user to control the implementation and feedback of the LFSR, which, in turn, controls the sequence of repeating values the LFSR will iterate through.

The pseudo random sequence can also be generated using exclusive-NOR gates. In this case the seed can be any value except all 1s. The sequence that is generated is of the same length as the exclusive-OR example above. 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

DS257 (v1.0) March 28, 2003 Product Specification

www.xilinx.com 1-800-255-7778

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Linear Feedback Shift Register v3.0 The length of the pseudo-random sequence is dependent on the length of the shift register and the number and the position of the feedback taps. The number and the position of the taps are commonly represented by a polynomial. For the Xilinx core, this is expressed in the form: P(x) = X3 + X1 + 1 For more information on this polynomial notation and how it relates to the LFSR implementation, refer to Appendix A: LFSR Polynomial Notation.

Feedback Gate Type (XOR or XNOR)XOR or XNOR gates can be used in the feedback path.

Configurable LFSR SizeThe LFSR supports sizes from 2 to 168. This is the number of registers that make up the shift register. This value is referred to as LFSR size or C_SIZE for this core, but might also be referred to as the width or length of the LFSR by other sources.

Galois FunctionalityIn the Galois implementation, the gates are placed between the registers. Figure 2 shows the Galois implementation of the LFSR from the previous example. This configuration produces the sequence shown in Table 2. This shows that the output sequence (Q2) is the same as the previous example, although time shifted by 1 cycle.

Configurable Initial Tap PositionsA series of ones and zeros represent the coefficients of the LFSR polynomial. These values describe the location of feedback taps for the LFSR. In the Fibonacci implementation, the output of some of the registers is combined using XOR or XNOR gates, then fed back into the input of the first (LSB) register. These feedback connections from the output of these selected registers are the tap positions. In the Galois implementation, the output of the last (MSB) register is fed back into XOR or XNOR gates located between the shift registers. In this case, the tap locations are the locations where the XOR/XNOR gates are located. A defined polynomial provides a standard way of defining the location of these taps for both Fibonacci and Galois implementations. For more information on how this polynomial correlates to the LFSR structure, see Appendix A: LFSR Polynomial Notation.

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Figure 2: Galois Implementation of a 3-bit LFSR

Table 2: LFSR Sequence for Initial Seed 111 Q2 1 1 0 0 1 0 1 1 Q1 1 0 0 1 0 1 1 1 Q0 1 1 1 0 0 1 0 1

Serial or Parallel OutputThe output of the LFSR can either be serial or parallel.

Optional SRL-16 ImplementationThe LFSR can use either an SRL16 or a register implementation. Note that SRL16 is only possible for certain cases, the core will revert to register implementation automatically if an SRL16 implementation is not available.

Optional Clock Enable InputIf the optional clock enable input has been selected, then the user can enable and disable the LFSR through use of the clock enable.

Optional Maximum Length LogicAn LFSR iterates through a number of unique states, generating a particular sequence of values, depending on its size, implementation, gate type, and taps. This sequence is referred to as the LFSR sequence. The number of values in the sequence is referred to as the LFSR sequence length. The LFSR sequence can contain up to (2k 1) unique values (where k is the LFSR size). The sequence length will vary from 1 to (2k 1) unique values, depending on LFSR size, implementation, and tap positions. Often, it is desirable to maximize the number of unique values in the LFSRDS257 (v1.0) March 28, 2003 Product Specification

Again, the length of the pseudo-random sequence is dependent on the length of the shift register and the number and the position of the feedback taps. The number and the position of the taps can again be represented as a polynomial. For the Xilinx core, this is expressed in the form: P(x) = 1 + X1 + X3 For more information on the polynomial notation, refer to Appendix A: LFSR Polynomial Notation.

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Linear Feedback Shift Register v3.0 sequence by finding a set of tap positions which will cause the LFSR to have its maximum sequence length of (2k 1). Appendix B: Maximum Sequence Length Polynomials, provides a table of tap positions that will cause the LFSR to iterate through its maximum sequence length. By default, an LFSR can have, at most, (2k 1) unique values in its sequence. However, since the LFSR has k registers, it is capable of storing 2k unique values. If an XOR-gate LFSR iterates through its maximum sequence of (2k 1), the state which will not be included will be the all-zeros state. Using XOR gates in the feedback, the LFSR can not generate an all-zeros value, and if the registers contain an all-zeros value, they can not generate a 1 bit in any of the registers. This 2kth state is considered to be the LFSRs forbidden state, since it can not enter or exit this state. For an LFSR with XNOR gates, the all-ones state is the forbidden state. Maximum Length Logic is a block of logic that can be added to the LFSR to allow the LFSR to access the forbidden state. It does not guarantee a certain sequence length or that the core will ever enter or exit the forbidden state, but it does increase the maximum possible sequence length to 2k unique values. If the maximum sequence length is chosen from Appendix B, and Maximum Length Logic is enabled, the sequence length of the LFSR will increase from (2k-1) to 2k, thereby allowing the maximum possible length sequence for an LFSR of size k. The maximum length logic makes for an area inefficient LFSR, since the logic to detect all zeros or all ones can require numerous extra LUTs. It is also speed inefficient, adding large delay along the critical path. In addition, the SRL16 option would be unavailable, because every bit of the SRL16 would need to be exposed to the maximum length logic. The maximum length logic is implemented using combinational logic. A counter can be used for the maximum length logic in certain conditions, which can help with performance for larger LFSRs. To complete a simple Pseudo-random Number (PN) generator we add the logic for serially loading the seed to the LFSR. A DATA_VALID signal is optionally provided at the output of the PN Generator. Figure 4 shows the block diagram for the simple LFSR PN generator. It should be understood that a serial load of a new seed, for a Fibonacci-type LFSR, can behave as a pseudo-parallel load. This option is preferred to a parallel load option since a parallel load prevents the core from being implemented using SRL16 primitives. If the user determines that the serial load option is not adequate, the core also has a parallel load option. The DATA_VALID output signal performs differently depending on the type of load. For more information see Appendix C: Data Valid Output.

Optional Data Valid OutputThe core can have the option of a DATA_VALID output pin. This pin indicates to downstream logic whether the output is valid. For a thorough description of the DATA_VALID and NEW_SEED outputs, see Appendix C: Data Valid Output.

Optional New Seed OutputThe core can have a NEW_SEED output that indicates the completion of a load operation. For a thorough description of the DATA_VALID and NEW_SEED outputs, see Appendix C: Data Valid Output.

Optional Asynchronous ResetThe core can have an optional asynchronous reset.

Optional Synchronous ResetThe core can have an optional synchronous reset. A parallel load of a constant value can be accomplished by using synchronous reset, which is more efficient than using the parallel load feature.

Optional Counter Implementation for Maximum Length LogicMaximum length logic can, in certain cases, be implemented using a counter to improve efficiency. This allows maximum length logic to be used while still allowing the space-efficient use of SRL16s. This also improves speed performance for larger LFSRs. For more information see the Performance section of this datasheet.

Clock - CLKThe input clock for the LFSR.

Serial Data Output - SD_OUTThis is the output from the last register in the LFSR. This output is a pseudo-random number sequence of 1s and 0s.

Parallel Data Output Bus - PD_OUT [N-1:0]This is an output bus of width N (LFSR size) where each bit is the output of a register in the LFSR. By the nature of the LFSR, this will produce a repeating finite set of unique values. The sequence depends on the initial seed and the taps selected. This output can be used as a FIFO controller since it behaves like an out-of-order binary counter.

Optional Load with Configurable Load TypeThe core can have an optional load, which can load a new seed value into the registers of the LFSR. Load can be either serial or parallel.



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Linear Feedback Shift Register v3.0

Load Control Input - LOADThis input pin, when asserted high, begins the loading of a seed value from the SD_IN or PD_IN input bus into the LFSR. If the load input type is serial (core has a SD_IN port), then the LOAD pin must be held high for a number of clock cycles until the data to be loaded has been completely clocked into the LFSR. If the load input type is parallel (core has a PD_IN port), then the LOAD pin must be held high one clock cycle while the data from the PD_IN port is written into the LFSR on the rising edge of the clock.

the LFSR with a seed is needed, and it is acceptable to set that value as a constant, SINIT should be used. Note that, if the core does not have maximum length logic, it is possible to initialize the core to a value that will lock up the LFSR. If the LFSR uses XOR gates and no maximum length logic, the all-zeros SINIT will freeze the core. For an LFSR with XNOR, the forbidden state is the all-ones case.

Asynchronous Initialization Input - AINITWhen asserted, AINIT immediately resets the LFSR registers with the Asynchronous Reset Value. This is the same value that the LFSR will assume on global reset/power up.

Serial Data Input - SD_INWhen this input port is present, it is used to input data bit-by-bit to initialize the LFSR when LOAD is high.

Terminal Count Output - TERM_CNTThis is an output that goes high every K clock cycles for two clock cycles, where K is the number of values in the LFSR number sequence. When present, the TERM_CNT output is created by the Maximum Length Logic, asserting a logic 1 whenever the Maximum Length Logic modifies the feedback to cause the LFSR to enter or exit the forbidden state.

Parallel Data Input Bus - PD_IN[N-1:0]When this input bus is present, it is used to load data of width N (the LFSR size) into the LFSR in a single clock cycle. The LFSR is loaded with this value when the LOAD signal is high.

Clock Enable Input - CEWhen CE=1 or when the CE port is not present, the core will update its state on every rising edge of the clock. When CE=0, the core will not change state or output values unless an asynchronous reset is asserted.

Logic Symbol

Data Valid Output - DATA_VALIDThe DATA_VALID pin indicates to downstream logic that the current output is the logical next member of the PN sequence. See Appendix C for more information.

New Seed Output - NEW_SEEDThe New Seed output goes high when a load operation has successfully been completed. See Appendix C for more information.XIP175

Figure 3: LFSR Schematic Symbol

Synchronous Initialization Input - SINITWhen asserted, the Synchronous Initialization input resets the LFSR registers with the Synchronous Reset Value on the rising edge of the clock. This is useful as a way to seed the LFSR at run-time, without including the load logic (which introduces significant overhead). When an ability to initialize

PinoutPort names for the core module are shown in Table 3 and Table 4. Table 3 lists the ports that are required for the core, while Table 4 lists ports that are optional based on the options selected in the CORE Generator.

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Figure 4: LFSR used as a simple PN-Generator4 www.xilinx.com 1-800-255-7778 DS257 (v1.0) March 28, 2003 Product Specification

Linear Feedback Shift Register v3.0 Table 3: Mandatory Pins Port Name CLK Port Width 1 Direction Input Description Clock

Table 4: Optional Pins Port Name SD_OUT PD_OUT[N-1:0] LOAD SD_IN PD_IN[N-1:0] CE DATA_VALID SINIT AINIT NEW_SEED TERM_CNT Port Width 1 LFSR Size (N) 1 1 LFSR Size (N) 1 1 1 1 1 1 Direction Output Output Input Input Input Input Output Input Input Output Output Serial output Parallel output Fill Enable for the LFSRs Serial data input Parallel data input Clock Enable High when output is valid Synchronous Initialization (constant value reload) Asynchronous Initialization (asynch constant reload) High when a new seed has just been loaded. High for two clock cycles every K clock cycles parallel output bus. Feedback Gate Type: This value selects the type of gate used for the LFSR, XOR or XNOR. The type of gate selected produces a completely different sequence of values in the LFSR. XOR: If XOR is chosen, the all-zeros case can never be entered from another state, and the core can not exit an all-zeros state unless Maximum Length Logic is enabled. XNOR: If XNOR is selected, the all-ones case can never be entered from another state, and the core can not exit an all-zeros state unless Maximum Length Logic is enabled. Description

CORE Generator ParametersThe CORE Generator parameterization windows for this module are described below. The first graphical user interface allows the implementation, special features, and layout to be defined. The second GUI allows the optional ports to be chosen and configured. The last GUI allows the taps to be chosen. The window below the tap polynomial displays the X-terms for the polynomial. The implementation window displays a simple diagram which describes how the LFSR will be implemented. The available options are described below.

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Definition of GUI Interface Fields Component Name: Enter a name for the output files generated for this module (up to 256 characters). Implementation: Select between the use of register or SRL16 implementation of the LFSR. Registers: The shift chain of the LFSR will be created from registers only. The number of registers used is equal to the size of the LFSR. SRL16: SRL16 Virtex primitives will be used to replace registers in the design whenever a series of 3 or more registers are chained together without combinational logic. The use of SRL16 primitives can generate a substantial size improvement for the core, depending on the taps and options selected.

Output Type: Indicates whether the LFSR has serial or parallel output. Parallel: The output bus is formed by connecting the outputs of the entire register chain. Serial: The serial output bit is connected to the output of the most-significant bit of the LFSR.

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Load Type: Indicates the type of load for the LFSR. The type of load directly affects the DATA_VALID output. For more information, see Appendix C: Data Valid Input. None: There is no way to load a value into the LFSR. The PD_IN and SD_IN ports are not connected when there is no load. Serial: The data on SD_IN will be written, one bit at a time, to the LFSR registers when asserting the LOAD input. Data is shifted directly into the LFSR bit-by-bit on each clock cycle that LOAD is

LFSR Type: Choose the feedback type, either Fibonacci or Galois LFSR Size: Length of the LFSR. A size from 2 to 168 can be chosen. The size determines the width of the

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Linear Feedback Shift Register v3.0 asserted. If the core has a serial load, the PD_IN port is not connected. Parallel: The data on PD_IN will be written to the LFSR registers on assert of the LOAD input and will load in one clock cycle. If parallel load is used, the SD_IN input is not used. registers. If Maximum Length Logic is not used, then a Synchronous Reset value of all-zeros (in the XOR gate case) or all-ones (in the XNOR gate case) will place the core in a lock-up state which it can not exit until another seed value is loaded into the core (using load). Clock Enable: Check this box to add the CE input port to the LFSR. If no clock enable input is present, the core is enabled by default. New Seed Output: Check this box to add the NEW_SEED output port to the LFSR. For more information, see Appendix C: Data Valid Option. Data Valid Output: Check this box to add the DATA_VALID output pin to the LFSR. For more information, see Appendix C: Data Valid Output. Terminal Count Output: Check this box to add the TERM_CNT output pin to the LFSR. This is only present when Maximum Length Logic is used. It allows the LFSR to be used as a repeating terminal count counter, outputting a logic one once per cycle of the LFSRs sequence. Field Polynomial: The hexidecimal value that specifies the polynomial of the LFSR. The polynomial describes how the LFSRs feedback is configured. The polynomial that corresponds to the inserted hex value is displayed in the small window below the field polynomial textbox. For information on how to specify the polynomial, see Appendix A: LFSR Polynomial Notation. Implementation: This graphic is a basic block diagram of how the polynomial maps to the hardware that will be built. This graphic is dependant on the LFSR type chosen. For information on how to specify the polynomial, see Appendix A: LFSR Polynomial Notation. Generate: Select to generate the LFSR module. Make sure that the parameters are correctly selected for the particular application before executing this option. Cancel: Select to close window and return to the CORE Generator. Datasheet: Select to generate a PDF version of this document.

Use Maximum Length Logic: Indicates whether the core should incorporate logic to allow entry and exit from the lock-up state. This adds a possible state to the LFSR sequence, allowing the maximum possible sequence of unique values to be 2n terms instead of 2n-1. (Where n is the number of registers in the LFSR). Maximum length logic makes sense only for tap polynomials that generate a maximum length sequence, such as those found in Table 8 in Appendix B. Since there are other tap polynomials not listed in Table 8, which may also generate a maximum length sequence, it is left to the user to decide whether maximum length logic is appropriate for the desired application. Use Counter For Max Length Logic: Indicates the type of hardware used to implement the maximum length logic (if present). If this option is selected, a counter will be used to detect the all-zeros or all-ones case. Otherwise, gates are used to detect the all-zeros or all-ones case. For a Fibonacci LFSR with maximum length logic, serial or no load, and no SINIT or AINIT pins, a counter can be used to detect the all-zeros or all-ones lock-up case. For large LFSRs, or LFSRs which use SRL16s, the counter implementation is recommended when selecting maximum length logic. Create RPM: Enables relative placement directives for the core. See the section on core performance for more details. Asynchronous Reset: Check the box to add the asynchronous port AINIT to the LFSR. Asynchronous Reset Value: The hexidecimal value that specifies the asynchronous reset value of the LFSR registers. This value is also used as the initial state of the core, regardless of whether the AINIT port is present. If Maximum Length Logic is not used, then an Asynchronous Reset value of all-zeros (in the XOR gate case) or all-ones (in the XNOR gate case) will place the core in a lock-up state which it can not exit until another seed value is loaded into the core (Using load or SINIT). Synchronous Reset: Check the box to add the synchronous port SINIT to the LFSR. Synchronous Reset Value: The hexidecimal value that specifies the synchronous reset value of the LFSR

Parameter Values in the XCO FileNames of the XCO parameters and their parameter values are identical to the names and values shown in the GUI, except that underscore characters (_) are used instead of spaces. The text in an XCO file is case insensitive. Table 5 shows the XCO file parameters and values, and summarizes the GUI defaults. The following is an example of the CSET parameters in an XCO file:

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Linear Feedback Shift Register v3.0 CSET component_name = my_lfsr CSET implementation = registers CSET lfsr_type = fibonacci CSET lfsr_size = 8 CSET feedback_gate_type = xor CSET output_type = output_type_serial CSET load_type = load_type_none CSET use_maximum_length_logic = false CSET use_counter_for_max_length_logic = false CSET create_rpm = false CSET asynchronous_reset = false CSET asynchronous_reset_value = FF CSET synchronous_reset = false CSET synchronous_reset_value = FF CSET clock_enable = false CSET new_seed_output = false CSET data_valid_output = false CSET terminal_count_output = false CSET tap_locations = 1D

Table 5: Parameter File Information Parameter Name component_name implementation lfsr_size lfsr_type feedback_gate_type output_type load_type use_maximum_length_logic use_counter_for_max_length_logic create_rpm asynchronous_reset asynchronous_reset_value synchronous_reset synchronous_reset_value clock_enable new_seed_output data_valid_output XCO Filename Values ASCII text starting with a letter and based upon the following character set: a..z,0..9 and _. One of the following keywords: srl16, registers Any integer 2 to 168 One of the following keywords: fibonacci, galois One of the following keywords: xor, xnor One of the following keywords: output_type_serial, output_type_parallel One of the following keywords: load_type_none, load_type_serial, load_type_parallel One of the following keywords: true, false One of the following keywords: true, false One of the following keywords: true, false One of the following keywords: true, false A hex value in the range of 0 to 2LFSR_size -1 One of the following keywords: true, false A hex value in the range of 0 to 2LFSR_size -1 One of the following keywords: true, false One of the following keywords: true, false One of the following keywords: true, false Default GUI Strings blank registers 8 fibonacci xor output_type_serial load_type_none false false false false FF false FF false false false



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Linear Feedback Shift Register v3.0 Table 5: Parameter File Information (Continued) Parameter Name terminal_count_output tap_locations XCO Filename Values One of the following keywords: true, false A hex value in the range of 1 to 2LFSR_size -1. Note that the LSB of the polynomial must be 1 because the X0 term is always in the polynomial. Default GUI Strings false 1D

Notes: 1. [A] The asynchronous and synchronous reset values are sometimes restricted: IF Use_Maximum_Length_Logic=true AND Use_Counter_for_Max_Length_Logic=true THEN IF feedback_gate_type=XOR THEN Asynchronous Reset Value = Hex value (2LFSR_size-1) Synchronous Reset Value = Hex value (2LFSR_size-1) ELSE IF feedback_gate_type=XNOR THEN Asynchronous Reset Value = 0 Synchronous Reset Value = 0 ELSE Asynchronous Reset Value = any value 0 to Hex value (2LFSR_size-1) Synchronous Reset Value = any value 0 to Hex value (2LFSR_size-1) 2. [B] Use_SRL16 is unavailable if: Output_type=Parallel OR Load_type=Parallel OR (Use_maximum_length_logic=Checked AND Use_counter_for_maximum_length_logic=Unchecked) OR Synchronous_Reset=Checked OR Asynchronous_Reset=Checked 3. [C] Use counter for max length logic is unavailable if: Use_maximum_length_logic=Unchecked OR LFSR_type=Galois OR Load_type=Parallel

DependenciesSome options in the CORE Generator GUI are limited in certain circumstances. The following tables help to clarify these interactions. Table 6: Summary of Permitted Async and Sync Reset Values Gate XOR XOR XOR XOR XNOR XNOR XNOR XNOR SRL16 Unchecked Unchecked Checked Checked Unchecked Unchecked Checked Checked MaxLenCounter No Yes No Yes No Yes No Yes (0) to (2^LFSR_SIZE-1) (0) to (2^LFSR_SIZE-1) where LSB=1 (2^LFSR_SIZE-1) (2^LFSR_SIZE-1) (0) to (2^LFSR_SIZE-1) (0) to (2^LFSR_SIZE-1) where LSB=0 0 0 Allowed Values

Notes: 1. LFSR_SIZE is the size of the LFSR.

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Table 7: Summary of Allowed Feature Combinations srl16 par load ser load no load par output ser output max len counter max len logic sinit ainit no yes yes no yes X X no no ainit yes yes yes yes yes Y yes Z sinit yes yes yes yes yes Y yes max len logic yes yes yes yes yes yes max len counter no yes yes yes yes ser output yes yes yes no par output yes yes yes no load no no ser load no

Notes: 1. X: X is yes or no, but must be the same for every occurrence of X 2. Y: ainit/sinit can be used with maximum length logic counter, but only if the LSB of the synchronous/asynchronous reset value is 0 (when using XOR gates) or 1 (when using XNOR gates) 3. Z: Not recommended (increases size and decreases performance)

Resource UtilizationThe following options increase the amount of on-chip resources consumed by the LFSR: Register Implementation (vs SRL16) Larger LFSR sizes Maximum Length Logic BOTH Asynchronous and Synchronous Resets Parallel Output Data Valid/New Seed Outputs

Data Valid Output/New Seed OutputAlthough they provide useful control signals for loading new values into the LFSR, the logic used to provide these outputs is slower than the LFSR itself. As the LFSR size increases, the performance of the Data Valid/New Seed logic degrades further. If a highly optimized LFSR is important, it is recommended that these outputs be disabled.

Asynchronous Reset/Synchronous ResetHaving BOTH an Asynchronous and a Synchronous Reset input on the LFSR core causes an extra gate to be placed between the shift registers. For small, fast LFSRs, this extra gate will negatively affect the performance of the core. If the LFSR's performance is already being degraded by another feature, the effects of having BOTH an Asynchronous and a Synchronous Reset input will be negligible. Note that having EITHER an Asynchronous or Synchronous Reset, but not both, has no noticeable effect on performance.

PerformanceThe options chosen for the LFSR can significantly impact its performance.

LFSR TypeFor LFSRs with only a few taps, the Fibonacci implementation will generally achieve a faster clock speed than it's Galois counterpart. Although faster for a small number of taps, the Fibonacci implementation's performance degrades as the number of taps increases. The Galois implementation, however, sees hardly any performance loss with an increase in the number of taps. So, for a basic LFSR, the Galois implementation is recommended to achieve desired speed results for more than 5 taps.

Use Maximum Length LogicBecause of the extra feedback logic added when using Maximum Length Logic, the critical path through the LFSR is increased, thus degrading performance. Since the normal Maximum Length Logic is constructed from combinational logic, its performance is optimal when the LFSR size is small. For very large LFSRs, it is recommended that the counter be used for Maximum Length Logic.

Initial Tap Locations (Tap Polynomial)Especially for Fibonacci implementations, fewer taps equates to faster speed.



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Use Counter for Maximum Length LogicThe typical combinational logic implementation of the Maximum Length Logic is faster than the counter implementation for most LFSR sizes. However, the counter implementation does not experience a significant performance loss as the LFSR size increases, as does the combinational logic implementation. Therefore, for very large LFSR cores, using a counter for the Maximum Length Logic is recommended.

core. This clearly differentiates between a Fibonacci-type and a Galois-type LFSR. This notation is also used by the W-CDMA specification 3G TS 25.213.

Galois-type LFSR NotationFigure 5 illustrates the tap numbering for a Galois-type LFSR. The Gains (X) are binary, either producing a feedback tap or no connection. Figure 6 shows an example of a Galois-type LFSR of length 3, with X0 = 1, X1 = 1, X2 = 0, X3 = 1. The example shown in Figure 6 is represented by the polynomial:

Terminal Count OutputThe terminal count output does not directly have an impact on performance. However, if the non-counter implementation of the Maximum Length Logic is used, the terminal count output is an ASYNCHRONOUS output. To maximize performance, it is recommended that this output be registered as soon as possible, or to simply not use this output. Relative Placement (RPM) can be used with the LFSR core. The core will not undergo a significant speed improvement by using RPMs, but when used as a component in larger designs, RPMs will help to keep the LFSR's performance more consistent, and will allow the higher level design to be placed and routed more efficiently.

p ( x)

X0

X1

X3

This clearly shows the position of the taps to produce the LFSR illustrated in Figure 6. Please note that X0 can also be written as 1. Therefore, alternatively:

p( x) 1 X 1

X3

Ordering InformationThis core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator System v5.2i and later. The Xilinx CORE Generator System tool is bundled with all Alliance Series Software packages, at no additional charge. To order Xilinx software, please visit the Xilinx Silicon Xpresso Cafe or contact your local Xilinx sales representative. Information on additional Xilinx LogiCORE modules is available on the Xilinx IP Center.

The taps polynomial can also be written as a string of bits, where each bit corresponds to the coefficient of a term of the polynomial. The highest-order terms correspond to the most significant bits, while the least significant bit always represents the X0 term. It should be noted that the single highest-order term always has a coefficient of 1, so this value is implied and not included in the bit representation of the polynomial. So, p(x) = X3 + X1 + X0 can be written as: Polynomial String=011 where 1X3 is an implied 1, followed by 0X2, 1X1, and 1X0. This string of bits is used to represent polynomials for Fibonacci and Galois implementation. In the CORE Generator GUI and the XCO file, this string is written in hexidecimal: tap_locations=3

Appendix A: LFSR Polynomial NotationA polynomial notation is commonly used to describe the functionality of an LFSR. It should be noted that this convention is frequently ambiguous: presented with a polynomial, there is confusion as to the look of the represented LFSR. It is therefore necessary to define a convention that will be used to describe an LFSR produced by the Xilinx

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Figure 5: Galois Feedback Tap Notation10 www.xilinx.com 1-800-255-7778 DS257 (v1.0) March 28, 2003 Product Specification


XIP172

Figure 6: Galois Implementation of a 3-bit LFSR

Fibonacci-type LFSR NotationFigure 7 illustrates the tap numbering for a Fibonacci-type LFSR. The Gains (X) are binary, either producing a feedback tap or no connection. Figure 8 shows an example of a Fibonacci-type LFSR of length 3, with X0 = 1, X1 = 1, X2 = 0, X3 = 1. The example shown in Figure 8 is represented by the polynomial:

Comparison of Galois/Fibonacci NotationThe highest order factor within a polynomial implies the length of the LFSR. Polynomials representing the LFSR for Figures 5 and 7 contain the term X3 as the highest factor. This implies the length of the LFSR is 3 in both cases. Both polynomials clearly represent the feedback taps when applied to Figures 4 and 6. For the Galois-type LFSR, feedback is in line with the direction of the shift register: feedback tap notation is incremented in line with the shift direction. For the Fibonacci-type LFSR, feedback is in opposition to the direction of the shift register: feedback tap notation decrements in line with the shift direction. This has the advantage of clearly defining the polynomial as implementing either a Galois or a Fibonacci-type LFSR.

p ( x)

X3

X1

X0

This clearly shows the position of the taps to produce the LFSR illustrated in Figure 8. Please note that X0 can again be written as 1. Therefore, alternatively:

p( x)

X3

X1 1

XIP178

Figure 7: Fibonacci Feedback Tap Notation



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XIP179

Figure 8: Fibonacci Implementation of a 3-bit LFSR

Appendix B: Maximum Sequence Length PolynomialsIn order for an LFSR to iterate through its largest possible sequence of values, it must use a polynomial which will produce such a sequence. This maximum length sequence is sometimes also referred to as a Maximal Length Codes. Table 8 shows a sample set of polynomials which will produce maximum sequence lengths for a given LFSR size. These are used as the default polynomial values in the LFSR CORE Generator GUI. The maximum possible number of values which can make up the LFSRs sequence is (2LFSR_SIZE-1). If Maximum Length Logic is used, the maximum possible number of val-

ues in the LFSR sequence increases to (2LFSR_SIZE) (See the section regarding the Maximum Length Logic option for more information). By using the polynomials from Table 8, the LFSR is able to have an ACTUAL sequence length equal to its maximum possible sequence length. Research has been done to determine the fewest number of taps which can be selected for a given-sized LFSR to produce a Maximum Length Sequence. The polynomial used to generate the maximum length sequence is the same for Fibonacci/Galois implementations, and with XOR or XNOR gates for feedback. The following table is incorporated from Xilinx Application Note 210 [5].

Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback LFSR Size (n) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Fibonacci implementation with outputs from registers numbered 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 3 5 6 6 5 7 9 6 4 5 14 15 13 4 16 12 4 3 3 1 1 1 12 13 14 11 12 13 5 4 8 4 Polynomial 1-Terms (Xn) 2 3 4 5 6 7 3 9 10 11 8 10 11 15 3 1 1 1 2 1 1 2 4 3 2 6 9 9 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence Length 3 7 15 31 63 127 255 511 1023 2047 4095 8191 16383 32767 65535

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Linear Feedback Shift Register v3.0 Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued) LFSR Size (n) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Fibonacci implementation with outputs from registers numbered 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 14 11 6 17 19 21 18 23 22 6 5 25 27 6 28 22 20 27 33 25 5 6 35 38 38 41 42 43 44 45 42 47 40 21 20 48 28 20 38 18 42 26 19 37 17 41 25 42 43 44 45 46 23 6 27 4 21 21 19 40 21 4 5 3 1 2 1 37 36 35 38 34 37 2 1 34 33 2 1 32 31 4 1 30 29 2 2 1 1 26 27 25 26 22 17 24 7 2 1 19 18 Polynomial 1-Terms (Xn) 17 18 17 20 21 22 23 2 25 24 25 28 29 26 31 30 33 32 35 36 33 33 39 19 41 22 5 26 3 20 47 27 49 3 7 13 3 2 1 5 1 3 20 22 3 2 24 3 10 13 7 2 11 32 32 4 2 3 1 1 1 1 1 5 1 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence Length 131071 262143 524287 1048575 2097151 4194303 8388607 16777215 33554431 67108863 134217727 268435455 536870911 1073741823 2147483647 4294967295 8589934591 17179869183 34359738367 68719476735 1.37439E+11 2.74878E+11 5.49756E+11 1.09951E+12 2.19902E+12 4.39805E+12 8.79609E+12 1.75922E+13 3.51844E+13 7.03687E+13 1.40737E+14 2.81475E+14 5.6295E+14



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Linear Feedback Shift Register v3.0 Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued) LFSR Size (n) 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Fibonacci implementation with outputs from registers numbered 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 49 50 49 52 53 31 55 50 39 58 59 60 61 62 63 47 65 66 59 67 69 65 66 48 73 74 75 76 77 70 79 77 79 47 44 82 38 43 42 80 38 59 65 41 47 59 58 64 40 46 58 74 75 76 77 78 16 11 36 31 20 25 19 72 53 42 55 40 54 69 70 29 16 57 58 56 57 66 67 10 10 61 60 64 4 46 6 45 5 61 62 16 57 38 37 59 22 35 34 56 22 38 18 37 17 53 54 16 37 24 36 23 35 Polynomial 1-Terms (Xn) 50 51 27 16 26 15 52 15 36 55 21 57 58 21 60 15 56 63 3 65 9 9 68 27 15 71 47 73 15 10 35 30 19 79 37 81 35 1 1 3 1 1 24 1 7 19 1 1 1 1 1 1 18 1 1 9 2 1 6 6 25 1 1 1 1 1 9 1 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence Length 1.1259E+15 2.2518E+15 4.5036E+15 9.0072E+15 1.80144E+16 3.60288E+16 7.20576E+16 1.44115E+17 2.8823E+17 5.76461E+17 1.15292E+18 2.30584E+18 4.61169E+18 9.22337E+18 1.84467E+19 3.68935E+19 7.3787E+19 1.47574E+20 2.95148E+20 5.90296E+20 1.18059E+21 2.36118E+21 4.72237E+21 9.44473E+21 1.88895E+22 3.77789E+22 7.55579E+22 1.51116E+23 3.02231E+23 6.04463E+23 1.20893E+24 2.41785E+24 4.8357E+24

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Linear Feedback Shift Register v3.0 Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued) LFSR Size (n) 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Fibonacci implementation with outputs from registers numbered 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 82 71 84 85 74 87 51 89 90 91 91 73 84 94 91 87 97 63 100 101 94 103 89 91 105 77 108 109 101 110 104 113 114 33 101 32 100 114 115 82 15 69 67 112 45 103 98 102 97 109 110 7 13 44 42 107 65 94 93 104 11 95 36 94 35 101 102 7 67 54 52 99 47 49 47 96 49 72 8 80 71 7 79 90 91 92 19 84 13 17 16 88 72 58 74 57 73 85 86 28 13 38 37 Polynomial 1-Terms (Xn) 83 46 45 84 27 12 87 71 89 18 83 12 93 94 95 47 97 98 45 100 6 66 103 10 105 106 63 108 6 12 111 43 113 81 14 1 13 1 1 13 1 38 1 1 1 2 21 11 2 6 11 2 37 1 1 9 1 16 15 2 31 1 1 10 2 9 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence Length 9.67141E+24 1.93428E+25 3.86856E+25 7.73713E+25 1.54743E+26 3.09485E+26 6.1897E+26 1.23794E+27 2.47588E+27 4.95176E+27 9.90352E+27 1.9807E+28 3.96141E+28 7.92282E+28 1.58456E+29 3.16913E+29 6.33825E+29 1.26765E+30 2.5353E+30 5.0706E+30 1.01412E+31 2.02824E+31 4.05648E+31 8.11296E+31 1.62259E+32 3.24519E+32 6.49037E+32 1.29807E+33 2.59615E+33 5.1923E+33 1.03846E+34 2.07692E+34 4.15384E+34



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Linear Feedback Shift Register v3.0 Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued) LFSR Size (n) 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 Fibonacci implementation with outputs from registers numbered 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 115 115 85 111 113 103 121 121 87 124 125 126 126 124 127 130 103 132 77 124 135 116 137 136 111 140 121 142 143 93 145 146 121 87 110 86 109 146 147 60 38 123 75 122 74 143 144 21 70 110 109 141 32 131 134 130 131 138 139 8 8 11 10 136 126 82 81 133 52 84 83 131 48 101 99 128 29 18 90 17 89 125 126 108 37 63 62 122 60 9 2 120 118 46 99 45 97 Polynomial 1-Terms (Xn) 116 117 71 20 70 18 118 119 111 121 59 123 124 107 36 127 27 129 130 47 132 51 134 135 125 137 7 5 140 31 142 20 69 145 59 37 148 1 2 33 8 7 18 1 2 37 1 1 1 2 5 3 1 29 1 57 11 1 21 1 3 29 1 21 1 1 52 1 1 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence Length 8.30767E+34 1.66153E+35 3.32307E+35 6.64614E+35 1.32923E+36 2.65846E+36 5.31691E+36 1.06338E+37 2.12676E+37 4.25353E+37 8.50706E+37 1.70141E+38 3.40282E+38 6.80565E+38 1.36113E+39 2.72226E+39 5.44452E+39 1.0889E+40 2.17781E+40 4.35561E+40 8.71123E+40 1.74225E+41 3.48449E+41 6.96898E+41 1.3938E+42 2.78759E+42 5.57519E+42 1.11504E+43 2.23007E+43 4.46015E+43 8.9203E+43 1.78406E+44 3.56812E+44

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Linear Feedback Shift Register v3.0 Table 8: Maximum Sequence Length Polynomial/Taps for XOR and XNOR Feedback (Continued) LFSR Size (n) 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Fibonacci implementation with outputs from registers numbered 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 148 97 148 151 152 152 154 155 156 157 128 159 143 161 162 163 164 165 161 166 153 151 168 17 75 104 151 135 128 74 103 150 134 127 162 163 164 165 166 88 60 14 31 39 142 141 160 19 27 124 41 131 132 25 123 40 130 131 154 155 156 157 158 129 32 116 27 27 87 86 152 66 40 39 Polynomial 1-Terms (Xn) 149 110 109 150 151 65 153 127 31 115 26 26 159 18 161 87 59 13 30 38 167 15 1 53 3 1 1 2 1 1 1 1 31 1 18 1 1 1 1 1 6 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sequence Length 7.13624E+44 1.42725E+45 2.8545E+45 5.70899E+45 1.1418E+46 2.2836E+46 4.56719E+46 9.13439E+46 1.82688E+47 3.65375E+47 7.30751E+47 1.4615E+48 2.923E+48 5.84601E+48 1.1692E+49 2.3384E+49 4.67681E+49 9.35361E+49 1.87072E+50 3.74144E+50

Appendix C: Data Valid OutputThe DATA_VALID pin indicates to downstream logic whether the data on the output (SD_OUT or PD_OUT) is valid. Output data is considered valid if: The data was updated on the previous rising clock edge The output is consistent with the previously output values, constituting the next valid value in the PN-sequence.

Asynchronous ResetIf AINIT goes high, it immediately resets the LFSR, also resetting DATA_VALID. DATA_VALID should go low, indicating that the reset value is not the next valid value in the sequence. (Letters are used to show a sequence of values, and do not equate to real values.) An example waveform is shown in Figure 10.

Synchronous ResetIf SINIT is high on the rising edge of the clock, the LFSR registers initialize to their synchronous reset value in the following clock cycle. This constant value is not the next proper value in the sequence for the LFSR, so it is deemed invalid. DATA_VALID should go low, indicating that the reset value is not the next valid value in the sequence. (Letters are used to show a sequence of values, and do not equate to real values.) An example waveform is shown in Figure 11.

Data Valid is effected by CE, AINIT, SINIT, LOAD, and LOAD_TAPS inputs.

Clock EnableIf clock enable goes low, DATA_VALID will go low on the following clock cycle to reflect that the output data has not been updated. An example waveform is shown in Figure 9.



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Figure 9: Example Waveform: Clock Enable effects on DATA_VALID and NEW_SEED

Figure 10: Example Waveform: AINIT effects on DATA_VALID Example

Figure 11: Example Waveform: SINIT effects on DATA_VALID

LoadIf a parallel load is performed, the LFSR is loaded with the parallel load value on the rising edge of the clock. Since the loaded value is out-of-sequence from the preceding output values, the DATA_VALID output goes low for one clock cycle. This indicates to downstream logic that the new value is not a valid member of the preceding sequence. See Figure 12 Example Waveform: Parallel Load with both Serial and Parallel Outputs shown. If the LFSR is Fibonacci with serial input and output, a pseudo-parallel load is possible. A Fibonacci LFSR shifts bits from LSB to MSB without modification. This means that all C_SIZE bits can be shifted into the registers before the effects of this load can be seen on the serial output. On this C_SIZEth clock cycle, the load is completed and the output changes exactly as it would if a parallel load were performed on this last clock cycle. Data valid will go low for only one clock cycle after the load is complete to indicate the presence of a value out-of-order from the previous sequence. If the pseudo-parallel load is not completed, data_valid should go low until a valid value is successfully loaded into the LFSR. An example is shown in Figure 13.

If the LFSR has a serial input, but either has a parallel output or Galois implementation, then a pseudo-parallel load is not possible. This case should be discouraged since it prevents the use of SRL16 primitives. If this case is used, the data_valid should go low from the start of the load until a valid value is successfully loaded into the LFSR (recall that the first value of a new sequence is not considered valid). If a serial load is not completed, data_valid should go low until a valid value is successfully loaded into the LFSR. An example is shown in Figure 14.

Alternate DATA_VALID SignalThe DATA_VALID output of the LFSR considers newly loaded values to be invalid. This is because a newly loaded seed is not the next logical value in the LFSR sequence. If it is desired to consider a newly loaded value (via load, synchronous reset, or asynchronous reset) a valid value, then the output DATA_VALID can be ORed with the NEW_SEED output to produce a new data valid signal which considers new seeds to be valid.

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Figure 12: Example Waveform: Incomplete Serial Load

Figure 13: Example Waveform: Incomplete Pseudo-Parallel Serial Load

Figure 14: Example Waveform: Parallel Load with Serial and Parallel Output (letters are used to show a sequence of values, and do not equate to real values) .

Revision HistoryThe following table shows the revision history for this document. Date 03/28/03 Version 1.0 Initial revision history. Revision



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