1Leonardo Rossi – EB 68 – Oct 5, 2001

Pixel status and schedule

Rad-hard electronics (has always been) on the critical path for the construction of the pixel detector.DMILL technology has proven (contrary to published specs) to be unable to meet pixel requirements (low yield for complex and dense chips).DeepSubMicron (0.25m gate length) technology appears to be able to meet pixel specs (at reduced cost), but transition DMILLDSM has taken ~1.5yrs.Pixel underwent layout modifications to cope with rad-hard electronics delay.This means that pixel detector must be installed “independently” from the rest of the ID (=insertable pixel). While doing this mod we tried to preserve as much as possible all the development work done to date.

I’ll then report on 2 important changes (DSM and Insertable layout) and on progress about the rest of the project, schedule will be illustrated.

2Leonardo Rossi – EB 68 – Oct 5, 2001

After succesfull Rad-soft FE and MCC (demonstrating that ATLAS specifications could be met), Rad-hard development began with Atmel/DMILL in 8/98 back 11/99 with very poor yield. Second run with Atmel (7/00) after investigations and some corrections. One option (FE-D2s) excluding circuit elements sensitive to technology problems but at cost of removing some functionality.Yield of FE-D2S good enough to proceed to build a few active modules and test single-chip, but hopeless for production. Design work stopped for FE and MCC in DMILL in 9/00 and all efforts concentrated on 0.25 process, which is now (10/01) ready for submission.

Lesson 1: for pixel FE (once you have a working chip design) a transition from one technology to another takes 1 to 1.5 yr. A correction cycle in the same technology takes less: 0.6 to 1 yr.

Rad-hard electronics

3Leonardo Rossi – EB 68 – Oct 5, 2001

During 2001 DSM ATLAS pixel design has been characterized with a 20-pixel chip built using both TSCM and IBM foundries.All characteristics (noise, jitter, etc.) are within specs (except threshold dispersion 2x out) and stay ~the same after 50+ Mrad (55 MeV p).FDR passed on June, follow up passed few days ago, submission week43 (22/10). Expect DSM chips back in week51.

Another DSM iteration foreseen (July02) to fix threshold dispersion and possible mistakes in DSM1.In between some small submissions (of critical parts) to secure the DSM2 success.

Finally production should begin in 4/03

4Leonardo Rossi – EB 68 – Oct 5, 2001

The delay of rad-hard electronics implies separate installation of the pixel system. This can be done by permanently installing a CRF tube attached to the barrel ID and then sliding in the pixel system later.

Only the CFR tube must be ready together with the barrel ID.

PP0SCT

TRTTRT

3450

mm 3400mm (end-plug face) Length of service panelPixel + Pigtails

795mm (Barrel Tube half length)

PP1

Insertable layout

5Leonardo Rossi – EB 68 – Oct 5, 2001

Advantages:• flexibility (easier upgrade & repair & coping with production delays)• testability (the full system is tested on surface, then connected at PP1)• smaller system (less (-17%) modules to build)• ID service routing easier (PPB1)

Disadvantages:• pixel installation needs vacuum breaking (2 b_pipes needed) and displacement of a 7.5m long object (SR buildingpit)• pixel (and pixel induced) performance are degraded (more material, some acceptance losses and smaller pixel lever arm)• mechanics more difficult

Advantages outweight disadvantages.

6Leonardo Rossi – EB 68 – Oct 5, 2001

X0 increase (CFR support tube, services along support tube, Al cooling tube inside staves)

DUBNA LAYOUT INSERTABLE LAYOUT

7.5%

Peak due to B-layer services, can be reduced if symmetric B_services are finally chosen

7Leonardo Rossi – EB 68 – Oct 5, 2001

3-hit acceptance losses of 2-3% mostly

•at interface barrel disks (impossible to get disks closer)

• close to =2.5 (disk cannot be smaller as b_layer must slide in)

Acceptance losses

8Leonardo Rossi – EB 68 – Oct 5, 2001

Pixel system is squeezed (inward:Rout 14.2 12.2 cm and outward:Rin 4 5 cm in barrel) and shortened. The number of disks is reduced (5 3)

130 cm130 cm

Longitudinal viewLongitudinal view Barrel Transverse viewBarrel Transverse view

9Leonardo Rossi – EB 68 – Oct 5, 2001

IP resolution degrades for low pT tracks (Rin increase), but stays the same for high pT tracks.

b-tagging is marginally affected, layer1 is the less critical (results depend on sw tuning)

No final results on EM Calo yet (about to come).

1 GeV

MH(400 GeV)

Phys TDR: Ru=18317 for b=50%

Ru= 805 for b=60%

10Leonardo Rossi – EB 68 – Oct 5, 2001

Progress on mechanics

PRR on local supports passed on July (both supports use C-C supports and Al cooling

tubes), production started (material procurement and part fabrication) for all layers. Good progress on support tube and global pixel support, ready for launching Insertable ECR by mid-October

Bi-stave Assembly

Sector Assembly

11Leonardo Rossi – EB 68 – Oct 5, 2001

Progress on sensors

Preproduction (75CiS+75Tesla good tiles) done. Oxygenated moderated p-spray.Tesla delivery slower, quality acceptable, final irradiation studies underwayGood agreement between firms and lab acceptance measurements.Production DataBase in operation in all sensor labs Ready to go for 2000 tiles production (within CORE boundaries), must start soon as production rate is limited.

TeslaTesla CisCis Bad tiles (vendor test)Bad tiles (vendor test)

12Leonardo Rossi – EB 68 – Oct 5, 2001

Progress on hybridisation

Module is made out of a bare module ( sensor tile +16 chips flip-chipped on) and flex circuit (+MCC). FDR of bare module and flex passed (8/00&12/00).Three generations of flex approaching final layout, 4th ongoing, then preproduction (7/02).Progress on modules slowed down due to missing electronics (4 modules done with DMILL). 100 dummy modules in fab. to check bumping firms + jigs in labs + technical staff and procedures in labs/firms. 8” bumping in hand.

Bare Bare modulemodule

MCCMCC

FlexFlex module module

MCCMCC

1999

2000

2001

13Leonardo Rossi – EB 68 – Oct 5, 2001

Progress on local services

Taiwan optopackage chosen (6/01), progress on optochips (DORIC and VDC) satisfactory. Both DMILL and DSM can be used, we prefer a unique technology for all rad-hard electronics.Decided to place optolinks at PP0 (fibre routing & optical connectivity).

Progress on pigatils: prototypes with microAl cables under construction (need special wirebonding machines available to the collaboration).

Design of power supply system with rad-hard voltage regulators is ongoing (need ST regulators).

14Leonardo Rossi – EB 68 – Oct 5, 2001

Global schedule

15Leonardo Rossi – EB 68 – Oct 5, 2001

Sensor production schedule

16Leonardo Rossi – EB 68 – Oct 5, 2001

Electronics production schedule

17Leonardo Rossi – EB 68 – Oct 5, 2001

Module production schedule

18Leonardo Rossi – EB 68 – Oct 5, 2001

Module production schedule (cont.)

19Leonardo Rossi – EB 68 – Oct 5, 2001

Installation schedule

20Leonardo Rossi – EB 68 – Oct 5, 2001

Final comments

Schedule can be “certified” only after some (25%?) production Hard to meet the pilot run (even with 2 layers), is it worth? Installation time before the 1st physics run long enough? Time window for pixel available there?

Insertable layout cannot be avoided, must go through ECR soon.

To proceed along this line we need to be assured that: in-situ beam pipe baking is possible (double wall pipe) a 7.5 m long object can be installed during shut down effects in EM Calo are acceptable activation does not prevent insertable layout installation/dismount