LEON3 © 2005 GE-Research Products · Advantages · Solutions With explicit permission of Gaisler...
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Transcript of LEON3 © 2005 GE-Research Products · Advantages · Solutions With explicit permission of Gaisler...
LEON3
© 2005GE-Research
Products · Advantages · Solutions
With explicit permission of Gaisler Research
LEON3 V0105 dsr 2 von 15
COMPANY INFORMATION
• Located in Gothenburg, Sweden
• Private Company
• Management team with 40 years combined experience in the space sector:– Per Danielsson: CEO– Jiri Gaisler: Founder and CTO– Sandi Habinc: System Design
• Design engineers with expertise within electronics, ASIC and software design
• Complete design facilities in-house for ASIC and FPGA design
Gaisler Research
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THE HISTORY OF ERC32 AND LEON
20022002
• Continuous development of IP blocks for LEON, FPU is released • Revenue of Gaisler Research is increasing• ASIC designers are hired
• ERC32 development starts, Jiri Gaisler is the technical officer at ESA 19921992
• ERC32 is released as a 3 chip solution19961996
• Development of LEON starts19971997
• LEON2-FT is manufactured by UMC• Commercial companies use the LEON2-STD
19991999 • LEON1 source code released• ERC32 single chip available
20012001 • LEON2 with on chip AMBA source code is released• LEON1 prototype
Gaisler Research is founded
20032003
20042004• Release of next generation processor LEON3• New plug & play concept for SOC design• IP-library (GRLIB) with blocks connecting on the AMBA bus
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PRODUCT PORTFOLIO
• LEON3 processor, STD/FT• LEON compatible IP-blocks:
– GRFPU, Floating Point Unit– SDRAM controller– PCI bridge– 10/100 Mbit Ethernet MAC
• LEON development boards• Technical support and adaptations• Full software development environment
based on open source tools
• TSIM, ERC32 and LEON simulator• GRMON, LEON Debug monitor
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LEON FEATURES
Simple Integration
Open Source Standard SW Environment
Open Source Standard SW Environment
GNU C/C++ compiler RTEMS real-time kernel eCos real-time kernel SnapGear Linux
High PerformanceHigh Performance
400 MHz on UMC 0.13 µm ASIC (std-cell)
125 MHz on ALTERA Stratix II FPGA Low Gate CountLow Gate Count
25 kgates for ASIC 3,500 LUT for Altera FPGA 4,000 Cells for Actel FPGA
Full Simulator and Debug Monitor
Full Simulator and Debug Monitor
Simulator for developing and debugging SW
Monitor for HW and SW validation
IP-Library of Cores for SOC Design
IP-Library of Cores for SOC Design
Portable and Vendor independent
Connection through standard AMBA bus
Customer Approval and Validation
Customer Approval and Validation
LEON is the standard processor of ESA
Numerous commercial customers are using LEON
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BUSINESS MODEL
Development Of New Product
Beta Version Release Open
Source License
Community Feedback
Product Improvements
Final Version Open Source and
Commercial License
Commercial Sales Funds Further Development
Gaisler Research uses an open source business model based on Dual Licensing. Dual licensing allows to provide commercial licenses for a fee, while at the same time offering the source code under open source licenses.
• Free access for the academic research community• Free evaluation possibilities for companies• Large user base gives sizeable and quick feedback• Commercial licences for IP cores to companies not willing
to comply with the GPL licence• Commercial licences for the LEON3 FT IP core library• Provide technical support and development tools
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MARKET AND APPLICATIONS
Commercial
CriticalCommercial
Civil Aircraft
LEON3GRLIB
Military
Space
FT
FT
FT
FT
STD
The Fault Tolerant (FT) version is used for critical, military and aerospace applications
The Standard version (Non-FT) is used for commercial applications
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CUSTOMERS contINUED
• Commercial– GPS receiver (Taiwan, Switzerland)– MP3 player (Taiwan)– Set top boxes (France, Germany, Canada)– Automotive (Germany)– Router (Australia)– DVD-DIVX converter (US)
• Military– Used by companies in US, France, Israel
• Space– All European space companies– US, China, Canada, Korea, Israel, India, Brazil
• Research and Universities– Used by hundreds of universities and research centres around the world
Customer identities can not be disclosed due to NDA’s
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COMPETITORS
PRODUCT ARM 9 ARM 11 ARC 700 Xtensa LX LEON3
Clock frequency (MHz) 250 400 400 350 400
Pipe-line stages 5 8 7 5 7
Gate count > 100’000 > 100’000 100’000 28’000 25’000
Synthesizable to FPGA No No Yes Yes Yes
Third party SW development tools
Yes Yes No No Yes
Open Source VHDL No No No No Yes
License Cost High High Medium Medium Low
Clock frequency: Depends on process and technology, figures are approximate for 0.13 µm process
Gate count: Depends on processor configuration, figures are for bare processor
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• Developed and validated for space use (FT-version)
• High performance (400 MHz on 0.13 µm process)
• Optimized for embedded real time systems
• IP library with co-processors and peripherals available
• Plug&play capabilities for system on a chip design
• Synthesizable, available in full VHDL source code
• Tool and vendor independent
Some advantages of LEON3 (1)
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Some advantages of LEON3 (2)
• Standard CPU (SPARC8), standard bus system (AMBA2.0)
• Complete set of macros available (click & synthesize)
• Large user community
• Operating system LINUX and different RTOS available
• Many years of experience guarantees a minimum number of bugs.
• Every ARM user is a potential LEON client, specially for FPGA’s
• …
LEON3 V0105 dsr 12 von 15
Next steps at Gleichmann Research
• Implementation of LEON3 system on Hpe_mini LEC
• Synthesis for high speed solution
• Adaption of Snapgear Linux (with and without MMU
• Evaluation of multiprocessor System
• Adaptation and check of multi processor Linux
• Implementation of different system solutions like PCIe, LCD controller, motor control …