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MICROELECTRONICS LAB

Integrated Circuits Design

Session 1

Eng. Mona ElGuindy

Dr. Ahmed Madian

Faculty of Information Engineering and Technology-IET

Electronics Department

AGENDA

Combinational MOS Logic Circuits

Stick Diagrams

CMOS Layout

Layout Rules

LEDIT



COMBINATIONAL MOS LOGIC CIRCUITS

Two input NOR Gate with depletion NMOS loads




Two input NOR Gate using CMOS




Two input NAND Gate with depletion NMOS

loads




Two input NAND Gate using CMOS



COMPLICATED LOGIC GATES USING CMOS

E=((A.B)+(C.D))



STICK DIAGRAMS

Stick diagrams convey layer information into

color code

How to draw a stick diagram?

Start by drawing two long horizontal lines

representing P and N diffusion used to make the

transistor

Then, Draw a vertical line for each input, these

vertical lines should cross the horizontal lines.

Now, we have a transistor.



STICK DIAGRAM FOR A CMOS INVERTER

We will start by drawing the two horizontal

lines (N and P diffusion) ,then, we will draw

the vertical line, one for each input (we have

one input Vin). We will now have one PMOS

transistors and one NMOS transistor.




Looking to NMOS connections, we can see that

the transistor is connected to the ground from

one side and Vout on the other side.




For the PMOS, the drain of the PMOS is

connected to the drain of NMOS , both are

connected to Vout , while its source is

connected to connected to VDD.



STICK DIAGRAM FOR 2-INPUT NOR GATE

Similarly, We will start by drawing the two

horizontal lines (N and P diffusion) ,then, we

will draw the vertical line, one for each input

(we have two inputs A and B). We will now

have two PMOS transistors and two NMOS

transistors




Looking to NMOS connections, we can see that

both transistors are connected to the ground

on one side and Vout on the other side.




For the PMOS, the drain of input A is connected

to Vout from one side while its source is

connected to input B. Finally input B is

connected to VDD.



CMOS LAYOUT

Creating a layout is very similar to stickdiagrams. The difference is that a layout is athick stick diagram. The diffusions (P and N),the poly used for the gate, and the metalsused for interconnections all have a specificwidth.



CROSS SECTION OF CMOS TECHNOLOGY



WHAT ARE THE DESIGN RULES TO DRAW A

LAYOUT?

The design rules are the interface between

design and process engineers.

Guidelines for constructing process masks

Design rules must be respected by the designer

Design rules reflect the limit of a process,

where they describe

Minimum width, minimum distance, overlap

Unit dimension: Lambda parameter



CMOS PROCESS LAYERS

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green



LAYOUT RULES

P-substrate

nWell

Active

Poly

P select

N select

Active contact

Poly contact

Metal 1

Via

Metal 2



LAYOUT RULES

Layer Type of Rule Value

Well Minimum width 12

Poly Minimum width

Minimum spacing

2

2

Active Minimum width

Minimum spacing

3

3

N select Minimum width

Minimum spacing

3

3

Metal 1 Minimum width

Minimum spacing

3

3

Metal 2 Minimum width

Minimum spacing

3

4

Layer X

Layer X

Minimum spacing

Minimum Width



LAYOUT RULES

Layer Type of Rule Value

Poly overlap Minimum extension over

Active

2

Poly - Active Minimum spacing 1

Active

Contact

Exact size 2 * 2

Active

contact

Minimum space to active

edge

2

Poly Contact Exact Size 2 * 2

Poly Contact Minimum space to poly edge 2



L-EDIT TOOL



Click: file New

Browse: LEDIT83 Samples Tech mosis mhp_ns5.tdb



Create a new cell: From the menu choose

Cell New



SETTING UP THE GRID

Menu: Setup Design

Technology name:SCN3MSUB

1 lambda=1/4



Go to grid tab where grid step should be 1

lambda



CMOS LAYOUT

Develop a suitable layout with 0.25m

technology using the following aspect ratios:

(W/L)N = 1m/0.5m and (W/L)P = 2m/0.5m



We first start by drawing the active (n+, p+)

As we need to have a PMOS with w=2u and we

are working with an 0.25m, therefore, the p+

region has to be 8

CMOS LAYOUT

8



CMOS LAYOUT

Then drawing that of NMOS equal to 1m.

Therefore equal to 4



CMOS LAYOUT

Moving to drawing the NSELECT and PSELECT



CMOS LAYOUT

As in the fabrication of CMOS the P+ is placed

into an NWELL



CMOS LAYOUT

Moving to the gate which has a length of

0.5m. Therefore, 2



CMOS LAYOUT

Making metal connections, and placing the

active contacts



FINAL CMOS LAYOUT



SOME NOTES

The contact for the gate is a poly contact not an

active contact.

The intersection between the active (n+, or p+) is

very important as it controls the channel width and

length and has to be very accurate.

You can check for your layout using the

DRC(Design rules check ) icon present in the

toolbar.

The extraction is done through the extraction icon

Errors

checkExtraction



THANKYOU

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