Lecture8-Wires-Transistorsbwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s10/Lectures/Lecture8... ·...

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EE141 EECS141 1 Lecture #8


  Hw 3 due today – HW 4 to be posted   No Lab next week   Extra review session Th at 6:30pm

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 Last lecture   Logical Effort + Wires

 Today’s lecture  Wiring (cntd) – Transistor models

 Reading (Ch 3, 4)


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 Use Better Interconnect Materials   e.g. copper, silicides

 More Interconnect Layers   reduce average wire-length

 Selective Technology Scaling   (More later)


Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

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What to do with the resistance?


•  Analysis method: •  Break the wire up into segments of length dx •  Each segment has resistance (r dx) and capacitance (c dx)

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The diffusion equation


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•  “Elmore delay”: approximation for delay of arbitrary (complex) RC circuits •  To find “Elmore time constant”:

•  For each capacitor, draw path of current from cap to input •  Multiply C by sum of R’s on current path that are common with path from Vin to Vout •  Add up RC products from all capacitors


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Model the wire with N equal-length segments:

For large values of N:


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CN-1 CN C2

R1 R2

C1

Tr

Vin

RN-1 RN

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Challenges   No further improvements to be expected after the

introduction of Copper (superconducting, optical?)   Design solutions

  Use of fat wires   Efficient chip floorplanning   Insert repeaters

( ) out w w d out d w w d C R C R C R C R T + + + = 693 . 0 377 . 0


# of metal layers is steadily increasing due to:"•  Increasing die size and device count: we need more wires and longer wires to connect everything

•  Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC

0.25 µm wiring stack

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Driver Polysilicon word line

Polysilicon word line

Metal word line

Metal bypass

Driving a word line from both sides

Using a metal bypass

WL

WL K cells


Repeater

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Taking the repeater loading into account

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What do digital IC designers need to know?


  With positive gate bias, electrons pulled toward the gate   With large enough bias, enough electrons will be pulled to "invert"

the surface (p→n type)   Voltage at which surface inverts: “magic” threshold voltage VT

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 Threshold

 Fermi potential

2ΦF is approximately 0.6V for p-type substrates γ is the body factor VT0 is approximately 0.45V for our process

Depletion charge


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Pinch-off

0< VGS - VT < VDS


  For (VGS – VT) < VDS, the effective drain voltage and current saturate:

’

  Of course, real drain current isn’t totally independent of VDS   For example, approx. for channel-length modulation:

’

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Cutoff: VGS -VT< 0

Linear (Resistive): VGS-VT > VDS

Saturation: 0 < VGS-VT < VDS

’

’


Quadratic Relationship

0 0.5 1 1.5 2 2.5 0

1

2

3

4

5

6 x 10 -4

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

VDS (V)

I D (A

)

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Linear Relationship

-4

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5 x 10

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

VDS (V)

I D (A

)


ξ (V/µm)

υ n

( m / s

)

υ sat = 10 5

Constant mobility "(slope = µ)

Constant velocity

ξ c

  Velocity saturates due to carrier scattering effects

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I D Long-channel device

Short-channel device

V DS V DSAT V GS - V T

V GS = V DD


0 0.5 1 1.5 2 2.5 0

1

2

3

4

5

6 x 10 -4

V GS (V)

I D (A

)

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5 x 10 -4

V GS (V)

I D (A)

quadratic

quadratic

linear

Long Channel"(L=2.5µm)

Short Channel"(L=0.25µm)

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