Lecture_7 of HR
Transcript of Lecture_7 of HR
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Advanced Computer Architecture
Digital Building Blocks-II
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Sequential Building Block
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Counters
Increments on each clock edge.
Used to cycle through numbers. For example,
000, 001, 010, 011, 100, 101, 110, 111, 000, 001
Example uses:
Digital clock displays
Program counter: keeps track of current instruction executing
Q
CLK
Reset
N
+N
1
CLK
Reset
N
N
QN
r
S y m b o l Imp lementa t ion
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Excitation Table Excitation table lists required inputs of flip-flops that will cause
necessary transition from present state to next state.
Present Next flip-flop JK SR D TState State
Q(t) Q(t+1) Input J K S R D T
0 0 0 X 0 X 0 00 1 1 X 1 0 1 1
1 0 X 1 0 1 0 1
1 1 X 0 X 0 1 0
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Analysis of Combinational vs SequentialCircuits
Combinational
Boolean Equations
Truth Table
Output as a function ofinputs
Sequential
State Equations
State Table
State Diagram
Output as a function of
input and current state
Next state as a functionof inputs and current
state.
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State Equations An algebraic expression assigning the next state of the flip-flop in
terms of the present state and input conditions of the machine isreferred to as a state equation. This equation is a Booleanexpression that specifies the present state and input conditions.
Fig shows a sequential circuit that has one full adder, one D flip-flip,two inputs x, y and output S. This circuit is an implementation ofserial adder.
Full Adder
D F/F
X
Y
Z
Q
S
C
D
Clock Pulse
Next state equation: Q(t+1)=D(t)=C(t)
Sum (S) :S(t) = X(t) Y(t) Q(t)
Carry (C) outputC(t)= X(t)Y(t) + X(t) Q(t) + Y(t)Q(t)
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State Table
Time sequence of inputs, outputs, and internal states offlip-flop can be described in a table called state table
Full Adder
D F/F
X
Y
Z
Q
S
C
D
Clock Pulse
Present Input Next State Output
Z XY Z S
0 0 0 0 0
1 0 0 0 10 0 1 0 1
1 0 1 1 0
0 1 0 0 1
1 1 0 1 0
0 1 1 1 01 1 1 1 1
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State Table
Entries in the next state sections define the necessarystate transition of the circuit and also specify the nextvalue of the output Q(t+1) of the flip-flop. This table is
also called transition table
Present State Next state, Z Output S
Z XY = 00 01 10 11 XY = 00 01 10 11
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
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State Diagram
Inputs, outputs and flip-flop states can be representedgraphically in a directed graph. This graph is known as
state diagram or state graph.
A state is represented by a circle (also called as vertices)
State transition is indicated by directed lines or arcs
connecting the vertices.
00/0 11/0
01/1
10/1 01/0
10/0
00/1 11/1
01
Present State Next state, Z Output SZ XY = 00 01 10 11 XY = 00 01 10 11
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
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STATE REDUCTION
State-reduction technique reduces number of states in a state
table while keeping the external input-output requirements
unchanged
mflip-flops produce 2mstates and a reduction in the number of
states may or may not result in a reduction in number of flip-
flops
State reduction is the process to develop compact state
diagrams and avoid the introduction of redundant states
If two states x and y are equivalent, then state y is called asredundant. Two states x and y of a finite state machine are
defined to be equivalentwhen the machine is started in these
states and the identical output sequences are generated from
every possible set of input sequences that can be applied
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STATE REDUCTION
0/0 1/1 0/1 0/0 0/0
ce
f
b
a
gd
1/01/0
0/0
1/1
1/0 0/0 1/0
0/1
1/0
State Diagram
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STATE REDUCTION
Present Next State Output
State X=0 X=1 X=0 X=1
a b c 0 0
b d e 0 0
c g f 0 0d a a 0 1
e a a 1 0
f a a 0 1
g a a 1 0
State Table
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STATE REDUCTION
Present Next State Output
State X=0 X=1 X=0 X=1
a b c 0 0
b d e 0 0
c g e f d 0 0d a a 0 1
e a a 1 0
f a a 0 1 X
g a a 1 0 X
State table shows removal and replacement of the states
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STATE REDUCTION
Present Next State Output
State X=0 X=1 X=0 X=1
a b c 0 0
b d e 0 0
c e d 0 0d a a 0 1
e a a 1 0
Reduced State table
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STATE REDUCTION
a
cb
e
d
0/1
1/0
1/0
0/0
0/0 1/0
0/0 0/0 1/0
1/1
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STATE REDUCTION
State a b c d e
Assignment-I 000 001 010 011 100
Assignment-II 001 011 101 100 111
Assignment-III 000 010 100 110 111
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STATE REDUCTION
Present Next State Output
State X=0 X=1 X=0 X=1000 001 010 0 0
001 011 100 0 0
010 100 011 0 0
011 000 000 0 1
100 000 000 1 0
Reduced State Table with Binary Assignment
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DESIGN METHOD
Synchronous sequential circuit:- flip-flops and
combinational gates
Design of circuit includes selection of flip-flops andfinding of combinational gate structure
Number of states needed in the circuit determines the
number of flip-flops and combinational circuit is derivedfrom state table
After selection of type and number of flip-flops, the
techniques of combinational-circuit design can be applied to
design combinational circuit. A combinational circuit is
fully specified by a truth table, a sequential circuit requires
a state table for its specification
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DESIGN METHOD
A sequential circuit has been described in state diagram. The
design uses D flip-flop. Circuit has four states. Binary values
have already been assigned to the states. From the state diagram,
it is seen that the circuit has one input variable and no outputvariables because the directed lines are marked with a single digit
without a slash. Two D flip-flops (A and B) are needed to
represent four states. Input variable is designated x.
0010
01
11
0 1 0
1 1
0 1
0
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DESIGN METHOD
0010
01
11
0 1 0
1 1
0 1
0
Present state Next State
X=0 X=1
AB AB AB
00 00 01
01 01 11
10 10 00
11 11 10
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DESIGN METHOD
State Transition
00 01 10 11
D input 0 1 0 1
Table: Excitation of D flip-flop
Present
State Input Next State F/F Inputs
A B X A B DA DB0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 1 0 1
0 1 1 1 1 1 11 0 0 1 0 1 0
1 0 1 0 0 0 0
1 1 0 1 1 1 1
1 1 1 1 0 1 0
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DESIGN METHOD
0 0 1 0
1 0 1 1
0 1 1 1
0 0 0 1
DA=Ax + Bx DB=Ax + Bx
A Bx Bx Bx BxA Bx Bx Bx Bx
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DESIGN METHOD
DA Q
Q
DB Q
Q
A
A
BB
Combinational
X
DA=Ax
+ Bx DB=A
x + Bx
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DESIGN METHOD
State Transition
00 01 10 11
J 0 1 x x
K x x 1 0
Table: Excitation of JK flip-flop
Present F/F Inputs
State Input Next State A F/F B F/FA B X A B JA KA JB KB
0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 x 1 x
0 1 0 0 1 0 x x 0
0 1 1 1 1 1 x x 0
1 0 0 1 0 x 0 0 x
1 0 1 0 0 x 1 0 x
1 1 0 1 1 x 0 x 0
1 1 1 1 0 x 0 x 1
Excitation table of the sequential circuit
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DESIGN METHOD
JB=Ax KB=Ax
0 0 1 0
x x x x
x x 0 0
x x 1 0
x x x x
0 1 0 0
0 1 x x
0 0 x x
JA=Bx KA=B
x
A Bx Bx Bx BxA Bx Bx Bx Bx
A Bx Bx Bx BxA Bx Bx Bx Bx
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DESIGN METHOD
A
A
B
B
Combinational
XJA Q
KA Q
JB Q
KB Q
JB=Ax KB=Ax
JA=Bx KA=Bx
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DESIGN METHOD
F/F Input State Transition
00 01 10 11
T 0 1 1 0
Table: Excitation of T flip-flop
Present
State Input Next State F/F Inputs
A B X A B TA TB0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 1 0 0
0 1 1 1 1 1 0
1 0 0 1 0 0 01 0 1 0 0 1 0
1 1 0 1 1 0 0
1 1 1 1 0 0 1
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DESIGN METHOD
0 0 0
0 0 0
1
1
0 0 0
0 0 0
1
1
A B
x
B
x Bx Bx
A B
x
B
x Bx Bx
TA= ABx + ABx TB= A Bx+ABx
=(AB) x =(AB) x
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DESIGN METHOD
A
A
B
B
Combinational
X TA Q
Q
TB Q
Q
TA= ABx + ABx Clock TB= A Bx+ABx
=(AB) x =(AB) x
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DESIGN METHOD
Present F/F Inputs
State Input Next State A F/F B F/F
A B X A B SA RA SB RB
0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 x 1 0
0 1 0 0 1 0 x x 0
0 1 1 1 1 1 0 x 01 0 0 1 0 x 0 0 x
1 0 1 0 0 0 1 0 x
1 1 0 1 1 x 0 x 0
1 1 1 1 0 x 0 0 1
State Transition
00 01 10 11
J 0 1 0 x
K x 0 1 0
Table: Excitation of SR flip-flop
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DESIGN METHOD
X
SA=Bx RA=Bx
0 0 1 0
x 0 x x
x x 0 0
x x 1 0
x x 0 x
0 1 0 0
0 1 x x
0 0 x x
SB=A
x RB=Ax
A Bx Bx Bx BxA Bx Bx Bx Bx
A Bx Bx Bx BxA Bx Bx Bx Bx
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DESIGN METHOD
A
A
B
B
Combinational
X
SA Q
RA Q
SB Q
RB Q
SA=Bx Clock RA=Bx
SB=Ax RB=Ax
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Digital Counter Design
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Digital Counter
used to record number of occurrences of input or to generate
the timing sequences to control operations in the digital
computers
Flip-flops are the main components for building a counter
Two categories; ripple or synchronous counter.
synchronous circuits are clocked i.e. work only on the arrival of
a signal pulse
ripple or asynchronous circuits are not clocked and do not need
a clock pulse to work i.e. the flip-flop output transition serves
as a source for triggering other flip-flop.
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Digital Counter
Counters in which the output of one F/F drives another are
called ripple counter or asynchronous counter
Ripple counters are constructed by using T F/Fs or JK flip-flop
with J & K leads shorted
F/Fs are cascaded in series.
They are triggered asynchronously
Output of one F/F drives the input of the next F/F. As the
triggering pulse moves from one F/F to another F/F like a
ripple in water, these counters are called ripple counters.
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Digital Counter
Counters are identified by their modulus abbreviated as MOD
Modulus of a counter is expressed by total number of countsthat can be made by that counter or total number of states
through which counter goes before resetting
A binary counter having n flip-flops has 2ntotal counts or states
and it has 2nmodulus. It is termed as mod- 2ncounter. A mod-2 counter counts two states and uses one flip-flop, a
mod-4 counter uses two flip-flops and counts 4 pulses, a mod-8
counter uses 3 flip-flops and counts 8 states or pulses.
Counter, which counts states greater than 2nbut less than 2n+1
requires n+1 number of flip-flop. For example, mod 5 counter
that counts 5 states from 0 to 4 uses (22
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Digital Counter
Ripple counters are not state machines, although they use
sequential logic.
Synchronous counters are state machines. Synchronous
counters of any type can be designed using the state machine
design method.
Asynchronous counters suffer from the lower speed of
operation
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Digital Counter
Ripple Counter
Ripple counter consists of cascaded JK F/Fs with JK leadwired high
Output of each F/F is connected to CLK input of next F/F.
F/F generating least significant bit of count receives input
clock from clock generator
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Mod-4 Ripple Counter
Mod-4 that counts through 4 different states. All J and K inputs
are connected to 1.
Bubbles in clock input of each F/F indicates that F/Fs changes
its state on a negative-going transition i.e. when a transition
from 1 in present to 0 in next state of a F/F occurs, the state of
next F/F will change.
Sequence of mod-4 ripple counter is 0->1->2->3->0
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Mod-4 Ripple Counter
Mod-4 that counts through 4 different states. All J and K inputs
are connected to 1.
Bubbles in clock input of each F/F indicates that F/Fs changes
its state on a negative-going transition i.e. when a transition
from 1 in present to 0 in next state of a F/F occurs, the state of
next F/F will change.
Sequence of mod-4 ripple counter is 0->1->2->3->0
DESIGN METHOD
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DESIGN METHOD
State Transition
00 01 10 11
D input 0 1 0 1
Table: Excitation of D flip-flop
State Transition
0
0 0
1 1
0 1
1J 0 1 x x
K x x 1 0
Table: Excitation of JK flip-flop
F/F Input State Transition
00 01 10 11
T 0 1 1 0
Table: Excitation of T flip-flop
MOD 4 ripple counter
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MOD-4 ripple counter
Count Decimal
SequenceA B
0 0 0
0 1 1
1 0 21 1 3
QB 0 1 0 1 0
QA 0 0 1 0 0
J K
B
Q Q
J K
A
Q Q
Input Clock Pulse
1
Sequence Table
Timing Diagram of MOD-4 ripple counter
Input clock
MOD 8 ripple counter
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MOD-8 ripple counter
J K
C
Q Q
J K
B
Q Q
J K
A
Q Q
Input Clock Pulse
1 Count DecimalSequence
A B C0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7Input clock
QC 0 1 0 1 0 1 0 1
QB 0 0 1 1 0 0 1 1
QA 0 0 0 0 1 1 1 1
MOD 16 ripple counter
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MOD-16 ripple counter
Input clock
QC 0 1 0 1 0 1 0 1
QB 0 0 1 1 0 0 1 1
QA 0 0 0 0 1 1 1 1
J K
D
Q Q
J K
C
Q Q
Input Clock Pulse
1
J K
B
Q Q
J K
A
Q Q
MOD 3 ripple counter
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MOD-3 ripple counter
0
2 1
A B Reset
0 0 0
0 1 0
1 0 0
1 1 1
1
Reset=ABState Diagram Truth Table K-Map
B B
A
A
J K
B
Q Q
J K
A
Q Q
Count Decimal
SequenceA B
0 0 0
0 1 1
1 0 2
1 1 3
Input Clock
QB 0 1 0 0 1 0 0
QA 0 0 1 0 0 1 0
Resetf) Timing
MOD 5 ripple counter
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MOD-5 ripple counter
Reset=AB
State Diagram Truth Table K-Map
0
3
1 2
4
A B C Reset
000 0
001 0
010 0
011 0
100 0
101 1110 X
111 X
1 X X
BC BC BC BC
A
A
J K
C
Q Q
J K
B
Q Q
J K
A
Q Q
Input Clock Pulse
1
MOD-10 Ripple Counter
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MOD-10 Ripple Counter0 31 2
9 78
4
6 5
A B C D Reset
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 00 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 01 0 1 0 1
1 0 1 1 X
1 1 0 0 X
1 1 0 1 X
1 1 1 0 X
1 1 1 1 X
X X
X 1
Reset=AC Reset = AC
MOD-10 Ripple Counter
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MOD-10 Ripple Counter
Reset=AC Reset = AC
J K
D
Q Q
J K
C
Q Q
J K
B
Q Q
J K
A
Q Q
Input Clock Pulse
1
MOD-14 Ripple Counter
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MOD-14 Ripple Counter
0 31 2
97
8
4 65
101112
2
13
A B C D Reset
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 00 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 X
X 1
Reset=ABC Reset = ABC
MOD-14 Ripple Counter
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MOD 14 Ripple Counter
Reset=ABC Reset = ABC
J KD
Q Q
J KC
Q Q
J KB
Q Q
J KA
Q Q
Input Clock Pulse
1
Synchronous Counter
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Synchronous Counter
Normal synchronous state machines
Normally edge triggered D or JK flip-flops are used as memory
devices
All the flip-flops are triggered synchronously by input pulse
from a master clock generator
Ripple counter connects all CLK leads to an outputs of the
previous stage
Clock signals from a common clock source are applied to CLK
leads of all the flip-flops in synchronous counter at a time. For
this reason, this type of counter is often called a parallel counter.
Synchronous Counter
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Synchronous Counter
Combinational Logic
J K
1stF/F
Q Q
J K
2ndF/F
Q Q
J K
(n-1)th F/F
Q Q
J K
nth F/F
Q Q
clock
Mod-4 Synchronous Counter
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y
0
3 2
1
Present Next Flip-flops input
State State
A B A B JA KA JBKB
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 11 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
1
X XX X
1
1 X
1 X
X 1
X 1
JA=B KA=B
JB=1 KB=1
Mod-4 Synchronous Counter
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y
J K
B
Q Q
J K
A
Q Q
Clock
1
CLR
Mod-8 Synchronous Counter
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y
1 2
37
0
6 45
Present Next Flip-Flop Inputs
State State A F/F B F/F C F/FA B C A B C JAKA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
0 0 1 0
x x x x
x x x x
0 0 1 0
JA=BC KA=BC
State diagram Excitation Table of the sequential circuit
Mod-8 Synchronous Counter
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y
JC=1 KC=1
0 1 x x
0 1 x x
x x 1 0
x x 1 0
JB=C KB=C
1 x x 1
1 x x 1
x 1 1 x
x 1 1 x
Mod-8 Synchronous Counter
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JA=KA=BC JB=KB=C JC=KC=1
J K
C
Q Q
J K
B
Q Q
J K
A
Q Q
Clock
1
CLR
Mod-8 Synchronous Counter
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6 5
40
7
1 32
Present Next Flip-Flop InputsState State A F/F B F/F C F/F
A B C A B C JAKA JB KB JC KC
1 1 1 1 1 0 X 0 X 0 X 11 1 0 1 0 1 X 0 X 1 1 X1 0 1 1 0 0 X 0 0 X X 11 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 1 1 1 X 1 X 1 X
1 0 0 0
x x x x
x x x x
1 0 0 0
JA=BC KA=BC
Mod-8 Synchronous Down Counter
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Mod 8 Synchronous Down Counter
JC=1 KC=1
1 0 x x
1 0 x x
x x 0 1
x x 0 1
JB=C KB=C
1 X X X
1 X X 1
X 1 1 X
X 1 1 X
Mod-8 Synchronous Down Counter
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Clock
1
CLR
J K
C
Q Q
J K
B
Q Q
J K
A
Q Q
MOD-5 synchronous counter
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0
3
1 2
4
PS NS F/F InputsA B C A B C JAKA JBKB JCKC
000 001 0 X 0 X 1 X
001 010 0 X 1 X X 1
010 011 0 X X 0 1 X
011 100 1 X X 1 X 1
100 000 X 1 0 X 0 X
000
0 0 1 0
X X X X
X X X X
1 X X X
JA=BC KA=1
MOD-5 synchronous counter
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X 1 1 X
X X X X
JC=A KC=1
0 1 x x
0 x x x
x x 1 0
x x x x
1 x x 1
0 x x x
JB=C KB=C
MOD-5 synchronous counter
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Vcc
Clock
CLR
J K
C
Q Q
J K
B
Q Q
J K
A
Q Q
Shift Register
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NQ
Sin
Sout
Symbol: Implementation:CLK
Sin
Sout
Q0
Q1
QN-1
Q2
Shift a new value in on each clock edge
Shift a value out on each clock edge
Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)
Shift Register with Parallel Load
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g
Clk0
1
0
1
0
1
0
1
D 0 D 1 D N -1D 2
Q0
Q1
QN -1
Q2
Sin
Sout
Load
When Load= 1, acts as a normal N-bit register
When Load= 0, acts as a shift register
Now can act as a serial-to-parallel converter(Sinto Q0:N-
1) or a parallel-to-serial converter(D0:N-1to Sout)
Memory Arrays
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Address
Data
ArrayN
M
Efficiently store large amounts of data Three common types:
Dynamic random access memory (DRAM)
Static random access memory (SRAM) Read only memory (ROM)
AnM-bit data value can be read or written at each uniqueN-
bit address.
T di i l f bit ll
Memory Arrays
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Two-dimensional array of bit cells
Each bit cell stores one bit
An array with Naddress bits and Mdata bits:
2Nrows and Mcolumns
Depth:number of rows (number of words)
Width:number of columns (size of word)
Array size:depth width = 2N M
Address
Data
ArrayN
M
Address Data
11
10
01
00
depth
0 1 0
1 0 0
1 1 0
0 1 1
width
Address
Data
Ar ray2
3
Memory Array: Example
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223-bit array
Number of words: 4
Word size: 3-bits
For example, the 3-bit word stored at address 10 is 100
Example:Address Data
11
10
01
00
depth
0 1 0
1 0 0
1 1 0
0 1 1
width
Address
Data
Array2
3
Memory Arrays
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Memory Arrays
A ddress
Data
1024-w o r d x
32-b i tA r ray
10
32
Memory Array Bit Cells
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Memory Array Bit Cells
Example:
Memory Array Bit Cells
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Memory Array Bit Cells
Example:0
1
Z
Z
Memory Array
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Wordline: similar to an enable
allows a single row in the memory array to be read or written
corresponds to a unique address
only one wordline is HIGH at any given time
wordline311
10
2:4
Decoder
Address
01
00
stored
bit =0wordline
2
wordline1
wordline0
stored
bit =1
stored
bit =0
stored
bit =1
stored
bit =0
stored
bit =0
stored
bit =1
stored
bit =1
stored
bit =0
stored
bit =0
stored
bit =1
stored
bit =1
bitline2
bitline1
bitline0
Data2
Data1
Data0
2
Types of Memory
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Random access memory (RAM): volatile Read only memory (ROM): nonvolatile
RAM: Random Access Memory
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Volatile:loses its data when the power is turned off
Read and written quickly
Main memory in your computer is RAM (DRAM)
ROM: Read Only Memory
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Nonvolatile:retains data when power is turned off
Read quickly, but writing is impossible or slow
Flash memory in cameras, thumb drives, and digital
cameras are all ROMs
Types of RAM
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Two main types of RAM:
Dynamic random access memory (DRAM)
Static random access memory (SRAM)
Differ in how they store data:
DRAM uses a capacitor SRAM uses cross-coupled inverters
Robert Dennard
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Invented DRAM in 1966 at
IBM
By the mid-1970s DRAMwas in virtually all
computers
DRAM
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Data bits stored on a capacitor
Called dynamicbecause the value needs to be refreshed
(rewritten) periodically and after being read:
Charge leakage from the capacitor degrades the value Reading destroys the stored value
wordline
bitline
stored
bit
DRAM
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wordline
bitline
wordline
bitline
+ +stored
bit = 1
stored
bit = 0
SRAM
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wordl ine
bitline bitline
Memory Arrays
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wordline311
10
2:4Decoder
Address
01
00
stored
bit =0wordline
2
wordline1
wordline0
stored
bit =1
stored
bit =0
stored
bit =1
stored
bit =0
stored
bit =0
stored
bit =1
stored
bit =1
stored
bit =0
storedbit =0
storedbit =1
storedbit =1
bitline2
bitline1
bitline0
Data2
Data1
Data0
2
wordline
bitline bitlinewordline
bitline
DRAM bit cell: SRAM bit cell:
ROMs: DOT Notation
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wordline
bitline
wordlinebitline
bit cel l
con taining 0
bit cel l
con taining 1
ROM Storage
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Address Data11
10
01
00
depth
0 1 0
1 0 0
1 1 0
0 1 1
width
ROM Logic
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Data2=A1A0
Data1= A1+A0
Data0= A1A0
Example: Logic with ROMs
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Implement the following logic functions using a 223-
bit ROM:
X=ABY=A+ B
Z=AB
Example: Logic with ROMs
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Implement the following logic functions using a 223-
bit ROM:
X=ABY=A+ B
Z=A B11
10
2:4Decoder
A , B
ZYX
01
00
2
Logic with Any Memory Array
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wordline311
10
2:4
D e c o d e r
A ddress
01
00
stored
bit = 0wordline2
wordline1
wordline0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
bitline2
bitline1
bitline0
Data2
Data1
Data0
2
Data2=A
1A
0
Data1=A1+A0
Data0=A1A0
Logic with Memory ArraysI l t th f ll i l i f ti i
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Implement the following logic functions using a223-bit memory array:
X=AB
Y=A+ B
Z=A Bwordline
311
10
2:4
Decoder
A, B
01
00
stored
bit = 1wordline2
wordline1
wordline0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit =1
stored
bit = 1
stored
bit =0
stored
bit = 1
stored
bit = 0
stored
bit =0
stored
bit = 0
stored
bit = 0
bitline2
bitline1
bitline0
X Y Z
2
Logic with Memory Arrays
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Called lookup tables (LUTs): look up output at each
input combination (address)
stored
bit=1
stored
bit =0
00
01
2:4
Decoder
A
stored
bit =0
bitline
stored
bit =0
Y
B
10
11
4-w ord x 1-bi t Array
A B Y
0 0
0 1
1 0
1 1
0
0
0
1
Truth
Table
A1
A0
Multi-ported Memories
Port address/data pair
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A1
A3
W D 3
W E3
A2
C LK
A r ray
R D 2
R D 1M
M
N
N
N
M
Port:address/data pair
3-ported memory
2 read ports (A1/RD1, A2/RD2)
1 write port (A3/WD3, WE3 enables writing)
Small multi-ported memories are called register files
Logic Arrays
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Programmable logic arrays (PLAs) AND array followed by OR array
Perform combinational logic only Fixed internal connections
Field programmable gate arrays (FPGAs) Array of configurable logic blocks (CLBs)
Perform combinational and sequential logic
Programmable internal connections
PLAs X =ABC + ABC
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X Y
A B C
AND ARRAY
OR ARRAY
ABC
AB
ABC
X =ABC + ABC
Y = AB
AND
ARRAY
OR
ARRAY
Inputs
Outputs
Implicants
N
M
P
PLAs: DOT Notation
Inputs
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AND
ARRAY
OR
ARRAY
Inputs
Outputs
Implicants
N
M
P
X Y
ABC
AB
ABC
A B C
AND ARRAY
OR ARRAY
FPGAs: Field Programmable Gate Arrays
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Composed of:
CLBs (Configurable logic blocks): perform logic
IOBs(Input/output buffers): interface with outsideworld
Programmable interconnection: connect CLBs and
IOBs Some FPGAs include other building blocks such as
multipliers and RAMs
Xilinx Spartan 3 FPGA Schematic
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CLBs: Configurable Logic Blocks
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Composed of:
LUTs (lookup tables): perform combinational logic
Flip-flops: perform sequential functions
Multiplexers: connect LUTs and flip-flops
Xilinx Spartan CLB
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Xilinx Spartan CLB
Spartan CLB has:
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Spartan CLB has: 3 LUTs:
F-LUT (24x 1-bit LUT)
G-LUT (24x 1-bit LUT) H-LUT (23x 1-bit LUT)
2 registered outputs:
XQ
YQ
2 combinational outputs:
X
Y
CLB Configuration Example
Show how to configure the Spartan CLB to perform the
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Show how to configure the Spartan CLB to perform thefollowing functions:
X = ABC + ABC
Y = AB
CLB Configuration Example
Show how to configure the Spartan CLB to perform the
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Show how to configure the Spartan CLB to perform thefollowing functions:
X = ABC + ABC
Y = AB
F4F3
F2F1
F
F2 F1 F0 0
0 11 0
1 1
0
10
0
F30
00
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
1
0
X
XX
X
X
X
X
x
F4
(A) (B) (C) (X)
G2 G1 G0 0
0 11 0
1 1
0
01
0
G3X
XX
X
X
XX
X
G4
(A) (B) (Y)G4G3G2G1
G0
AB
0
A
BC
0
Y
X
FPGA Design Flow
A CAD t l ( h Xili P j t N i t ) i d t
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A CAD tool (such as Xilinx Project Navigator) is used todesign and implement a digital system. It is usually an
iterative process.
The user enters the designusing schematic entry or
an HDL.
The user simulatesthe design.
A synthesistool converts the code into hardware andmaps it onto the FPGA.
The user uses the CAD tool to download the
configurationonto the FPGA This configures the CLBs and the connections between
them and the IOBs.