Lecture06 Latches

8/11/2019 Lecture06 Latches

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Lecture 5 ECE 425

Outline

Efficient XOR circuits

Tri-state buffers

Clocking

Latches


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Lecture 5 ECE 425

XOR

Recall that XOR is a maximally-bad function to implementwith AND/OR gates

Cleverer circuit

Note that does not always provide active drive -- have

to be careful about putting in series


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Lecture 5 ECE 425

Tri-State Inverter

Has high-impedance (disconnected) state

In

Enable

Out


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Lecture 5 ECE 425

Clocking

So far, weve seen combinationalcircuits -- data flowsfrom input to output directly

Most useful circuits are sequential-- they involve

feedbackand memory

Finite State Machines are an important class of sequentialcircuit

We control timing of sequential circuits with a centralized

clock signal


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Sequential Logic

2 storage mechanisms

COMBINATIONAL

LOGIC

Registers

CLK

Q D

Current State

Inputs


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Naming Conventions

In our text: A latch is a level sensitive device

An edge-triggered element is a register

Any bistable component (cross-coupled gates) is a

There are many different naming convention For instance, many books call edge-triggered elem

this leads to confusion however

Memory classification Foreground (embedded into logic: registers)

Background (large arrays)

Memory classification Static / Dynamic


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Timing Definitions

CLK

D

tc 2 q

thold

tsetup

QDATA

STABLE

DATA

STABLE


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Characterizing Timing

Clk

D Q

tC2 Q

Clk

D Q

tC2 Q

tD 2 Q


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Maximum Clock Frequency

FFs

LOGIC

tp,comb

Also:tcdreg+ tc

tcd: contaminimu

Data is hso it can

t + t + t = T


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Latch versus Register

Latch

stores data when

clock is low

D

Clk

Q D

Clk

Q

Register

stores data w

clock rises

Clk Clk

D D


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Latches

In

clk

In

Out

Positive Latch

CLK

D

G

Q

Out

Out Out

In

clk

In

Neg

D

Out

Out Out

In

clk

In

Out

Positive Latch

CLK

D

G

Q

Out

Out Out

In

clk

In

Neg

D

Out

Out Out


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Latch-Based Design

N latch is transparent

when = 0

P latch is tra

when = 1

N

LatchLogic

P

Latc


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Writing into a Static Latch

D

CLK

CLK

Forcing the state

Use the clock as a decoupling signal,that distinguishes between the transparent and opaque

CLK

CLK

CLK

D

Q


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Mux-Based Latches

Negative latch(transparent when CLK= 0)

Positive latch(transparent wh

CLK

1

0D

Q 0

CLK

1D


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Mux-Based Latch

CLK

CLK

CLK

D


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Master-Slave Register

Multiplexer-based latch pair

QMD

CLK

T2

I2

T1I1

I3

T4

I5

T3I4


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Complimentary Single-Phase Clocking

Back-to-back level-sensitive latches create an edge-triggered latch

This implementation requires that true and inverted

clock signals be exactly synchronous


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Complimentary Single-Phase Clocking

In practice, this never happens


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Two-Phase Clocking

Use non-overlapping clocks to tolerate skew


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Recommended Clocking Strategies

Single-phase clocking should be used with purely staticlogic

Mainly used in gate array/standard cell designs

Two-phase clocking is better when you have RAMs,

PLAs, or other structures as well as static gates Well use two-phase clocking in the MPs

In high-speed designs, generating non-overlapping clocks

is difficult, and eats into cycle time

More and more high-performance designs are using

single-phase clocking

Can exploit pipeline structure to make single-phase

clocking work better


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Pipeline Design With Latches

Simple, but requires even division of logic between stages


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Pipeline Design With Level-Sensitive Latches

Can borrow time from one stage to the next Requires that the longest path between two latches of

the same phase be < cycle time


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Clock Distribution

Want to minimize skewbetween clock edges at any twopoints on chip


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Clock Distribution in Modern Chips

Getting harder and harder to generate global clocks withacceptable skew

Wire delays becoming large relative to cycle time

Process, temperature, etc. cause variances inperformance of different clock buffers

Many designs starting to use Globally Asynchronous,Locally Synchronous (GALS) approach

Divide chip into regions

Within a region, use single clock Between regions, add circuits to deal with clock skew

Also used to clock different regions of chip at differentrates


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Static Latch Structures


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Edge-Triggered Latch With Cross-Coupled Inverters


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Dynamic Latches Require Fewer Transistors


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Wrapping Up

Reading -- Section 1.4.7, 7.1-7.4

Next time: Gate and Circuit Delay

Lecture06 Latches

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