Lecture03-part1

7/30/2019 Lecture03-part1

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LECTURE 3


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XNOR XOR


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Implement the logic function

Graphical approach to find the PMOS network

Each NMOS transistor is represented by an arc connecting the source and

drain nodes of the transistors and is labeled with the logical input variable.


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Placing a new nodeinside of everyenclosed path

Two exterior nodes areneeded: one representing theoutput and one representing V

DD


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New arcs cut through the NMOS arcs and connect the pairs ofnodes that are separated by the NMOS arcshas the same logic label as the NMOS arc that is intersected

minimum PMOS logic network only one PMOS transistor

per logic input.


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Final CMOS circuit

2


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Whats the logic function ?


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internal nodecapacitance of thepull-down stack


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the case where both inputs transition go low (A = B = 10) results in a smallerdelay


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PASS TRANSISTOR LOGIC


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NMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drainterminals

NMOS switch closes when the gate input is high

Remember - NMOS transistors pass a strong 0 buta weak 1

A B

X Y X = Y if A and B

X Y

A

B X = Y if A or B


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PMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain

terminals

PMOS switch closes when the gate input is low

Remember - PMOS transistors pass a strong 1 buta weak 0

A B

X Y X = Y if A and B = A + B

X Y

A

B X = Y if A or B = A B


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Pass Transistor (PT) Logic

AB

FB

0

Gate is static a low-impedance path exists to bothsupply rails under all circumstances

N transistors instead of 2N

No static power consumption

Ratioless

Bidirectional (versus undirectional)

A

0

B

BF


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VTC of PT AND Gate

A

0

B

BF= AB

0.5/0.25

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

0 1 2

B=VDD, A=0VDD

A=VDD, B=0VDDA=B=0VDD

Vout,

V

Pure PT logic is not regenerative - the signalgradually degrades after passing through a numberof PTs (can fix with static CMOS inverter insertion)


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Differential PT Logic (CPL)A

B

A

B

PT NetworkF

A

B

AB

Inverse PTNetwork F

F

F

F=AB

A

A

B F=AB

B

B B

AND/NAND

A

A

B F=A+B

BF=A+B

BB

OR/NOR

A

A F=A

B

F=AB

BB

XOR/XNOR

A

A

Why not do the same with all pfets??


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CPL Properties

Differential so complementary data inputs and outputsare always available (so dont need extra inverters)

Still static, since the output defining nodes are alwaystied to VDD or GND through a low resistance path

Design is modular; all gates use the same topology, onlythe inputs are permuted.

Simple XOR makes it attractive for structures like adders

Fast (assuming number of transistors in series is small)

Additional routing overhead for complementary signals

Still have static power dissipation problems


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T i t L l R t Ci it R


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Transient Level Restorer Circuit Response

0

1

2

3

0 100 200 300 400 500

Voltag

e,

V

Time, ps

W/Lr=1.75/0.25

W/Lr=1.50/0.25

W/Lr=1.25/0.25W/Lr=1.0/0.25

W/Ln=0.50/0.25

W/L2=1.50/0.25

W/L1=0.50/0.25

node x never goes below VMof inverter so output neverswitches

Restorer has speed and power impacts: increases thecapacitance at x, slowing down the gate; increases tr (but

decreases tf)

Solution 2: Multiple V Transistors


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Solution 2: Multiple VT Transistors Technology solution: Use (near) zero VT devices for the NMOS

PTs to eliminate mostof the threshold drop (body effect still in

force preventing full swing to VDD)

Impacts static power consumption due to subthresholdcurrents flowing through the PTs (even if VGS is below VT)

Out

In2= 0V

In1

= 2.5V

A= 2.5V

B= 0V

low VT transistors

sneak path

on

off butleaking

S l ti 3 T i i G t (TG )


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Solution 3: Transmission Gates (TGs)

Full swingbidirectionalswitch controlled by

the gate signal C, A = B if C = 1

A B

C

C

A B

C

C

B

C = VDD

C = GND

A = VDD B

C = VDD

C = GND

A = GND

Most widely usedsolution


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Resistance of TG

0

5

10

15

20

25

30

0 1 2

Resistance,

k

Rp

Rn

2.5V

0V

2.5V VoutRp

Rn

Req W/Ln=0.50/0.25

W/Lp=0.50/0.25

G l i l


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TG Multiplexer

GND

VDD

In1 In2S S

S S

S

S

S

In2

In1

F

F

F = !(In1 S + In2 S)

How does this compare to a static

complementary multiplexer?


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Transmission Gate XOR

B

A A B

1

off

off

an inverter

B !A

0

on

on

weak 0 if !A

weak 1 if A

A !B


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TG Full Adder

Sum

Cout

A

B

Cin

Diff ti l TG L i (DPL)


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Differential TG Logic (DPL)

A

A

B

B

B

AND/NAND

F=AB

F=AB

XOR/XNOR

A

A

B

B

A

A

B

F=AB

F=AB

A

A

B

B A B A

GND

GND

VDD

VDD

B

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