CLASSGRADING HOMEWORKSPROJECTSREVIEW OF DIGITAL LOGIC

Digital Design using VHDL and VerilogMarek Perkowski

Department of Electrical and Computer EngineeringPortland State University

IntroductionAdministrationAbout ReviewRASSP ProgramWhy VHDL?Flip-Flops (see ECE 271 class slides)Shift RegistersGeneralized RegisterPipelined Sorter

AdministrationInstructor: Prof. Marek A. Perkowski

Course InformationMy home page http://ee.pdx.edu/~mperkowsComputer Engineering web sitehttp://ece.pdx.edu

AdministrativeOfficeFAB room 160-05Office HoursFridays 6 pm - 10 pm - meetings in FAB, room 150Other Times by AppointmentOffice Phone(503)725-5411 (Answering Machine)

AdministrativeEmailmperkows@ee.pdx.eduStudents with DisabilitiesIf you need special assistance, please inform me soon so that we can work something out.There is a milestone chart available on the class web site.

GradingHW35%Assignments are on the web, may be changed. If changed, I will inform you. Usually these are mini-projects. You may be asked to present them in class.

Final Project65%You will present it in classNo exams

GradingAttendance at LectureNot graded, but recommended.Attendance at Friday meetings not graded, come if you can.

Makeup ExamsMakeup homeworks or exams are not given. Project should be completed before end of the class

HomeworksHomeworks Require Use of VHDLAlways you have to simulate the circuitYou may be asked to synthesize it also.

Mentor Graphics Toolscontact support (cat) peopleuse any lab that is available. Work at home.use addpkgWe use Modelsim for simulation and LeonardoSpectrum for synthesis. Synthesis is mandatory for the project.

Slides

My slides are based on at least 5 books, slides from Internet and my industrial experience, on top of teaching this class since 1989. You can learn all you need if you read slides in detail. Not always I will cover all slides in class. In such case you have to complete reading slides for this week at home.You can learn a lot from previous homeworks and projects that are posted.

Required and Additional TextbooksRequired and recommendedVHDL and FPLDs. Zoran Salcic. CD ROM included. Kluwer Academic Publisherssee my web pageAdditionalThe Designers Guide to VHDLPeter J. AshendenMorgan-KaufmanISBN 1-55860-270-4 (paperback)LOC TK7888.3.A863Dewey Decimal 621.392--dc201996

Resources

IEEE Standard 1076-1993find using search engines on WWW

Use my WWW Page resources, too much to digest.

IEEE Interactive VHDL TutorialOn-line on Computer Engineering Home pagehttp://cpe.gmu.edu password protected

ResourcesOur BookCypress Semiconductor (Warp release 5.x)PC-based$99 with textbookOriented towards Their PLD & FPGA devicesVHDL Subset simulatorXilinx FPGAStudent editionSchematic, FSM, VHDL

Honor CodeYou Are Encouraged to Collaborate With Other Students in Projects.Final VHDL code for each Homework should be done by yourself.In Final Project, each file should have at the top student name of the student responsible for this part of code.

Remind the class.Your webpageList of your names with interests and experiences. Previous design projects that you have done.Any experience in robotics?Any experience in pipelined and systolic processors?Any experience with image processing?Previous VHDL or Verilog projects.C++ experienceOther languages like LISP, Prolog, Basic, etc.I will intentionally repeat the most important parts of material or ideas. I believe in real understanding of material by students and good understanding of fundamentals is most important for me.You have to understand the combinational logic, flip-flops, registers, state diagrams, pipelining, ALU, etc.

Homework 1Simple Satisfiability Machine Simple Petric Function Oracle based machineAny type of SorterFibonacci sequence generatorGCDLCMAny other controller from CU and DP.Any other oracle, SEND+MORE=MONEY, graph coloring, etc.These are just examples, more projects will be added, you can propose your own project.

Projects for year 2008 Transforms Hough TransformsRadon TransformsFast Fourier TransformHadamardHaarAddingArithmeticGaborThese are just examples, more projects will be added, you can propose your own project.

Projects for year 2008 Oracles Graph Coloring (optimized)FPRM learningLogic PuzzlesError Correcting codes designTraveling SalesmanAny other oracles with practical useThese are just examples, more projects will be added, you can propose your own project.

Projects for year 2008 Cellular Automata and RoboticsMandelbrot Set with quaternions and octonionsRobot Vision with morphological algebrasGalois Field Arithmetics for robot visionNeural Net for a robotPID controller for a robotSum of Product minimization for a robotDecision trees in hardware for robotCar model controlLogic DecompositionThese are just examples, more projects will be added, you can propose your own project.

Projects for year 2008 Cellular Automata and RoboticsHidden Markov ModelKalman Filter for robotParticle Filter for robot obstacle avoidanceGenetic Algorithm in hardwareThese are just examples, more projects will be added, you can propose your own project.

Projects for year 2008 Robotics Speech Recognition for a robot (new)Rough Set Machine (continuation - Torrey Lewis)Convolutional Image Processor (continuation)Controller of a Robot (new)Evolvable Hardware (new)These are just examples, more projects will be added, you can propose your own project.

ReviewMealy and MooreRegistered OutputRabin-Scott

Digital System Representation

Basic Logic Functions

Logic Synthesis Using AND, OR and NOT gates

Function Minterms and MaxtermsDiscuss generator of all functions of certain type, use MUX as example

Example: 3-variable function

Example: 3-variable function

NAND, NOR, and De Morgans Theorem

Realizing Sum of Products (SOP) using NAND/NAND

Realizing Product of Sums (POS) using NOR/NOR

Digital System Design: Adder

Iterative Structure of Adder

Full Adder

Full Adder Realization

Implementation Using Multiplexers

Binary Decoder Circuits

A 2-to-4 Decoder with Enable

FA implementation using Decoders

D Flip-Flop

Sequential (Bit-Serial) Adder

Sequential Adder

Behavioral Model of Sequential Adder

To discuss on white-boardSorting data flowPipelined circuit from itButterfly combinational circuit from itSequential controller from itThe concepts:Combinational circuitFinite State machineShifting circuits, starting from Moebius Counter. (Johnson)Cooperating FSMs.Iterative CircuitPipelined circuitSystolic circuitCellular automaton

For students to rememberSOP and POSNand, Nor and De MorganMultiplexerDecoder AdderIterative circuit for adderOther iterative circuitsD flip-flopFlip-flop and register without and with enable.Use of enable in other circuitsSequential versus parallel circuits trade-off.

Some materials from Alnuweiri