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Lecture Outline VLSI Fundamentals - Penn Engineeringese570/spring2019/... · Lecture Outline...
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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 20: April 4, 2019 Dynamic Logic, Charge Sharing and
Leakage, Memory Overview
Penn ESE 570 Spring 2019 – Khanna
Lecture Outline
! Dynamic Logic ! Charge Sharing and Leakage ! Memory Overview
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Dynamic Logic
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Logic Comparison Overview
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DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh.
Logic Comparison Overview
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DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances. Outputs are generated in response to input voltage levels and a clock. Requires periodic updating or refresh.
CSM1
BL
WL
CBL
WL
X
BL
VDD−VT
VDD/2
VDD
GND
Write "1" Read "1"
sensingVDD/2
ΔV VBL VPRE– VBIT VPRE–( )CS
CS CBL+------------------------= =
Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
Comparison of Logic Implementations
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Y
Ratioed
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CMOS
2
Comparison of Logic Implementations
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Y
Ratioed
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CMOS
Comparison of Logic Implementations
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Y
Ratioed
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CMOS
Comparison of Logic Implementations
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Y
Ratioed
1
1
1
VDD more robust
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CMOS
Dynamic CMOS Precharge
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VDD
A
CK
Mp
Me
Z
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Dynamic CMOS Precharge
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Z
Z
of C is complete
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Dynamic (Clocked) Logic: Example
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CK = 0 => Z = ? CK = 1 => Z = ?
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Comparison of Static and Dynamic Logic
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ADVANTAGES ?
DISADVANTAGES ?
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Comparison of Static and Dynamic Logic
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Comparison of Static and Dynamic Logic
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Cascaded Dynamic Logic
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Cascaded Dynamic Logic
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Cascaded Dynamic Logic
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Cascaded Dynamic Logic
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Cascaded Dynamic Logic
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Domino Logic
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Requirements
! Single transition " Once transitioned, it is done # like domino falling
! All inputs at 0 during precharge " ‘Outputs’ pre-charged to 1 then inverted to 0
" I.e. Inputs are pre-charge to 0
! Non-inverting gates
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Cascaded Domino CMOS Logic Gates
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Cascaded Domino CMOS Logic Gates
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propagating
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Cascaded Domino CMOS Logic Gates
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propagating
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Charge Leakage
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CMOS Dynamic D Latch
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Cx is usually a parasitic
capacitance
- Positive level-sensitive
- Inverting
D Q
NMOS PMOS
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Comparison CMOS Static & Dynamic D-Latch
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Data bit stored on Cx when CK = 1 → 0
Dynamic D-Latch
NMOS PMOS
Penn ESE 570 Spring 2019 – Khanna
Comparison CMOS Static & Dynamic D-Latch
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Data bit stored on Cx when CK = 1 → 0
Dynamic D-Latch
ϕ1
ϕ1
Static D-Latch
Data bit stored in bistable-loop when
ϕ1 = 1 → 0
NMOS PMOS
Penn ESE 570 Spring 2019 – Khanna Penn ESE 570 Spring 2019 – Khanna
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
NOTE: No cross-coupled inverters)
Flip-Flop
Latch circuit:
Latch
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Penn ESE 570 Spring 2019 – Khanna
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vy ≤ VT0n,M3 = 1.0 V;
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vy = VT0n = 1V (VGD > VT0p)
Vy ≤ VT0n,M3 = 1.0 V;
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vy = VT0n = 1V (VGD > VT0p)
Vy ≤ VT0n,M3 = 1.0 V;
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vy = VT0n = 1V (VGD > VT0p)
Vy ≤ VT0n,M3 = 1.0 V;
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Penn ESE 570 Spring 2019 – Khanna
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vy = VT0n = 1V (VGD > VT0p)
Vy ≤ VT0n,M3 = 1.0 V;
i.e. Vx can drop from Vx-max = VDD – VTMP to Vx-min = 2.55 V due to charge leakage before VQ is effected (i.e. the output changes state).
EXTRA: Charge Storage and Leakage
! Assume logic-high is stored onto Vx during active phase (CK=1)
! When CK=0, Vin#0
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EXTRA: Charge Storage and Leakage
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Cext
Cext
EXTRA: Charge Storage and Leakage
interconnect
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EXTRA: Junction Capacitance
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Cext
Cext Ileakage =Cx
dVxdt
Vx-max to Vx-min due to leakage.
min(thold ) = Δt =Cx−min
Ileakage−maxΔVx =
Cx−min
Ileakage−max(Vx−max −Vx−min )
Vx−max =VDD −VTn,MP Vx−min = 2.55V
Cx−min =Cext +Cj,min =Cext +Cj (V =Vx−max )Penn ESE 570 Spring 2019 – Khanna
ESTIMATE
EXTRA: Example
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vx-max. Assume
VDD
leakage-max
Vx−max =VDD −VTn,MP Vx−min = 2.55VPenn ESE 570 Spring 2019 – Khanna
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EXTRA: Example
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Cn+p+ = CJSW Pn+p+ = 0.200 fF/µm (18 µm + 6 µm + 2 µm) = 5.20 fF Cn+p = CJ An+p = 0.095 fF/µm2 (36 µm2 + 12 µm2) = 4.56 fF
Penn ESE 570 Spring 2019 – Khanna
EXTRA: Example
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min(thold ) = Δt =Cx−min
Ileakage−maxΔVx =
Cx−min
Ileakage−max(Vx−max −Vx−min )
Cx−min =Cext +Cj,min =Cext +Cj (V =Vx−max )
Vx−max =VDD −VTn,MP ≈ 4V Vx−min = 2.55V
Cj (V ) =A ⋅Cj0
1+Vφ0
+P ⋅Cj0sw
1+Vφ0sw
Cj (Vx−max = 4V ) =4.56 fF
1+4V0.88
+5.20 fF
1+4V0.95
= 4.21 fF
VDD = 5.0 V VT0 = 1.0 V PB = 0.88 V PBsw = 0.95 V Ileakage,max = 0.85 pA
Penn ESE 570 Spring 2019 – Khanna
EXTRA: Example
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min(thold ) = Δt =Cx−min
Ileakage−maxΔVx =
Cx−min
Ileakage−max(Vx−max −Vx−min )
Cx−min =Cext +Cj,min =Cext +Cj (V =Vx−max )Cx−min = 0.52 fF + 0.90 fF + 2.42 fF + 4.21 fF = 8.05 fF
VDD = 5.0 V VT0 = 1.0 V PB = 0.88 V PBsw = 0.95 V Ileakage,max = 0.85 pA
min(thold ) =8.05 fF0.85pA
(4V − 2.55V ) =13.73ms
Penn ESE 570 Spring 2019 – Khanna
EXTRA: Example Overview: Min Hold Time
! Find min voltage value for storage node to maintain data " Vx = voltage across storage capacitor
! With dimensions of switch MOS and load MOS " Calculate Cext = Cgb+ Cint = Cgb + Cpoly + Cmetal
" Calculate Cj = junction capacitance
! With max leakage value " Calculate min hold time (i.e. min time for storage
capacitor to leak to min Vx)
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min(thold ) = Δt =Cx−min
Ileakage−maxΔVx =
Cx−min
Ileakage−max(Vx−max −Vx−min )
Charge Sharing
Penn ESE 570 Spring 2019 – Khanna
Shift Register
! Shift registers store and delay data ! Simple design: cascade of latches
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DD-
Latch D-
Latch D-
Latch
Out
ϕ1 ϕ1 ϕ2
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Shift Register with Dynamic D Latches
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
When Vout(i) = 0V (or 5V) and Vin(i+1) = 5V (or 0V) for i = 1,2 (stage)
“Charge Sharing” is an issue when ϕ1/ϕ2 close. Penn ESE 570 Spring 2019 – Khanna
Shift Register with Dynamic D Latches
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
When Vout(i) = 0V (or 5V) and Vin(i+1) = 5V (or 0V) for i = 1,2 (stage)
“Charge Sharing” is an issue when ϕ1 or ϕ2 close pass gate switches.
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Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb >> Va
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Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb >> Va
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Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb >> Va
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Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb >> Va
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Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
“Rule of Thumb” make Cout1 = 10 Cin2
Vb >> Va
Penn ESE 570 Spring 2019 – Khanna
Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb << Va
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Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb << Va
If Vb = 0 and Va >> Vb # VR ≈Cin2VDDCout1 +Cin2
Penn ESE 570 Spring 2019 – Khanna
Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Vb << Va
If Vb = 0 and Va >> Vb # VR ≈Cin2VDDCout1 +Cin2
If Cout1 >> Cin2 # VR ≈Cin2VDDCout1
<<VDDPenn ESE 570 Spring 2019 – Khanna
Charge Sharing
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
“Rule of Thumb” make Cout1 = 10 Cin2
Vb << Va
If Vb = 0 and Va >> Vb # VR ≈Cin2VDDCout1 +Cin2
If Cout1 >> Cin2 # VR ≈Cin2VDDCout1
<<VDDPenn ESE 570 Spring 2019 – Khanna
Domino Logic Design Considerations
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Requirements
! Single transition " Once transitioned, it is done # like domino falling
! All inputs at 0 during precharge " ‘Outputs’ pre-charged to 1 then inverted to 0
" I.e. Inputs are pre-charge to 0
! Non-inverting gates
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Cascaded Domino CMOS Logic Gates
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
propagating
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Pre-charge Leakage
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
“weak keeper”
(W/L)p-keeper < (W/L)n-min
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Charge Sharing within PDN
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
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Charge Sharing within PDN
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
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Charge Sharing within PDN
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Charge Sharing within PDN
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1
2
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Kenneth R. Laker, University of Pennsylvania,
updated 25Mar15
Charge Sharing within PDN
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Since all nodes are pre-charged there is no charge-
sharing.
C4
C3
C2
C1
Z4
Z3
Z2
Z1
P0
Z1 = G1 + P1 * P0 Z2 = G2 + P2 * G1 + P2 * P1 * P0 = G2 + P2 * Z1 Z3 = G3 + P3 * G2 + P3 * P2 * G1 + P3 * P2 * P1 * P0 = G3 + P3 * Z2 Z4 = G4 + P4 * G3 + P4 * P3 * G2 + P4 * P3 * P2 * G1 + P4 * P3 *P1 * P0 = G4 + P4 * Z3
Charge Sharing within PDN
Penn ESE 570 Spring 2019 – Khanna
CMOS Logic
! Best option in the majority of CMOS circuits ! Advantages:
" Noise-immunity not sensitive to kn/kp
" does not involve pre-charging of nodes " dissipates no DC power " layout can be automated
! Disadvantages: " Large fan-in gates lead to complex circuit structures (2N
transistors) " larger parasitics " slower and higher dynamic power dissipation than alternatives " no clock and no synchronization.
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Pseudo-nMOS/Ratioed Logic
! Finds widest utility in large fan-in gates ! Advantages:
" Requires only N+1 transistors for N fan-in " smaller parasitics " faster and lower dynamic power dissipation than full
CMOS
! Disadvantages: " Noise-immunity sensitive to kn/kp
" dissipates DC power when pulled down " not well-suited for automated layout " no clock and no synchronization.
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CMOS domino-logic
! Used for low-power, high-speed applications. ! Advantages:
" Requires N+k transistors for N fan-in (size advantages of pseudo-nMOS)
" dissipates no DC power " noise immunity not sensitive to kn/kp " use of clocks enables synchronous operation
! Disadvantages: " Relies on storage on soft nodes " will require thorough simulation at all the process corners to insure
proper operation " some of the speed advantage over static gates is diminished by the
required pre-charge (pre-discharge) time
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Memory Overview
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CPU Memory Hierarchy
Kenneth R. Laker, University of Pennsylvania,
updated 02Apr15
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Locality and Cacheing
! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again
! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can’t build large, fast memories
! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) -- 5-20 ns access time, very expensive (on-CPU
faster) " DRAM (dynamic RAM) -- 60-100 ns, cheaper " Disk -- access time measured in milliseconds, very cheap
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Semiconductor Memory Classification
RWM NVRWM ROM
EPROM
E2PROM
FLASH
RandomAccess
Non-RandomAccess
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
Penn ESE 570 Spring 2019 - Khanna
Memory Architecture: Core
Word 0Word 1
Word 2
Word N-1
Word N-2
Input-Output
S0S1S2
SN-2SN_1
(M bits)
StorageCell
M bits
N W
ords
Word 0Word 1
Word 2
Word N-1
Word N-2
Input-Output(M bits)
StorageCell
M bits
Dec
oder
A0
A1
AK-1
S0
N words => N select signalsToo many select signals
Decoder reduces # of select signalsK = log2N
Penn ESE 570 Spring 2019 - Khanna
Memory Architecture: Decoders
Penn ESE 570 Spring 2019 - Khanna
Word 0Word 1
Word 2
Word N-1
Word N-2
Input-Output
S0S1S2
SN-2SN_1
(M bits)
StorageCell
M bits
N W
ords
Word 0Word 1
Word 2
Word N-1
Word N-2
Input-Output(M bits)
StorageCell
M bits
Dec
oder
A0
A1
AK-1
S0
N words => N select signalsToo many select signals
Decoder reduces # of select signalsK = log2N
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Array-Structured Memory Architecture
Input-Output(M bits)
Row
Dec
oder
AK
AK+1
AL-1
2L-K
Column Decoder
Bit Line
Word Line
A0
AK-1
Storage Cell
Sense Amplifiers / Drivers
M.2K
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing torail-to-rail amplitude
Selects appropriateword
Penn ESE 570 Spring 2019 - Khanna
ROM Memories
Penn ESE 570 Spring 2019 - Khanna 80
MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VDD
Pull-up devices
Penn ESE 570 Spring 2019 - Khanna
MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VDD
Pull-up devices
Penn ESE 570 Spring 2019 - Khanna
MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VDD
Pull-up devices
Penn ESE 570 Spring 2019 - Khanna
MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VDD
Pull-up devices
0 1 1 1
Penn ESE 570 Spring 2019 - Khanna
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MOS NOR ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
GND
GND
VDD
Pull-up devices
0 1 1 1
1 1 0 0
0 1 0 1
1 1 1 1
Penn ESE 570 Spring 2019 - Khanna
MOS NAND ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
VDD
Pull-up devices
All word lines high by default with exception of selected row
Penn ESE 570 Spring 2019 - Khanna
MOS NAND ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
VDD
Pull-up devices
All word lines high by default with exception of selected row
Penn ESE 570 Spring 2019 - Khanna
MOS NAND ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
VDD
Pull-up devices
All word lines high by default with exception of selected row
1 0 0 0
Penn ESE 570 Spring 2019 - Khanna
MOS NAND ROM
WL[0]
WL[1]
WL[2]
WL[3]
BL[0] BL[1] BL[2] BL[3]
VDD
Pull-up devices
All word lines high by default with exception of selected row
0 0 1 1
1 0 1 0
0 0 0 0
1 0 0 0
Penn ESE 570 Spring 2019 - Khanna
Ideas
! Dynamic/clocked logic " Only build/drive one pulldown network " Fast transition propagation " Domino Logic allows for cascading
! Domino Logic allows for cascading ! Charge Leakage
" Constrains min/max clock frequency
! Charge Sharing with pass gates " Need to size carefully
! Memory Architecture " Share circuitry and minimize area per bit
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Admin
! HW 7 due tomorrow 4/5 " Extended to Sunday 4/7
! HW 8 released Friday " 1 week to turn-in " Will count as Extra Credit
! Final Project released Tuesday next week " Work in pairs – start pairing off " Design and layout memory " Due 4/30 (last day of class)
" Everyone gets an extension until 5/7
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