1

Technology Scaling Trends and Interconnect Issues

Lecture-15

Fall SemesterMasud H. Chowdhury

Electrical and Computer EngineeringUniversity of Illinois at Chicago

2

Technology Scaling• Systems at a glance:

• Interconnect Dimensions:

Present Features Future Around 2012*

0.13 micron 10M/sq.cm

3.06 GHz1.01-2.5V70 Watts1.2 Watts

0.035 micron180M/sq.cm10 GHz0.5-0.6V175 Watts3.2 Watts

FEATURE SIZE

DENSITY

ON-CHIP CLOCK

SUPPLY VOLTAGE

POWER (HIGH PERF.)

POWER (MOBILE)

hd

w

h

h/w

wd

0.2-0.4um

2.5-3.0

0.1-0.15um0.1-0.15um

0.7-.9um

1.7-1.9

0.3-0.4um0.3-0.4um

hd

w

h

Present/FuturePastReference

d dw

hw

h, w, and d going down

but h/w going up

M M M M

Technology scaling data for metal layer 2

Technology size h w d h/w

0.5 um 0.98 um 0.75 um 0.95 um 1.31

0.25 um 0.89 um 0.48 um 0.45 um 1.85

3

Interconnect Wire Inside IC• Each wire in an interconnect network connects a transmitter (or transmitters) to a set of

receivers and is implemented as a chain of wire segments of various lengths and geometries

• At the early stages the impact of these on-chip interconnect wires were negligible• Wiring in current IC technologies form a complex geometry that introduces capacitive,

resistive and inductive parasitics, which have become dominant over device parasitics in deep submicron technologies.

• These interconnect parasitics have multiple impacts on circuit behavior– Increased propagation delay– Impact on power consumption– Introduction of noise

transmitters receivers

schematics physical

4

Interconnect Wire Inside IC• In current process multiple layers of aluminum or copper, and at least one layer of

polysilicon wires are available to provided connectivity in very high densities ICs

Layout cross section

5

Interconnect Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process

3D micro-photographic view

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric

Interconnect Parasitics: Capacitance• Parallel Plate Model:

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

diint

LLCwire SSS

SS

1

PermittivityPermittivity

Here W and L are width and length of the wire; di and tdi is the permittivity and thickness of dielectric

7

Interconnect Parasitics: Capacitance• Fringing Capacitance:

– Continuous push for denser circuits leads to steady reduction of W/H ratio, which makes parallel plate assumption inaccurate

– The capacitance between sidewalls of the wires and the substrate, known as fringing capacitance, can not be ignored, which is illustrated in the figure below

W - H/2H

+

(a)

(b)

• An exact model to incorporate both parallel plate and fringing capacitance is very complex

• Among various models a simplified and common used model for interconnect capacitance to substrate is as shown below

• Here the model is comprised of a parallel plate capacitance determined orthogonal field between wire of width w=W-H/2, and a fringing capacitance modeled by a cylindrical wire with dimension equal to interconnect thickness Hground or substrate

8

Interconnect Parasitics: Capacitance• Fringing Capacitance Versus Parallel Plate Capacitance:

9

Interconnect Parasitics: Capacitance• Capacitance in Multi-Layer Representation:

– As digital technology entered into the era of multi-layer interconnect lines some other capacitive components become significant

– In advanced CMOS technologies the total capacitance is estimated as the sum of four components:

• Line-to-ground/substrate capacitance • Coupling or lateral capacitance - between

two nets on the same layers• Parallel or crossover capacitance - due to

overlap area of two nets on different layers• Fringing capacitance - formed between

the edge of one conductor and the surface of another conductor on different layers

– However, the coupling or lateral capacitance has become the dominant component among these capacitances

GND

M3

M2

M1

CG

CC

CfCp

Capacitance in multi-layer representation

fpcGtotal CCCCC 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

1 1.2 1.4 1.6 1.8 2

spacing/min spacingco

uplin

g/to

tal c

apac

itanc

e

0.18 um

0.25 um

0.5 um

Coupling capacitance compared to total capacitance with technology

scaling

10

Interconnect Parasitics: Capacitance• Components of Wire Capacitance in Multi-Layer Representation:

fringing parallel

11

Interconnect Parasitics: Resistance• Interconnect resistance can be obtained by the following simplified model

W

L

H

R = H W

L

= Sheet ResistanceR=H

resistivity of the material

12

Interconnect Parasitics: ResistanceDealing With Resistance:

• Interconnect resistance is increasing with continuous scaling (decreasing cross-section and increasing length L with chip size), and has become very critical

• Various steps have been adopted to deal with wire resistance– Use Better Interconnect Materials: Due to lower sheet resistance aluminum has been extensively

used, but now it is being being replaced by copper due to its lower resistivity

– Selective Technology Scaling: H is being reduced much slower than W so that wire cross-section does not decrease rapidly

– More Interconnect Layers: reduce average wire-length

– Advanced processes also offer silicide polysilicon and diffusion layers as alternatives to regular polysilicon

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

13

Interconnect Parasitics: InductanceDefinition of Inductance:• A changing current passing through a conductor generates a voltage drop proportional to

the rate of change of the currentV = L(di/dt)

• The constant of proportionality L is called the inductance of the conductor• The parasitic element defined above is also called self inductance of the conducting wire• Another inductive parasitic element is mutual inductance, whose definition is as follows:

– A changing current in an inductive wire induces a voltage change on a neighboring inductive wire. The induced voltage is proportional to the rate of change of current, and the constant of proportionally M is called the mutual inductance between the conductors

M = k/(L1L2)– Here k is mutual inductive coefficient, L1 and L2 are the self inductances of the two

conductors

CC M

Rdrv LCG

R

14

Interconnect Modeling• Ideal Wire:– No impact on electrical behavior of the circuit– Occur as simple lines with no attached parasitic– No voltage drop along the wire – the whole wire is equipotent– Signal propagates immediately from end to end – no delay in wires– No wire is ideal

• Practicality of Ideal Wire: – The effect of short wires inside small circuits such as gates can be ignored– In the early phase of design when the devices properties are analyzed wires can be

considered as ideal to make the analysis simple– Two decades back, when the minimum feature size was about 5μm, the gate parasitic

impedance dominated integrated circuit performance and interconnect lines were modeled as a short or ideal wire

Short Circuit

15

Interconnect Modeling• Introduction of Wire Capacitance:

– With the continuous scaling of device and wire sizes, the interconnect capacitance to reference plane became comparable to the device capacitances, requiring the introduction of capacitance in line modeling

– Since at low and medium frequency ranges resistive components is small, only capacitive component of the wire was considered at the early stages

VDD VDD

Vin Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplified

Model

16

Interconnect Modeling• Lumped Capacitive Model:

– Interconnect parasitics are distributed along the length

– When only one parasitic is dominant, and the interaction between the components is small, and when looking at only on aspect of the circuit behavior it is useful to model the wire parasitic as a lumped element

– Lumped model can be analyzed manually using simple differential equation

– In this lumped model the line is still represents an equipotent region – no voltage drop due to the wire itself

– The lumped capacitor affects the performance of the driving gate

– Lumped capacitive model is very simple and widely used for many short and wide lines where resistive component is insignificant

17

Interconnect Modeling• Lumped RC Model:

– With further scaling down of technology, the cross sectional area of the lines has been scaled down to provide more lines per unit area, while the length of the lines has increased with chip size and complexity. As a result the resistance of long signal lines increased significantly

– Equipotent – zero voltage drop assumption is no longer valid, and a resistive-capacitive model is required

– In this model the total wire resistance is put into a single resistor, and similarly the total capacitance is combined into one capacitor

– Lumped RC model is very useful and first-order model used intensively in analyzing the transient behavior of the transistor-wire network

• RC Tree or Chain Model:– Lumped RC model is pessimistic for a resistive-capacitive line– Resistance at the beginning of the line sees more capacitance than the resistance downward along

the line– Scaling trends pushed interconnect modeling to the next step of modeling interconnect lines as RC

Tree or RC Chain. – In this modeling a long line is broken into multiple segments, where the resistance and capacitance

of each segment are lumped into one resistance and one capacitance– For analyzing this type of RC Tree or RC Chain, Elmore Delay model is used

Driver

Rwire

Cwire

18

Interconnect Modeling• Distributed RC Model:

– RC Tree or RC Chain gives better accuracy as compared to the lumped RC model

– For very high performance circuit, where margin of tolerance is very narrow a distributed RC model would be much desirable

– Since the resistance and capacitance of the line are distributed along the length of the line, a truly distributed model, where the parasitic elements are distributed at every infinitesimal segment, will give accurate performance

– But analysis of pure distributed line with associated parasitics for every infinitesimal segment is very complex and time consuming

– Practical analysis of high performance interconnect circuits uses RC Tree or RC Chain model between lumped and truly distributed model.

– Number of segments in the RC Tree or Chain determines accuracy of analysis

– Higher number of segments gives better accuracy, but makes the analysis more complex

19

Interconnect Delay Analysis with Different RC Line Model• Delay Analysis of Lumped RC Line:

– Propagation delay is defined as the time difference between 50% transition points of input and output signals

– From earlier analysis we found that delay of a CMOS inverter can be derived from its RC model

– For lumped RC line we can derive exactly similar delay expression• Delay Analysis Line Modeled as RC Chain

– Elmore RC time constant at node N

– The Propagation delay:

– The Elmore RC time constant is derived by determining the path between node i and the source/input node. Each term in the summation expression is product of the capacitance of node i and the total resistance of that path.

LpppLH CRt .69.069.0 VoutVout

Rn

Rp

VDD

CLCL

VDDLnnpHL CRt .69.069.0

Driver RwireCwire

Inver RC Model and Delay Lumped RC Line Model and Delay

wirewirewireDwire CRt .69.069.0

NDwiret 69.0

Ni

20

Interconnect Delay Analysis with Different RC Line Model• Delay Analysis of Distributed RC Line:

– In distributed model the line is divided into N number of equal-length segments, each segment having a length ΔL.

– Here per unit length resistance and capacitance of the line are r and c respectively– The Elmore RC time constant:

– Here R is the total resistance of the line– C is the total capacitance of the line– For distributed line N is very large:

• Observations:– We observe that the delay of RC line shows quadratic dependence on line length– The propagation delay for truly distributed line is half of the delay obtained from

lumped RC model– Therefore, lumped model is pessimistic, since it overestimates interconnect delay. – RC chain or tree model is more optimistic model with better delay approximation. This

model approximates Elmore RC constant somewhere between RC and RC/2– For accurate delay analysis, distributed model is the most appropriate

2345.0345.0)2

(69.069.0 rcLRCRC

t DNDwire

21

Interconnect Modeling• Distributed RC Model with Coupling Capacitance:

– In current extremely dense integrated circuits, the line-to-reference capacitance alone has become insufficient for signal behavior analysis

– The lateral or coupling capacitance, formed by two parallel edges of non-overlapping conductors in the same plane, is increasing as the spacing between conducting lines in the same plane decreases, which came down close to or less than 1μm

– To improve the degrading resistance of long wires, the vertical dimensions of the lines scaled slowly as compared to the horizontal dimension, leading to a very high aspect ratio. Consequently, the coupling or lateral capacitance is becoming even stronger due to longer overlap area among lines in the same layer.

– This is particularly true in the upper metal layers, where power and clock distribution networks, and global signal lines run across the whole chip area. They require longer, thicker and wider wires to ensure power and signal distribution, lower IR drop, reduced clock skew, robustness under process variations, and signal reliability.

– Bus-dominant designs worsen the effects of coupling, since it results in longer parallel runs.

22

Interconnect Modeling• Introduction of Self and Mutual Inductances

– Due to faster on-chip rise time and the drive for low resistive lines, currently on-chip inductance have become important

– Longer and wider wires in clock distribution networks and upper metal layers exhibit significant inductive effects

– Accuracy requirements at very higher operating frequencies, make it crucial to include self and mutual inductances

– Figure below illustrates all the factors that influence the interaction of two adjacent interconnects lines

– Therefore, in current deep submicron

technology for very high performance

integrated circuits analysis lines are

modeled as distributed RLC lines with

coupling capacitance and mutual

inductances

All that influence performance

CC M

Rdrv LCG

R

23

Transition of Interconnect ModelingShort Circuit

Lumped C

Distributed RC

Distributed RLC

Lumped RC

All that influence performance

CC M

Rdrv LCG

R

24

Summary

Interconnect parameters dominating Decreasing feature sizes

Dominance of coupling capacitance

Inclusion of inductances

Signal integrity issue becomes critical Increasing CCT/CTOTAL ratio

Decreasing noise margin

• Power Consumption going up