Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture.

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Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture

Transcript of Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture.

Page 1: Lecture 8 Shelving in Superscalar Processors (Part 1) Advanced Computer Architecture.

Lecture 8Shelving in Superscalar

Processors (Part 1)

Advanced Computer Architecture

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Direct Issue

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The principle of shelving: Indirect Issue

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Design Space of Shelving

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Scope of Shelving

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Layout of Shelving Buffers

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Implementation of Shelving Buffer

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Basic Variants of Shelving Buffers

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Using a Combined Buffer for

Shelving, Renaming, and Reordering

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Number of Shelving Buffer Entries

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Number of read and write ports

how many instructions may be written into (input ports) or

read out from (output parts) a particular shelving buffer in a cycle

depend on individual, group, or central reservation stations

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Shelving: Operand Fetch Policy

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Operand Fetch Policies

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Operand fetch during instruction issue

Reg. file

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Operand fetch during instruction dispatch

Reg. file