Lecture 8 Low Power Design - Circuits and Systemscas.ee.ic.ac.uk/people/kostas/web page...
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Lecture 8 - 1Introduction to Digital Integrated Circuit DesignLow Power Design
Lecture 8
Low Power Design
Konstantinos MasselosDepartment of Electrical & Electronic Engineering
Imperial College London
URL: http://cas.ee.ic.ac.uk/~kostasE-mail: [email protected]
Lecture 8 - 2Introduction to Digital Integrated Circuit DesignLow Power Design
Based on slides/material by…
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html“Digital Integrated Circuits: A Design Perspective”, Prentice Hall
D. Harris http://www.cmosvlsi.com/coursematerials.htmlWeste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison Wesley
Lecture 8 - 3Introduction to Digital Integrated Circuit DesignLow Power Design
Recommended Reading
J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”: Chapter 5 (5.5), Chapter 11 (11.7)
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”: Chapter 4 (4.4), Chapter 6 (6.5)
Lecture 8 - 4Introduction to Digital Integrated Circuit DesignLow Power Design
Why worry about power?-- Heat Dissipation
DEC 21164
source : arpa-esto
microprocessor power dissipation
Lecture 8 - 5Introduction to Digital Integrated Circuit DesignLow Power Design
Evolution in Power Dissipation
Lecture 8 - 6Introduction to Digital Integrated Circuit DesignLow Power Design
Why worry about power — Portability
Multimedia Terminals
Laptop Computers
Digital Cellular Telephony
BATTERY(40+ lbs)
Year
Nom
inal
Cap
acity
(Wat
t-hou
rs /
lb)
Nickel-Cadium
Ni-Metal Hydride
65 70 75 80 85 90 95 0
10
20
30
40
50 Rechargable Lithium
Expected Battery Lifetime increaseover next 5 years: 30-40%
Lecture 8 - 7Introduction to Digital Integrated Circuit DesignLow Power Design
Power and Energy
Power is drawn from a voltage source attached to the VDD pin(s) of a chip.
Instantaneous Power:
Energy:
Average Power:
( ) ( )DD DDP t i t V=
0 0
( ) ( )T T
DD DDE P t dt i t V dt= =∫ ∫
avg0
1 ( )T
DD DDEP i t V dtT T
= = ∫
Lecture 8 - 8Introduction to Digital Integrated Circuit DesignLow Power Design
Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
Lecture 8 - 9Introduction to Digital Integrated Circuit DesignLow Power Design
Dynamic Power Consumption
Dynamic power is required to charge and discharge load capacitances when transistors switch.One cycle involves a rising and falling output.On rising output, charge Q = CVDD is requiredOn falling output, charge is dumped to GNDThis repeats Tfsw times over an interval of T
Cfsw
iDD(t)
VDD
Lecture 8 - 10Introduction to Digital Integrated Circuit DesignLow Power Design
Dynamic Power Consumption
Cfsw
iDD(t)
VDD[ ]
dynamic0
0
sw
2sw
1 ( )
( )
T
DD DD
TDD
DD
DDDD
DD
P i t V dtT
V i t dtT
V Tf CVT
CV f
=
=
=
=
∫
∫
Lecture 8 - 11Introduction to Digital Integrated Circuit DesignLow Power Design
Activity Factor
Suppose the system clock frequency = fLet fsw = αf, where α = activity factor• If the signal is a clock, α = 1• If the signal switches once per cycle, α = ½• Dynamic gates:
Switch either 0 or 2 times per cycle, α = ½• Static gates:
Depends on design, but typically α = 0.1
Dynamic power: 2dynamic DDP CV fα=
Lecture 8 - 12Introduction to Digital Integrated Circuit DesignLow Power Design
Dynamic Power Consumption
V in V out
C L
E nergy/transition = CL * V d d2
Pow er = E nergy/transition * f = C L * V dd2 * f
N eed to reduce C L , V dd , and f to redu ce pow er.
Vdd
N ot a fu nction of transistor sizes!
Lecture 8 - 13Introduction to Digital Integrated Circuit DesignLow Power Design
Dynamic Power Consumption - Revisited
Power = Energy/transition * transition rate
= CL * Vdd2 * f0→1
= CL * Vdd2 * P0→1* f
= CEFF * Vdd2 * f
Power Dissipation is Data DependentFunction of Switching Activity
CEFF = Effective Capacitance = CL * P0→1
Lecture 8 - 14Introduction to Digital Integrated Circuit DesignLow Power Design
Short Circuit Current
When transistors switch, both nMOS and pMOS networks may be momentarily ON at onceLeads to a blip of “short circuit” current.< 10% of dynamic power if rise/fall times are comparable for input and output
Lecture 8 - 15Introduction to Digital Integrated Circuit DesignLow Power Design
Short Circuit Currents
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
Lecture 8 - 16Introduction to Digital Integrated Circuit DesignLow Power Design
Impact of rise/fall times on short-circuit currents
VDD
Vout
CL
Vin
ISC ≈ 0
VDD
Vout
CL
Vin
ISC ≈ IMAX
Large capacitive load Small capacitive load
Lecture 8 - 17Introduction to Digital Integrated Circuit DesignLow Power Design
Short-circuit energy as a function of slope ratio
0r
876543210
1 2 3 4 5
ΔE / E
VDD = 5 V
VDD = 3.3 V
W/L|P = 7.2μm/1.2μm W/L|N = 2.4μm/1.2μm
The power dissipation due to short circuit currents is
rise/fall times of the input and output signals. minimized by matching the
Lecture 8 - 18Introduction to Digital Integrated Circuit DesignLow Power Design
Power Consumption is Data Dependent
Example: Static 2 Input NOR Gate
Assume:P(A=1) = 1/2P(B=1) = 1/2
P(Out=1) = 1/4P(0→1)
= 3/4 × 1/4 = 3/16
Then:
= P(Out=0).P(Out=1)
CEFF = 3/16 * CL
Lecture 8 - 19Introduction to Digital Integrated Circuit DesignLow Power Design
Transition Probabilities for Basic Gates
Lecture 8 - 20Introduction to Digital Integrated Circuit DesignLow Power Design
Transition Probability of 2-input NOR Gate
Lecture 8 - 21Introduction to Digital Integrated Circuit DesignLow Power Design
Problem: Reconvergent Fanout
A
B
X
Z
Reconvergence
P(Z=1) = P(B=1) . P(X=1 | B=1)
Becomes complex and intractable real fast
Lecture 8 - 22Introduction to Digital Integrated Circuit DesignLow Power Design
How about Dynamic Circuits?
Mp
Me
VDD
PDN
φ
In1In2In3
Out
φ
Power is Only Dissipated when Out=0!
CEFF = P(Out=0).CL
Lecture 8 - 23Introduction to Digital Integrated Circuit DesignLow Power Design
4-input NAND Gate
Example: Dynamic 2 Input NOR Gate
Assume:P(A=1) = 1/2P(B=1) = 1/2
P(Out=0) = 3/4
Then:
CEFF = 3/4 * CL
Switching Activity Is Always Higher in Dynamic Circuits
Lecture 8 - 24Introduction to Digital Integrated Circuit DesignLow Power Design
Transition Probabilities for Dynamic Gates
Switching Activity for Precharged Dynamic Gates
P0→1 = P0
Lecture 8 - 25Introduction to Digital Integrated Circuit DesignLow Power Design
Glitching in Static CMOS
A
B
X
CZ
ABC 101 000
X
Z
Unit Delay
also called: dynamic hazards
Observe: No glitching in dynamic circuits
Lecture 8 - 26Introduction to Digital Integrated Circuit DesignLow Power Design
Example: Adder Circuit
0 5 100.0
2.0
4.0
Time, ns
Sum
Out
put V
olta
ge, V
olts
Cin
S15
S10
6
5
4
3
2S1
Add0 Add1 Add2 Add14 Add15
S0 S1 S2 S14 S15
Cin
Lecture 8 - 27Introduction to Digital Integrated Circuit DesignLow Power Design
How to Cope with Glitching?
F1
F2
F3
F1
F3
F2
0
0
0
0
1
2
0
0
0
0 1
1
Equalize Lengths of Timing Paths Through Design
Lecture 8 - 28Introduction to Digital Integrated Circuit DesignLow Power Design
Static Power
Static power is consumed even when chip is quiescent.• Ratioed circuits burn power in fight between ON transistors• Leakage draws power from nominally OFF devices
Lecture 8 - 29Introduction to Digital Integrated Circuit DesignLow Power Design
Static Power Consumption
Vin=5V
Vout
CL
Vdd
Istat
Pstat = P(In=1).Vdd . Istat
• Dominates over dynamic consumption
• Not a function of switching frequency
Lecture 8 - 30Introduction to Digital Integrated Circuit DesignLow Power Design
Leakage
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
Sub-Threshold Current Dominant Factor
Lecture 8 - 31Introduction to Digital Integrated Circuit DesignLow Power Design
Sub-Threshold in MOS
VT=0.6VT=0.2
√ID
VGS
Lower Bound on Threshold to Prevent Leakage
Lecture 8 - 32Introduction to Digital Integrated Circuit DesignLow Power Design
Reducing Vdd
P x td = Et = CL * Vdd2
E(Vdd=2)=
(CL) * (2)2
(CL) * (5)2E(Vdd=5)
Strong function of voltage (V2 dependence).Relatively independent of logic function and style.
E(Vdd=2) ≈ 0.16 E(Vdd =5)
0.03
0.05
0.07
0.1
0.15
0.20
0.30
0.50
0.70
1.00
1.5
1 2 5
51 stage ring oscillator
8-bit adder
Vdd (volts)
quadratic dependence
NO
RM
ALI
ZED
PO
WE
R-D
ELA
Y P
RO
DU
CT
Power Delay Product Improves with lowering VDD.
Lecture 8 - 33Introduction to Digital Integrated Circuit DesignLow Power Design
Lower Vdd Increases Delay
CL * VddI
=Td
Td(Vdd=5)
Td(Vdd=2)=
(2) * (5 - 0.7)2
(5) * (2 - 0.7)2
≈ 4
I ~ (Vdd - Vt)2
Relatively independent of logic function and style.
1.001.502.002.503.003.504.004.505.005.506.006.507.007.50
2.00 4.00 6.00Vdd (volts)
NO
RM
AL
IZED
DE
LA
Y
adder (SPICE)
microcoded DSP chip
multiplier
adder
ring oscillator
clock generator2.0μm technology
Lecture 8 - 34Introduction to Digital Integrated Circuit DesignLow Power Design
Lowering the Threshold
DESIGN FOR PLeakage == PDynamic
Vt = 0.2Vt = 0
ID
VGS
Reduces the Speed Loss, But Increases Leakage
Vdd
Delay
2Vt
Interesting Design Approach:
Lecture 8 - 35Introduction to Digital Integrated Circuit DesignLow Power Design
Transistor Sizing for Power Minimization
Minimum sized devices are usually optimal for low-power.
Small W/L’s
Large W/L’s
Higher Voltage
Lower Voltage
Lower Capacitance
Higher Capacitance
Lecture 8 - 36Introduction to Digital Integrated Circuit DesignLow Power Design
Reducing Effective Capacitance
Global bus architecture Local bus architecture
Shared Resources incur Switching Overhead
Lecture 8 - 37Introduction to Digital Integrated Circuit DesignLow Power Design
Low Power Design
Reduce dynamic power• α: clock gating, sleep mode• C: small transistors (esp. on clock), short wires • VDD: lowest suitable voltage• f: lowest suitable frequency
Reduce static power• Selectively use ratioed circuits• Selectively use low Vt devices• Leakage reduction: stacked devices, body bias, low temperature
Lecture 8 - 38Introduction to Digital Integrated Circuit DesignLow Power Design
Summary
• Power Dissipation is becoming Prime DesignConstraint
• Low Power Design requires Optimization at all Levels
• Sources of Power Dissipation are well characterized
• Low Power Design requires operation at lowest possible voltage and clock speed