LECTURE 6 DIGITAL PHASE LOCK LOOPS (DPLLs) · 8/6/2018 · Lecture 06 – (8/9/18) Page 6-3 CMOS...

Lecture 06 – (8/9/18) Page 6-1

CMOS Phase Locked Loops © P.E. Allen - 2018

LECTURE 6 –DIGITAL PHASE LOCK LOOPS (DPLLs)

INTRODUCTION

Topics

• Noise Performance of the DPLL

• DPLL Design Procedure

• DPLL System Simulation

Organization:

Lecture 06 – (8/9/18) Page 6-2


NOISE PERFORMANCE OF THE DPLL

Combination of Noise and Information

In the LPLL, the noise and information signals are added because of the linear

multiplier PD.

The noise supression of DPLL’s is generally better than LPLL’s but no theory of noise

exists for the DPLL.

The following pages provide some insight into the noise performance of the DPLL.

Lecture 06 – (8/9/18) Page 6-3


Noise Performance of a DPLL with an EXOR PD

v1

v2'

vd

qj Phase noise at

a given inband

frequency

t

v1j

qj qj qj

Ideal Input

Input with

phase noise

superimposed

(phase jitter)

vd is proportional

to the phase noise.

\ LPLL noise theory

» DPLL noise theory.

t

vd100%

50%

0%

Detector

Ouput

Fig. 2.2-32

qj qj qj

Lecture 06 – (8/9/18) Page 6-4


Phase Noise in a Communication Signal

Consider the following simple noise model-

Lecture 06 – (8/9/18) Page 6-5


Input Signal-to-Noise Ratio

The input signal noise ratio of a pulse with phase jitter is defined as,

SNRi = 1

2 n12

where

n12

W2

36

where,

W

v1

t

Lecture 06 – (8/9/18) -6


Phase Noise in a DPLL with a JK Flip-Flop and a PFD

The basic difference is that the JK Flip-flop and PFD are edge-triggered.

When the input signal fades (v1→0), the reshaped signal can stick at a distinct logic

level.

Conclusion:

The noise suppression of the DPLL is about the same for all phase detectors as long as

none of the edges of the reference get lost by fading. If fading occurs, the EXOR offers

better noise performance.

Summary of DPLL Noise Performance:

Ps = input signal power

Pn = input noise power

Bi = input noise bandwidth

BL = noise bandwidth n

2

+ 1

4

SNRi = SNR of the input signal = Ps

Pn

SNRL = SNR of the loop = SNRi Bi

2BL

Lecture 06 – (8/9/18) Page 6-7


DPLL DESIGN PROCEDURE

Design Procedure

Objective: Design Ko, Kd, , and F(s)

Given: Phase detector and VCO

Steps:

1.) Specify f1(min), f1(max), f2(min), and f2(max).

2.) Design N unless otherwise specified.

Given: n(min) < n < n(max) and min < < max

For these ranges we get approximately,

n(max)

n(min) =

Nmax

Nmin and

max

min =

Nmax

Nmin → N = Nmean = NmaxNmin

3.) Determine . Typically, 0.7.

4.) If noise is of concern, continue with the next step, otherwise go to step 12.

5.) If there are missing edges in the input signal (fading), go to step 6, otherwise go to

step 7.

6.) Choose an EXOR phase detector. Continue with step 8.

Kd = VOH-VOL

Lecture 06 – (8/9/18) Page 6-8


Design Procedure – Continued

7.) Choose the JK Flip-flop or PFD as the phase detector.

Kd = VOH-VOL

2 (JK flip-flop)

Kd = VOH-VOL

4 (PFD)

8.) Specify BL.

BL should be chosen so that SNRi Bi

2BL ≥ 4

n12 → SNRi and Bi BL

• If N changes, this can create a problem because

BL = n

2

+ 1

4

and both n and vary with N.

• Need to check that BL(min) is large enough.

• If BL is too small, then N should be increased.

Lecture 06 – (8/9/18) Page 6-9



9.) Find Ko.

Ko = 2(max)-2(min)

vf(max)-vf(min)

10.) Find n given BL and .

n = 8BL

1+4

If N is variable, use BL and correspondingly to N = Nmean.

11.) Specify the loop filter.

Given n, , Ko, Kd, and N find 1, 2, and Ka (Ka>1).

Go to step 19.

12.) Continued from step 4.

Choose the PFD → Kd = VOH-VOL

4

13.) Find Ko.

Ko = 2(max)-2(min)

vf(max)-vf(min)

Lecture 06 – (8/9/18) Page 6-10



14.) Specify the type of loop filter. Use the passive lag filter as the others offer no

benefits.

15.) Determine n.

a.) Fast switching (Tp). Go to step 16.

b.) DPLL does not lock out when switching from Nofref to (No+1) fref. po < fref.

Go to step 20.

c.) Neither the pull-in time nor the pull-out range are critical. Go to step 21.

16.) Given the maximum Tp allowed for the largest frequency step, solve for 1 or 1+2.

17.) Find n.

Loop filter is passive: n = KoKd

N(1+2)

Active lag filter: n = KoKdKa

N1

Active PI filter: n = KoKd

N1

Lecture 06 – (8/9/18) Page 6-11



18.) Given n and , find 2.

2 = 2

n

If the system cannot be realized (negative values of 1 or 2), modify n and

appropriately.

19.) Given 1 and 2 (and Ka), determine the filter components.

20.) Given po and find n.

n po

11.55(+0.5)

21.) Given TL, find n from n 2/TL.

22.) Given n, find 1 and 1+2.

Passive lag filter: 1+2 = KoKd

Nn2

Active lag filter: 1 = KoKdKa

Nn2

Active PI filter: 1 = KoKd

Nn2

Lecture 06 – (8/9/18) Page 6-12


Flowchart of the DPLL Design Procedure

Specify the range of f1 and f2

Determine N or range of N

Determine z or range of z

Is Noise Suppression Required?

Are there missing edges?

Yes No

Choose the PFD, design the VCO and the loop filter

Given TP, Dwpo, or TLTPDwpo

TL

Use Dwpo and z to find wn Use TL to find wnUse TP to find t1or t1+t2

Estimate wn from t1

Use wn and z to find t1

Use wn and z to find t2

Use PFD

NoYes

Use EXOR

Specify the noise bandwidth, BL

Design the VCO

Use BL and z to find wn

Select the loop filter and determine t1, t2, (Ka)

Calculate the loop filter values Fig. 2.2-37

Lecture 06 – (8/9/18) Page 6-13


Design Example – A Frequency Synthesizer Using the 74HC/HCT4076

Design a DPLL frequency synthesizer using the CMOS 74HC/HCT4076 PLL. The

frequency sythesizer should be able to produce a set of frequencies in the range of 1MHz

to 2MHz with a channel spacing of 10kHz. Use a PFD and a passive lag-lead filter.

Design:

1.) Determine the ranges of the input and output frequencies.

f1 is constant at 10kHz. f2(min) = 1MHz and f2(max) = 2MHz

2.) Choose N.

Nmax = 2MHz

10kHz = 200 and Nmin =

1MHz

10kHz = 100

Nmean = Nmax·Nmin = 141

3.) Find . Start by choosing = 0.7 and find max and min.

max

min =

Nmax

Nmin = 2 and = max·min = 0.7

min2 2 =0.49 → min = 0.59 and max = 0.59 2 = 0.83

0.59 < < 0.83 which is consistent with our choice of .

4.) Select the PFD as the phase detector. For the 74HC/HCT4076, VOH = 5V and

VOL=0V. This gives a Kd = 5V/4 = 0.4 V/rad.

Lecture 06 – (8/9/18) Page 6-14


Design Example – Continued

5.) According to the data sheet of the 74HC4046A, the VCO operates linearly in the

voltage range of vf = 1.1V to 3.9V as shown.

Ko = 2x106x2

3.9-1.1 = 2.2x106 rads/V·sec

The data sheet also requires calculation of

two resistors, R1 and R2, and a capacitor, C1.

Using the graphs from the data sheet gives,

R1 = 47k, R2 = 130k, and C1 = 100pF.

6.) Assume the loop should lock with 1ms.

TL = 1ms → n = 2/TL = 6280 rads/sec.

7.) Using a passive loop filter we get,

1+2 = KoKd

Nn2 =

2.2x106·0.4

141·62802 = 161µs

8.) 2 = 2

n =

2·0.7

6280 = 223µs!!! (The problem is that 1+2 is too small)

Go back and choose TL = 2ms → n = 2/TL = 3140 rads/sec.

1+2 = KoKd

Nn2 =

2.2x106·0.4

141·31402 = 633µs and 2 = 2

n =

2·0.7

3140 = 446µs → 1 = 187µs

10 2 3 4 5

f2 (MHz)

2

1

3.9V

vf(V)

Fig. 2.2-35

1.1V

Lecture 06 – (8/9/18) Page 6-15


Design Problem – Continued

9.) Design the loop filter.

For optimum sideband supression, C should be large. Choose C = 0.33µF.

R1 = 1

C =

187x10-6

0.33x10-6 = 567 and R2 = 2

C =

446x10-6

0.33x10-6 = 1.351

The data sheet requires that R1+R2 ≥ 470 which is satisfied.

Block diagram of the DPLL frequency synthesizer design of this example:

PC1

(EXOR)

PC2

(PFD)

PC3

(JK)

PCPoutVCO

PC2out

R1=567W

R2=1.35kW

C = 0.33mF

R1=

47kW

R2=

130kW

C1=100pF

74HC4046A

C1A C1B

VCOout

SIGin

COMPin

v1(10kHz)

v2'

VCOin R1 R2

74HC40102

(40103)CP

TE PL MR

TC

PEP0····P7

Data N

+5V

v2'

Fig. 2.2-36

Lecture 06 – (8/9/18) Page 6-16


Simulation of the DPLL Example

The block diagram of this example is shown below.

The PFD-charge pump combination can be approximated as†

“KdF(s)” = Kd(1+s2)

s(1+2)

Therefore, the loop gain becames

LG(s) = KoKd(1+s2)

s2(1+2) =

Kv (1+s2)

(s+)2(1+2) (the factor is used for simulation purposes)

For this problem,

Kd = 0.4V/rad., Ko = 2.2x106, 2 = 446µs, and 2+2 = 633µs. Also choose = 0.01.

† R.E. Best, “Phase-Locked Loops – Design, Simulation, and Applications,” 4th Ed., McGraw-Hill, NY, p. 103

Kd

PD

F(s)

LPF

Ko

VCO

s

1

N

q1(s)

q2'(s)q2(s)

Optional¸ N Counter

Fig. 2.2-25

Lecture 06 – (8/9/18) Page 6-17


Simulation of the DPLL Example – Continued

PSPICE Input File DPLL Design Problem-Open Loop Response - Best

VS 1 0 AC 1.0

R1 1 0 10K

* Loop bandwidth = Kv =8.8x10E5 sec.-1 Tau1=187E-6 Tau2=446E-6 N=141

ELPLL 2 0 LAPLACE {V(1)}= {8.8E+6/(S+0.01)/141*(0.446E-3*S+1)/(S+0.01)/0.633E-3}

R2 2 0 10K

*Steady state AC analysis

.AC DEC 20 10 100K

.PRINT AC VDB(2) VP(2)

.PROBE

.END

Simulation Results:

Note that the phase is very

close to 0° and |LG|>>1 at

low frequencies which is

typical of type II systems.

-40

-20

0

20

40

60

80

100

10 100 1000 10 4 10 5

dB

or

Deg

rees

Frequency (Hz)

|LG|

LG Phase

wc

Phase

Margin

» 84°

Lecture 06 – (8/9/18) Page 6-18


DPLL SYSTEM SIMULATION

Examples of Case Studies using the Best Software†

PLL Parameters-

Supply voltages:

Positive supply = 5V Negative supply = -5V

Phase detector:

Vsat+ = 4.5V Vsat

- = 0.5V

Loop filter:

1 = 500µs 2 = 50µs

Oscillator:

Ko = 130,000 rads/V·sec Vsat+ = 4.5V Vsat

- = 0.5V

The simulation program will be used to verify the following calculated values:

n = 17,347 rads/sec. (calculated prior to simulation)

= 0.486 (calculated prior to simulation)

fpo = 7719 Hz

fp = 13,192 Hz

† Roland E. Best, Phase-Locked Loops – Design, Simulation, and Applications, 4th ed., McGraw-Hill Book Co., 1999, New York, NY

Lecture 06 – (8/9/18) Page 6-19


Case 1 – System Benchmark

vd(mV)

t(µs)

vd

vf

Lecture 06 – (8/9/18) Page 6-20


Case 2 - f = 8000Hz

vd(V) vf

vd

Phase error

≥ 90°

Lecture 06 – (8/9/18) Page 6-21


Case 3 – Loop Just Locks Out

vd

vf

vd(V)

vf

Loop pulls out

vd

Lecture 06 – (8/9/18) Page 6-22


Case 4 – Pull-In Range Verification

vd(V)

vf

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

vd

Loop will not pull back in for df > 14,200 Hz

Lecture 06 – (8/9/18) Page 6-23


Case 5 – PFD and Illustration of a Virtually Infinite Pull-In Range

fp = ±40kHz f = 35 kHz to avoid clipping of vf.

vd(V) vd

vf

Tp 1.5ms

Lecture 06 – (8/9/18) Page 6-24


Case 6 – EXOR with Active PI Filter

Tp 5ms

vd(V)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

vf

vd

Lecture 06 – (8/9/18) Page 6-25


SUMMARY

• Illustrated the Noise Performance of the DPLL

• Presented a DPLL Design Procedure

• Showed how to do DPLL System Simulation

• The DPLL is much more compatible with IC technology and is the primary form of

PLL used for frequency synthesizers

LECTURE 6 DIGITAL PHASE LOCK LOOPS (DPLLs) · 8/6/2018 · Lecture 06 – (8/9/18) Page 6-3 CMOS...

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