CSCE 5730: Digital CMOS VLSI Design 1

CSCI 5330Digital CMOS VLSI Design

Instructor: Saraju P. Mohanty, Ph. D.

Lecture 5: Microwind/DCSH

NOTE: The figures, text etc included in slides are borrowedfrom various books, websites, authors pages, and othersources for academic purpose only. The instructor doesnot claim any originality.

CSCE 5730: Digital CMOS VLSI Design 2

Lecture Outline

• Microwind Tool• DCSH Tool• Silicon Tool

Source:1. http://www.microwind.org2. Microwind Based Design (http://vsp2.ecs.umass.edu/vspg/658/

TA_Tools/microwind/Microwind.html)

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Microwind and DSCH• Microwind is a tool for designing and simulating circuits

at layout level. The tool features full editing facilities(copy, cut, past, duplicate, move), various views (MOScharacteristics, 2D cross section, 3D process viewer),and an analog simulator.

• DSCH is a software for logic design. Based on primitives,a hierarchical circuit can be built and simulated. It alsoincludes delay and power consumption evaluation.

• Silicon is for 3D display of the atomic structure of silicon,with emphasis on the silicon lattice, the dopants, and thesilicon dioxide.

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Microwind and DSCH …• Download the followings from

http://www.microwind.org/–Microwind3–DSCH3– User Manual: http://intrage.insa-

toulouse.fr/~etienne/microwind/manual_lite.pdf• Installation and Use:

– Unzip the files above to be able to work withMicrowind.

– Read the reference manual for the software.– Double click on Microwind3.exe to start the layout

editor or on Dsch3.exe to start the schematic editor.

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Tools from Microwind

http://www.microwind.org/• Microwind• DSCH• Microwind3 Editor• Microwind 2D viewer• Microwind 3D viewer• Microwind analog simulator• Microwind tutorial on MOS devices• View of Silicon Atoms

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Microwind and DSCH : NOR Example

• We will learn both the design flow and the CADtools.

• The specifications we are going to see may bedifferent for different foundry and technology.

• Design Example (3 Levels) : NOR Gate– Logic Design– Circuit Design– Layout Design

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Microwind / DSCH NOR Example: Logic

• Open the SchematicEditor in Microwind(DSCH3). Click on thetransistor symbol in theSymbol Library on theright.

• Instantiate NMOS orPMOS transistors fromthe symbol library andplace them in the editorwindow.

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Microwind / DSCH NOR Example: Logic

• Instantiate 2 NMOS and 2PMOS transistors.

• Connect the drains andsources of transistors.

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Microwind / DSCH NOR Example: Logic

• Connect Vdd and GNDto the schematic.

• Connect input button andoutput LED.

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Microwind / DSCH NOR Example: Logic

• You now have NOR schematicready.

• Use your logic simulator toverify the functionality of yourschematic.

• The next step is to simulatethe circuit and check forfunctionality.

• Click on, Simulate -> Startsimulation.

• This brings up a SimulationControl Window.

• Click on the input buttons toset them to 1 or 0. Red colorin a switch indicates a '1'.

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Microwind / DSCH NOR Example: Logic

• Inputs: 0 0 • Inputs: 0 1

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Microwind / DSCH NOR Example: Logic

• Inputs: 1 0 • Inputs: 1 1

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Microwind / DSCH NOR Example: Logic

• The simulation output can be observed as a waveform after theapplication of the inputs as above. Click on the timing diagram icon in theicon menu to see the timing diagram of the input and output waveforms.

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Microwind / DSCH NOR Example: Circuit

• Simulate your system withyour hand calculatedtransistor sizes.

• Click File -> Make VerilogFile. The Verilog,Hierarchy and Netlistwindow appears. Thiswindow shows the verilogrepresentation of NORgate. Click OK to save theVerilog as a .txt file.

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Microwind / DSCH NOR Example: Circuit

• Open the layout editorwindow in Microwind.Click File -> SelectFoundry and select X.rul.This sets your layoutdesigns in X technology.

• Click on Compile ->Compile Verilog File. AnOpen Window appears.Select the .txt verilog filesaved before and open it.

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Microwind / DSCH NOR Example: Circuit

• After selecting the .txt file,a new window appearscalled Verilog file.

• Click on Size on the righttop menus. This shows upthe NMOS and PMOSsizes. Set the sizesaccording to choice.

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Microwind / DSCH NOR Example: Circuit• Click Compile and then Back

to editor in the Verilog FileWindow. This creates alayout in layout editorwindow using automaticlayout generation procedure.

• Add a capacitance to theoutput of the design. Thevalue of the capacitancedepends on your choice.

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Microwind / DSCH NOR Example: Circuit

• Click on OK. Thecapacitance is shown onthe left bottom cornerwith a value of 0.015fF.

• Click on the label marked In1. Awindow appears. Click on thePulse option in the window. Inserta 01 sequence for that specificinput and click on Insert. Thenclick on Assign. Perform thisassignment on the other inputs.

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Microwind / DSCH NOR Example: Circuit• Click Simulate -> Run simulation. A simulation window appears with

inputs and output, shows the tphl, tplh and tp of the circuit. The powerconsumption is also shown on the right bottom portion of the window.

• If you are unable to meet the specifications of the circuit change thetransistor sizes. Generate the layout again and run the simulations tillyou achieve your target delays.

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Microwind / DSCH NOR Example: Layout

• Design the layoutmanually

• Open the layout editorwindow in Microwind.Click File -> SelectFoundry and select X.rul

• Vdd and GND rails are ofMetal1. The top rail is usedas Vdd and the bottom oneas GND. Click on Metal 1 inthe palette and then createthe required rectangle in thelayout window.

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Microwind / DSCH NOR Example: Layout

• The next step is to buildthe NMOS transistors.Click on the transistorsymbol in the palette. Setthe W, L of the transistor.

• Then click on Generatedevice. The source of thetransistor is connected tothe GND rail.

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Microwind / DSCH NOR Example: Layout

• Create another NMOS andplace it in parallel to the firstNMOS device. We share thetwo devices' drain diffusions. ADRC check can be run byclicking on Analysis -> DesignRule Checker.

• The next step is to placetwo PMOS transistors inseries.

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Microwind / DSCH NOR Example: Layout• Place the PMOs transistor on

layout close to the Vdd rail on thetop. To construct two PMOStransistors in series, diffusions areshifted to a side and another polyline is added as second transistor.The diffusion is shared to savearea and reduce capacitance.

• The next step is toconnect the inputs and theoutput of the twotransistors.

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Microwind / DSCH NOR Example: Layout

• Poly inputs are connected• Metal output is

connected.

• The next step is to connectthe poly to metal1 and thento metal2. The first symbol inthe first row of the palette isthe poly to metal1 contact.

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Microwind / DSCH NOR Example: Layout

• Then we connect themetal1 to metal2 contactto the previous contact.This is the 4th contact onthe first row.

• The next step is toconnect the outputMetal1 to Metal2. Onceagain use the 4thcontact in the first row.

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Microwind / DSCH NOR Example: Layout

• Now we connect metal2 to the two inputs and one outputand bring them to the top to go out of the cell.

• Observe the two inputs (left & right) and an output (middle)above the Vdd rail in dark blue color.

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Microwind / DSCH NOR Example: Layout

• Now we label the inputs and output as In1, In2 and out.Click on Add a Pulse Symbol in the palette (5th from theright in the 3rd row). Then click on the metal2 of one of theinputs. A window appears. Change the name of the inputsignal. Insert a 01 sequences and click on Insert. The clickon Assign. Similarly assign the 2nd input a pulse.

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Microwind / DSCH NOR Example: Layout

• Now select the Visible Node symbol from the palette (7thin the third row). Select it and click on the output. The 'Adda Visible Property' window appears. Change the labelname to out. Select Visible in Simulation. Click on Assign.Now the output is also labeled.

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Microwind / DSCH NOR Example: Layout• Select Vdd Supply and GND from the

palette (third row). Also click on thecapacitor (3rd in 2nd row) symbol andadd it to the output. Also, extend the p-well into the Vdd Rail. The click on Edit-> Generate -> Contacts. Select PATHand then in Metal choose Metal1 andN+ polarization.

• To run the Simulation of yourcircuit, click on Simulate -> StartSimulation. Depending on the inputsequences assigned at the inputthe output is observed in thesimulation. The power value is alsogiven.

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More Reading from Microwind Sitehttp://intrage.insa-toulouse.fr/~etienne/microwind/docs.html• Introducing basic design rules. MOS design

rules, interconnect design rules, supply designrules.

• Technology influence on design rules resistanceeffect, capacitance effect, propagation.

• Specific design rules salicide, ldd, antenna ratio,matching, supply rules, ESD.

• Introducing CMOS 90nm technology• A very simple four-bit microprocessor designed

and simulated at gate level with DSCH3