Lecture 5 Lecture 5 Fault Modeling Fault

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Jan. 26, 2001 VLSI Test: Bushnell-Agrawal/Lecture 5 1

Lecture 5

Fault Modeling

Lecture 5

Fault Modelings Why model faults?s Some real defects in VLSI and PCB

s Common fault modelss Stuck-at faults

s Single stuck-at faultss Fault equivalences

Fault dominance and checkpoint theorems Classes of stuck-at faults and multiple faults

s Transistor faultss Summary




Observed PCB

Defects

Observed PCBDefects

Defect classes

ShortsOpens

Missing components Wrong componentsReversed componentsBent leads

Analog specificationsDigital logicPerformance (timing)

Occurrence frequency (%)

511

613

68

555

Ref.: J. Bateson, In-Circuit Testing , Van Nostrand Reinhold, 1985.




Common FaultModels

Common FaultModels

s Single stuck-at faultss Transistor open and short faultss Memory faultss PLA faults (stuck-at, cross-point,

bridging)s Functional f aults (processors)s Delay faults (transit ion, path)s Analog faultss For more examples, see Section 4.4 (p.

60-70) of the book.




Single Stuck-at Faultingle Stuck-at Faults

Three properties define a single stuck-at faults Only one line is faultys The faulty line is permanently set to 0 or 1s The fault can be at an input or output of a gate

s Example: XOR circuit has 12 fault sites ( ) and24 single stuck-at faults

a

b

c

d

e

f

10

g h i 1

s-a-0 j

k

z

0(1)1(0)

1

Test vector for h s-a-0 fault

Good circuit valueFaulty circuit value




Fault Equivalenceault Equivalences Number of fault sites in a Boolean gate circuit

= #PI + #gates + # (fanout branches) .s Fault equivalence: Two faults f1 and f2 are

equivalent if all tests that detect f1 also

detect f2.s If faults f1 and f2 are equivalent then the

corresponding faulty functions are identical.s Fault collapsing: All single faults of a logic

circuit can be divided into disjoint equivalencesubsets, where all faults in a subset aremutually equivalent. A collapsed fault setcontains one fault from each equivalencesubset.




Equivalence Examplequivalence Example

sa0 sa1sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

sa0 sa1

Faults in redremoved byequivalencecollapsing

20Collapse ratio = ----- = 0.625

32




Fault Dominanceault Dominances If all tests of some fault F1 detect another fault

F2, then F2 is said to dominate F1.s Dominance fault collapsing: If fault F2

dominates F1, then F2 is removed from the

fault list.s When dominance fault collapsing is used, it is

sufficient to consider only the input faults of Boolean gates. See the next example.

s In a tree circuit (without fanouts) PI faults forma dominance collapsed fault set.

s If two faults dominate each other then they areequivalent.




Dominance Exampleominance Example

s-a-1F1

s-a-1F2 001

110 010000

101100

011

All tests of F2

Only test of F1s-a-1

s-a-1s-a-1s-a-0

A dominance collapsed fault set




Checkpointsheckpointss

Primary inputs and fanout branches of acombinational circuit are called checkpoints .s Checkpoint theorem: A test set that detects

all single (multiple) stuck-at faults on all

checkpoints of a combinational circuit, alsodetects all single (multiple) stuck-at faults inthat circuit.

Total fault sites = 16

Checkpoints ( ) = 10




Classes of Stuck-atFaults

Classes of Stuck-atFaults

s Following classes of single stuck-at faults areidentified by fault simulators:

s Potentially-detectable fault -- Test produces anunknown (X) state at primary output (PO);

detection is probabilistic, usually with 50%probability.

s Initialization fault -- Fault prevents initialization of the faulty circuit; can be detected as a potentially-detectable fault.

s Hyperactive fault -- Fault induces much internalsignal activity without reaching PO.

s Redundant fault -- No test exists for the fault.s Untestable fault -- Test generator is unable to find

a test.




Multiple Stuck-atFaults

Multiple Stuck-atFaults

s A multiple stuck-at fault means that any setof lines is stuck-at some combination of (0,1)values.

s The total number of single and multiplestuck-at faults in a circuit with k single faultsites is 3 k -1 .

s A single fault test can fail to detect thetarget fault if another fault is also present,however, such masking of one fault byanother is rare.

s Statistically, single fault tests cover a verylarge number of multiple faults.




Transistor (Switch)Faults

Transistor (Switch)Faults

s MOS transistor is considered an ideal switchand two types of faults are modeled:

s Stuck-open -- a single transistor is permanentlystuck in the open state.

s Stuck-short -- a single transistor is permanentlyshorted irrespective of its gate voltage.

s Detection of a stuck-open fault requires twovectors.

s Detection of a stuck-short fault requires themeasurement of quiescent current ( IDDQ ).




Stuck-Open Exampletuck-Open Example

Two-vector s-op test can be constructed by ordering two s-at tests A

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-open

1

0

0

0

0 1(Z)

Good circuit states

Faulty circuit states

Vector 1: test for A s-a-0(Initialization vector)

Vector 2 (test for A s-a-1)




Stuck-Short Exampletuck-Short Example

A

B

VDD

C

pMOSFETs

nMOSFETs

Stuck-short

1

0

0 (X)

Good circuit state

Faulty circuit state

Test vector for A s-a-0

IDDQ path in

faulty circuit




Summaryummarys

Fault models are analyzable approximations of defects and are essential for a testmethodology.

s For digital logic single stuck-at fault model

offers best advantage of tools and experience.s Many other faults (bridging, stuck-open andmultiple stuck-at) are largely covered by stuck-at fault tests.

s Stuck-short and delay faults and technology-dependent faults require special tests.

s Memory and analog circuits need other specialized fault models and tests.

Lecture 5 Lecture 5 Fault Modeling Fault

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