Lecture 5: Arithmetic › courses › archive › fall15 › cos375 › lec… · 1 Lecture 5:...
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Lecture 5: Arithmetic
COS / ELE 375
Computer Architecture and Organization
Princeton University Fall 2015
Prof. David August
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Binary Representation of Integers
• Two physical states: call these 1 and 0
• Collections of these bits can represent numbers
Binary Decimal 0 0 1 1
10 2 11 3
100 4 101 5 110 6 111 7
1000 8 … … 1{n} 2n-1
A Familiar Assignment of Meaning
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Size and Overflow in Unsigned Integers
Number of bits determines unsigned integer range Overflow: • 8-bit integer ! 111111112 (= 25510) • Add 1 • What happens?
Bits Integer Range 8 0 - 255 16 0 - 65,535 32 0 - 4,294,967,295 64 0 - 18,446,744,073,709,551,615
Binary Decimal 0 0 1 1
10 2 … … 1{n} 2n-1
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Overflow in Unsigned Addition
Modulo Arithmetic: UAddw(u, v) = u + v mod 2w
• • • • • •
uv+
• • • u + v• • •
True Sum: w + 1 bits
Operands: w bits
Discard Carry: w bits UAddw(u , v)
UAdd w ( u , v ) = u + v u + v < 2 w
u + v � 2 w u + v ≥ 2 w " # $
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Visualization of Integer Addition • Compute true sum Add4(u, v) • Values increase linearly with u and v • Forms planar surface
0
5
10
15
20
25
30
35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 2 4 6 8 10 12 140
2
4
6
8
101214
0
5
10
15
20
25
30
Add4(u , v)
u
v
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0 2 4 6 8 10 12 140
2
4
6
810
1214
0
2
4
6
8
10
12
14
16
Visualization of Unsigned Addition
0
2w
2w+1
UAdd4(u, v)
u
v
True Sum
Modulo Sum
Overflow
Overflow
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Modulo Arithmetic
Modulo Addition Forms an Abelian Group • Closed under addition
• 0 ≤ UAddw(u, v) ≤ 2w –1
• Commutative • UAddw(u, v) = UAddw(v, u)
• Associative • UAddw(t, UAddw(u, v)) = UAddw(UAddw(t, u), v)
• 0 is additive identity • UAddw(u, 0) = u
• Every element has additive inverse • Let UCompw(u) = 2w – u • UAddw(u , UCompw(u)) = 0
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Overflow Possibilities 1. Hardware does not detect overflow (MIPS: addu, addiu, subu)
• Software checks if necessary • Reacts in manner specified
2. Hardware records overflow • Software decides whether or not to do anything • Software system / language specific
3. Hardware throws exception(interrupt) (MIPS: add, addi, sub)
• Control jumps to predefined address for exception • Interrupted address is saved for possible resumption
Exception - an unscheduled procedure call EPC - Exception PC records excepting instruction address
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Detecting Unsigned Overflow
• Task: • Given s = UAddw(u, v) • Determine if s = u + v
• Claim: • Overflow iff s < u • ovf = (s < u) • By symmetry iff s < v
• Proof: • 0 ≤ v < 2w
• No overflow ⇒ s = u + v ≥ u + 0 = u • Overflow ⇒ s = u + v – 2w < u + 0 = u
u v
2ws
u v
2ws
No Overflow:
Overflow:
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What about Negative Numbers?
• We have been looking at unsigned numbers • What about negative or signed numbers?
• Need new interpretation of bits • Some patterns interpreted as negative numbers
Bits Patterns 8 256 16 65,536 32 4,294,967,296 64 18,446,744,073,709,551,616
Binary Pattern 0 1 1 2
10 3 … … 1{n} 2n
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Key Standard Pattern Assignments
• Which one is best? • Issues?
• Balance • Zeros • Ease of operations
Bit Pattern Sign Magnitude One�s Complement
Two�s Complement
000 +0 +0 0 001 +1 +1 +1 010 +2 +2 +2 011 +3 +3 +3 100 -0 -3 -4 101 -1 -2 -3 110 -2 -1 -2 111 -3 -0 -1
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Most Common: Two�s Complement
Bit Pattern Two�s Complement
000 0 001 +1 010 +2 011 +3 100 -4 101 -3 110 -2 111 -1
• �Invert and Add 1� to negate • Sign Bit • Zeros, Range • What about arithmetic?
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Unsigned and Two�s Complement
• Unsigned Values
• UMin = 0 • UMax = 2w – 1
• Two�s Complement
• TMin = –2w–1
• TMax = 2w–1 – 1
B2T (X ) = −xw−1 ⋅2w−1 + xi ⋅2
i
i=0
w−2
∑B2U(X ) = xi ⋅2i
i=0
w−1
∑
SignBit
Decimal Hex Binary UMax 65535 FF FF 11111111 11111111 TMax 32767 7F FF 01111111 11111111 TMin -32768 80 00 10000000 00000000 -1 -1 FF FF 11111111 11111111 0 0 00 00 00000000 00000000
Values for W = 16
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0
TMax
TMin
–1–2
0
UMaxUMax – 1
TMaxTMax + 1
Two�s Compliment
Range
UnsignedRange
Representation Relationship
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Sizes and C Data Types
char, short, int, long int • Refer to number of bits of integer • Most machines: signed two�s complement unsigned <type> • Same number of bits as signed counterparts • Unsigned integer
C Data Type MIPS, x86 Alpha
char 8 bits 8 bits
short 16 bits 16 bits
int 32 bits 32 bits
long int 32 bits 64 bits
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Sign Extension char minusFour = -4; short moreBits; moreBits = (short)minusFour; Given w bit signed integer, return equivalent w+k bit signed integer
Sign Extend:
• • • X
X ' • • • • • •
• • •
w
wk
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Sign Extension Proof of Correctness Outline
• Prove Correctness by Induction on k • Induction Step: extending by single bit maintains value
lb, lbu - load byte (sign extend), load byte unsigned
- • • • X
X ' - + • • •
w+1
w
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Two�s Complement Addition
• TAdd and UAdd have identical Bit-Level Behavior!
• • •
• • •
u
v+
• • • u + v
• • •
True Sum: w + 1 bits
Operands: w bits
Discard Carry: w bits TAddw(u, v)
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-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7-8
-6
-4
-2
02
46
-8
-6
-4
-2
0
2
4
6
8
Visualizing Two�s Compliment Addition
• Range: -8 to +7 • If sum ≥ 2w–1
• Becomes negative • At most once
• If sum < –2w–1 • Becomes positive • At most once
TAdd4(u , v)
u
v
PosOver
NegOver
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Characterizing TAdd
• True sum requires w+1 bits • Drop MSB
–2w –1
–2w
0
2w –1
2w–1True Sum
TAdd Result
1 000…0
1 100…0
0 000…0
0 100…0
0 111…1
100…0
000…0
011…1
PosOver
NegOver
TAddw (u,v) =
u + v + 2w−1 u + v < TMinwu + v TMinw ≤ u + v ≤ TMaxwu + v − 2w−1 TMaxw < u + v
#
$ %
& %
(NegOver)
(PosOver)
u
v
< 0 > 0
< 0
> 0
NegOver
PosOverTAdd(u , v)
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Detecting Two�s Complement Overflow
• Task: • Given s = TAddw(u, v) • Determine if s = Addw(u, v)
• Claim: • Overflow iff either:
• u, v < 0, s ≥ 0 (NegOver) • u, v ≥ 0, s < 0 (PosOver)
• ovf = (u<0 == v<0) && (u<0 != s<0);
• Proof: • Obviously, if u ≥ 0 and v < 0, then TMinw ≤ u + v ≤ TMaxw
• Symmetrically if u < 0 and v ≥ 0 • Other cases from analysis of TAdd
0
2w –1
2w–1PosOver
NegOver
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Negation, Inversion
Inversion: • Flip all 0�s to 1�s and vice versa: 0011 => 1100 • What does this do to the two�s complement value?
Negation: • Two�s complement: invert all bits and add 1 • Example:
310 = 0011 invert(0011) + 1 ! 1100 + 1 ! 1101 1101 = -310
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Two�s Complement Negation
• Mostly like Integer Negation • TComp(u) = –u
• TMin is Special Case • TComp(TMin) = TMin • Note Also: TComp(0) = 0
• Negation in C (x = -x;) is Actually TComp
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Comparing Two�s Complement Numbers
• Given signed numbers u, v • Determine whether or not u > v • Return true for shaded region:
• Bad Approach: • Test (u – v) > 0 • Problem: Thrown off by Overflow
u
v
< 0 > 0
< 0
> 0
u < v
u > v
u==v
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-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7-8
-6
-4
-2
02
46
-8
-6
-4
-2
0
2
4
6
8
Comparing with TSub
NegOver: • u < 0, v > 0 • TSub4(u, v) > 0 PosOver: • u > 0, v < 0 • TSub4(u, v) < 0
u
v
< 0 > 0
< 0
> 0
u-v
+ -
-
+
+ +
-
-
NegOver
PosOver
TSub4(u, v)
u
v
PosOver
NegOver
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Building It! The ALU
• ALU takes 2 N-bit numbers and operates upon them • Let�s start by supporting MIPS and, andi, or, and ori • Outline: Build a 1 bit ALU, and use 32 of them
xn x2 x1 x0
yn y2 y1 y0
zn z2 z1 z0
ALU
Operation
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1-bit ALU for and, or, add
b
0
2
R e s u l t
O p e r a t i o n
a
1
C a r r y I n
C a r r y O u t
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andi and ori Truth Table
Op Ai Bi Result
0 (andi) 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 (ori) 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Result = AiBi(Op) + (Ai + Bi)(Op)
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Addition
• 1-bit ALU for addition:
• Carry is majority function (more ones than zeros?) • Sum is a parity function (odd number of 1�s?)
cout = ab + acin + bcin sum = a XOR b XOR cin
sum
cout
a
b
cin
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Building a 32 bit ALU for and, or, add
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
b
0
2
R e s u l t
O p e r a t i o n
a
1
C a r r y I n
C a r r y O u t
Forms a Ripple Carry Adder
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What about subtraction?
• Two's complement approach: just negate b and add. • An elegant solution - use the carry in on bit 0:
0
2
Result
Operation
a
1
CarryIn
CarryOut
0
1
Binvert
b
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Speed of 32 bit ALU for and, or, add, sub
Result31a31
b31
Result0
CarryIn
a0
b0
Result1a1
b1
Result2a2
b2
Operation
ALU0
CarryIn
CarryOut
ALU1
CarryIn
CarryOut
ALU2
CarryIn
CarryOut
ALU31
CarryIn
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A Performance Problem?
• Is a 32-bit ALU as fast as a 1-bit ALU? • Can you see the ripple? How could you get rid of it?
c1 = b0c0 + a0c0 + a0b0
c2 = b1c1 + a1c1 + a1b1
• Other ways to do addition? • ripple carry adder - this approach, too slow! • complete sum-of-products - huge! • Somewhere in between…
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Without carry in value, what can we do?
ci+1 = bici + aici + aibi ci+1 = (aibi) + (ai + bi)ci
When is the carry generated? gi=ai bi When does the carry propagate? pi=ai+bi
ci+1 = (aibi) + (ai + bi)ci ci+1 = gi + pi ci ci+1 = gi + pici
Carry-Lookahead Adder (CLA)
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c1 = g0 + p0c0 c2 = g1 + p1c1 c3 = g2 + p2c2 c4 = g3 + p3c3 c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
Is this faster? Carry out = 2 gate delays, 4 bit adder • Ripple Carry: 4 * 2 = 8 gate delays • CLA: 1 to compute all g/p + 2 for SOP = 3 gate delays
Carry-Lookahead Adder (CLA)
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Use CLA principle to build bigger adders
16 bit CLA adder too big Compose approaches: • Use a set of 4-bit CLA adders • Link them together:
• Ripple carry between CLA blocks • Or, build another level of CLA
CarryIn
Result0--3
ALU0
CarryIn
Result4--7
ALU1
CarryIn
Result8--11
ALU2
CarryIn
CarryOut
Result12--15
ALU3
CarryIn
C1
C2
C3
C4
P0G0
P1G1
P2G2
P3G3
pigi
pi + 1gi + 1
ci + 1
ci + 2
ci + 3
ci + 4
pi + 2gi + 2
pi + 3gi + 3
a0 b0 a1 b1 a2 b2 a3 b3
a4 b4 a5 b5 a6 b6 a7 b7
a8 b8 a9 b9
a10 b10 a11 b11
a12 b12 a13 b13 a14 b14 a15 b15
Carry-lookahead unit
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c4 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0 G0 = g3 + p3g2 + p3p2g1 + p3p2p1g0 P0 = p3p2p1p0
Pi and Gi are to a 4-bit adder unit as
pi and gi are to a single bit adder
C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0
Carry-Lookahead Adder (CLA) Hierarchy
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Use CLA principle to build bigger adders
How Fast for 16 bits? Carry out = 2 gate delays
Ripple Carry: • 16 * 2 = 32 gate delays 2 Level CLA, using only 4-bit CLA Units: • 1 gate delays for all gi/pi • 2 gate delays for all Gi/Pi from gi/pi • 2 gate delays for cout from all G and P • Total of 5 gate delays!
CarryIn
Result0--3
ALU0
CarryIn
Result4--7
ALU1
CarryIn
Result8--11
ALU2
CarryIn
CarryOut
Result12--15
ALU3
CarryIn
C1
C2
C3
C4
P0G0
P1G1
P2G2
P3G3
pigi
pi + 1gi + 1
ci + 1
ci + 2
ci + 3
ci + 4
pi + 2gi + 2
pi + 3gi + 3
a0 b0 a1 b1 a2 b2 a3 b3
a4 b4 a5 b5 a6 b6 a7 b7
a8 b8 a9 b9
a10 b10 a11 b11
a12 b12 a13 b13 a14 b14 a15 b15
Carry-lookahead unit
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Summary
• Unsigned Numbers • Signed Numbers: Signed Magnitude, One�s
Complement, Two�s Complement • Two�s Complement
• Addition • Inversion, Negation • Subtraction, Comparison
• ALU: and, or, add, sub • Ripple Carry, Carry Lookahead Reading: • Pay particular attention to overflow detection logic