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Verilog HDL

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In = Clock, Reset, Input ...

Out = X, Y Machine State = S1, S2

Designspecification

State Diagram

State Table

Boolean Expand Simplified

Manual

Manual

Manual

Traditional design flow of sequential logic circuit

Implement onseveral ICs

Manual

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GENERAL PROCEDURE FOR DESIGNINGSYNCHRONOUS CIRCUIT

1. Understand the specifications of the sequential circuit.

Determine the types and number of input and output

terminals. Note: all CLK inputs of FF are connected to a

common clock source.

2. Identify the number of states and determine the number of

flip-flops used. Produce a State Diagram.3. Translate the State Diagram into a State Table. Note: the

values of Decoder States determine the changes from

Present State to Next State.

4. Establish the Boolean Expressions for all decoders andoutput functions (with respect to Present State and Input

State (if any) as variables.

5. Simplify the expressions using K-map or Boolean Algebra

6. Draw the logic circuit diagram.

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Design

specification

Designdescription

Implement on ONECPLD/FPGA chip

HDL Syntax

Manual(programming)

Automatic

Sequential Logic Circuit Implement by PLD Technology

In = Clock, Reset, Input ...

Out = X, Y Machine State = S1, S2

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Implementations of A Finite

State Machine (FSM) UsingVerilog

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FSM Design Using Verilog

Standard model for a Finite State Machine

FSM is a computational model consisting of a finite number of

states and transitions between those states, possibly withaccompanying actions. [IEEE 610]

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FSM Design Using Verilog

Example1: Consider the following State Diagram. Specifications:

No of finite states = 6 (A, B, C, D, E and F)

No of inputs = 1

No of outputs = 3

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FSM Design Using Verilog

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FSM Design Using Verilog

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FSM Design Using Verilog

module fsm (input i, clock, reset,

output reg [2:0] out);

reg [2:0] currentState, nextState;

localparam [2:0]

A = 3'b000B = 3'b001,

C = 3'b010,

D = 3'b011,

E = 3'b100,

F = 3'b101;

The localparam statement specifies thestate assignment for the system.

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FSM Design Using Verilog

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FSM Design Using Verilog

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User Defined Primitives (UDPs)

UDP is a set of gate primitives specified anddesigned by the user. UDP can be either

combinatorial or sequential.

Definition:

Why UDP? UDP is a very compact and efficient way of

describing a possibly arbitrary block of logic

UDP can reduce the pessimism with respect tothe unknown x value in the simulators three

valued logic, thus creating more realistic modelsfor certain situations

UDP can increase simulation efficiency

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Creating UDP (Combinational Logic)

UDP are defined in a manner similar to a truth table

enumeration of a logic function.

UDP are defined outside modules.

Started with keyword primitive followed by a UDP nameand declarations ofoutput and inputs (in bracket).

A table (similar to a Truth Table) is then specifiedshowing the value of the output for the variouscombinations of the inputs.A colon separates theoutput on its right from the inputs on its leftEnded with keyword endprimitive.

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There are a number of rules that must be considered:

Primitives can have multiple input ports, but exactly

only one output port. They may not havebidirectional inout ports.

The output port must be the first port in the portlist.

All primitive ports are scalar. No vector ports areallowed.

Only logic values of 1, 0, and x are allowed on inputand output. The z value cannot be specified,although on input, it is treated as an x.

Creating UDP (Combinational Logic)

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Creating UDP (Combinational Logic)Example

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Creating UDP (Sequential Logic)Level Sensitive

Sequential UDP are defined similar to the combinational

logic with some differences:

1. The output shall also be declared as type reg toindicate there is an internal state. The output value isalways the same as the value of internal state.

2. There is an additional field added in each table entry

to indicate the current state. This field is separatedby colons from the inputs and the output.

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Creating UDP (Sequential Logic)Level Sensitive

Note: ? = 0,1 or x and - = no change of value

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Creating UDP (Sequential Logic)Edge Sensitive

Similar to creating Level Sensitive Sequential Logic

UDP, the edge sensitive UDP differs in the manner of:

1. Changes at the output triggers by specific transitionsof the inputs such as clock Positive Going Transition

(PGT) or Negative Going Transition (NGT).

2. All unspecified transitions will default to an output

value x (unknown). All transitions must be explicitlyspecified to avoid output default to x.

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Creating UDP (Sequential Logic)Edge Sensitive - Example

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Creating UDP (Sequential Logic)Edge Sensitive with Initial - Example