Lecture 4: Implementing Logic in CMOSusers.ece.utexas.edu/.../vlsi1/main/lectures/lecture_4.pdf ·...

VLSI-1 Class Notes

Lecture 4:Implementing Logic in CMOS

Mark McDermottElectrical and Computer Engineering

The University of Texas at Austin

9/11/18

VLSI-1 Class Notes

Review of DeMorgan’s Theorem

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Recall that:(AB)’ = A’+B’ and AB = (A’ + B’)’(A+B) = A’B and A+B = (A’B’)’

AB

(AB)’ A’B’ A’+B’

AB AB A’

B’(A’+B’)’

AB

(A+B)’ A’B’

A’B’

AB A+B A’

B’(AB)’

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Bubble Pushing

§ Start with network of AND / OR gates§ Convert to NAND / NOR + inverters§ Push bubbles around to simplify logic

Y Y

Y

D

Y

(a) (b)

(c) (d)

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Static CMOS Circuits

§ N and P channel networks implement logic functions– Each network connected between Output and VDD or VSS

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Series network: "AND" function

Parallel network: "OR" function

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Duality in CMOS Circuits

§ N and P networks must implement complementary functions§ Duality is sufficient for correct operation

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What are the values of A, B and C which will produce a connection between P and Q

AB

C

Q

P

A + B * C

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Constructing Complex Gates

§ Example: F = (A * B) + (C * D)

– Take un-inverted function F = (AB + CD) and derive N-network

– Identify AND, OR components; F is OR of AB,CD

– Make connections of transistors

• AND , Series connection, OR , Parallel

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A

B

C

D

F

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Construction of Complex Gates, Cont d

§ Construct P-network by taking complement of N-expression (AB +CD), which gives the expression, (A + B) * (C + D)

§ Combine P and N circuits

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C D

A B

A B

C

F

V

D

DD

A

B

C

D

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Layout of Complex Gate

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A B

C

F

V

D

DD

A

B

C

D

AND-OR-INVERT (AOI) gate

C D B A

F

Vdd

GND

Layout

Metal 1

Metal 2

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Example of Compound Gate

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F = (A + B + C) * D

V

C

B

A

D

D

A B C

DD

F

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Example of More Complex Gate

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A

B

C

E

D HG

F

BA

C D

E F

H

G

+V

OUT

OUT = (A+B)*(C+D)*(E+F+GH)

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Exclusive-NOR Gate in CMOS

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OUTPUTIN2IN1

VDD

P

P

IN1(A)

IN2(B)

N N OUTPUT = AB + AB

NB

OUT

P

PN

B

A

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Pseudo nMOS Logic

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VDD

B D

A

Z

C

E

Generally a weak device

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Duality is not Necessary

§ Functions realized by N and P networks must be complementary, and one of them must conduct for every input combination

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da b c

da b c

da b c

VDD

F

CMOS Circuit"Hybrid"

a

b

c

b

a

a

c d

c dGND

F = ab + a b + a’c’ + cd + c d

The N and P networks are NOTduals, but the switching functionsthey implement are complementary

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Example of Dual Rail Complex CMOS Gate

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F =

G =

VDD

G F

x x

y y

x x

zz

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Signal Strength

§ Strength of signal– How close it approximates ideal voltage source

§ VDD and GND rails are strongest 1 and 0

§ nMOS pass strong 0– But degraded or weak 1

§ pMOS pass strong 1– But degraded or weak 0

§ Thus nMOS are best for pull-down network

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Pass Transistors

§ Transistors can be used as switches

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g

s d

g = 0s d

g = 1s d

0 strong 0Input Output

1 degraded 1

g

s d

g = 0s d

g = 1s d

0 degraded 0Input Output

strong 1

g = 1

g = 1

g = 0

g = 0

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Transmission Gates

§ Pass transistors produce degraded outputs§ Transmission gates pass both 0 and 1 well

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g = 0, gb = 1a b

g = 1, gb = 0a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a bg

gba b

g

gb

a bg

gb

g = 1, gb = 0

g = 1, gb = 0

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Pass Transistor Logic

§ What is the difference between the two circuits?

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C, CF(A,B,C)

AA B B A B

F(A,B)

A B

P

P

P

P

1

2

3

4

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Pass Transistor Logic -- Better Layout

§ Group similar transistors, so they can be in the same well

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A A B B

F(A,B)P

P

P

P

4

3

2

1

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Pass Transistor Logic Pull-Up Version

§ How do voltage levels at the output of this gate differ from that of the pass-transistor multiplexer in the previous foil?

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AA B B

F(A,B)

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Tristates

§ Tristate buffer produces Z when not enabled

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EN A Y0 00 11 01 1

A Y

EN

A Y

EN

EN

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Non-restoring Tri-state®

§ Transmission gate acts as Tri-state® buffer– Only two transistors– But nonrestoring

• Noise on A is passed on to Y

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A Y

EN

EN

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Tri-state® Inverter

§ Tri-state® inverter produces restored output– Violates conduction complement rule– Because we want a Z output

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A

YEN

A

Y

EN = 0Y = 'Z'

Y

EN = 1Y = A

A

EN

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Multiplexers (mux)

§ 2:1 multiplexer chooses between two inputs

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S D1 D0 Y0 X 00 X 11 0 X1 1 X

0

1

S

D0

D1Y

0101

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Gate-Level Mux Design

§ How many transistors are needed?

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1 0 (too many transistors)Y SD SD= +

44

D1

D0S Y

4

2

22 Y

2

D1

D0S

20

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Transmission Gate Mux

§ Nonrestoring mux uses two transmission gates– Only 4 transistors if both of the select signals are available– If not then it takes 6 transistors…

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S

S

D0

D1YS

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Inverting Mux

§ Inverting multiplexer– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing

§ Non-inverting multiplexer requires adding an inverter

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SD0 D1

Y

S

D0

D1Y

0

1S

Y

D0D1

S

S

S

S

S

S

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4:1 Multiplexer

§ 4:1 mux chooses one of 4 inputs using two selects– Two levels of 2:1 muxes– Or four tristates

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S0

D0

D1

0

1

0

1

0

1Y

S1

D2

D3

D0

D1

D2

D3

Y

S1S0 S1S0 S1S0 S1S0

Requires pre-decoded signals

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D Latch**

§ When CLK = 1, latch is transparent– D flows through to Q like a buffer

§ When CLK = 0, the latch is opaque– Q holds its old value independent of D

** transparent latch or level-sensitive latch

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CLK

D Q

Latch D

CLK

Q

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D Latch Design

§ Multiplexer chooses D or old Q

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1

0

D

CLKQ

CLK

CLKCLK

CLK

DQ QQ

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D Flip-flop Design

§ Built from master and slave D latches

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QMCLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latch

Latch

D QQM

CLK

CLK

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Questions?

9/11/18

Lecture 4: Implementing Logic in CMOSusers.ece.utexas.edu/.../vlsi1/main/lectures/lecture_4.pdf ·...

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