Lecture 4: CMOS Transistor Theory - Pittkmram/1192-2192/lectures/... · 2017. 8. 31. · q nMOS I-V...

Introduction to CMOS VLSI

Design

Lecture 4: CMOS Transistor Theory

David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan

University of Pittsburgh

CMOS VLSI Design 3: CMOS Transistor Theory Slide 2

Outline q  Introduction q  MOS Capacitor q  nMOS I-V Characteristics q  pMOS I-V Characteristics q  Gate and Diffusion Capacitance q  Pass Transistors q  RC Delay Models


Introduction q  So far, we have treated transistors as ideal switches q  An ON transistor passes a finite amount of current

–  Depends on terminal voltages –  Derive current-voltage (I-V) relationships

q  Transistor gate, source, drain all have capacitance –  I = C (ΔV/Δt) -> Δt = (C/I) ΔV –  Capacitance and current determine speed

q  Also explore what a “degraded level” really means

© Digital Integrated Circuits2nd Devices

MOS Transistors - Types and Symbols

D

S G

D

S G

G S

D D

S G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS with Bulk Contact


The MOS Transistor

Polysilicon Aluminum


Controlling current flow in an nFET.

Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.

© Digital Integrated Circuits2nd Devices Introduction to Circuits, Fourth Edition by Peter Uyemura, Copyright © 2004 John Wiley & Sons. All rights reserved.

Controlling current flow in a pFET.


What is a Transistor?

VGS ≥ VTR o n

S D

A Switch!

|V GS |

A MOS Transistor

I-V Curves

Resistor I = V/R

Diode I = Is*exp(k*V-Vt)

Current (I) vs. Voltage (V) I = f(V)

0 0.5 1 1.5 2 2.5 0

1

2

3

4

5

6 x 10 -4

V DS

I D (A)

MOS I = f(Vgs, Vds)


Terminal Voltages q  Mode of operation depends on Vg, Vd, Vs

–  Vgs = Vg – Vs

–  Vgd = Vg – Vd

–  Vds = Vd – Vs = Vgs - Vgd

q  Source and drain are symmetric diffusion terminals –  By convention, source is terminal at lower voltage –  Hence Vds ≥ 0

q  nMOS body is grounded. First assume source is 0 too. q  Three regions of operation

–  Cutoff –  Linear –  Saturation

Vg

Vs Vd

VgdVgs

Vds+-

+

-

+

-


MOS Capacitor q  Gate and body form MOS capacitor q  Operating modes

–  Accumulation –  Depletion –  Inversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < Vt

depletion region

(c)

+-

Vg > Vt

depletion regioninversion region

In general, MOS gate capacitance is not constant

© Digital Integrated Circuits2nd Devices Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOS Transistors – Operating regions


nMOS Cutoff q  No channel q  Ids = 0

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d

d

s

g


nMOS Linear q  Channel forms q  Current flows from d to s

–  e- from s to d q  Ids increases with Vds

q  Similar to linear resistor

+-

Vgs > Vt

n+ n+

+-

Vgd = Vgs

+-

Vgs > Vt

n+ n+

+-

Vgs > Vgd > Vt

Vds = 0

0 < Vds < Vgs-Vt

p-type body

p-type body

b

g

s d

b

g

s d Ids

d

s

g


n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions

Linear Region Vgs>Vt & Vgd>Vt

Positive Charge on Gate: Channel exists, Current Flows

since Vds > 0 Ids = k’(W/L)((Vgs-Vt)Vds-Vds

2/2)

R Vgd

Vgs

Ids

Vds

I=V/R R= 1/(k’(W/L)(Vgs-Vt))

Ids


nMOS Saturation q  Channel pinches off q  Ids independent of Vds

q  We say current saturates q  Similar to current source

+-

Vgs > Vt

n+ n+

+-

Vgd < Vt

Vds > Vgs-Vt

p-type bodyb

g

s d Ids

d

s

g


n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Saturation: Vgs>Vt & Vgd<Vt

Positive Charge on Gate: Channel exists, Current Flows

since Vds > 0 But: channel is “pinched off”

Ids = (k’/2)(W/L)(Vgs-Vt)2

Vgd

Vgs

Ids

Ids


I-V Characteristics q  In Linear region, Ids depends on

–  How much charge is in the channel? –  How fast is the charge moving?


MOS Transistors – Regions Transitions


Channel Charge q  MOS structure looks like parallel plate capacitor

while operating in inversion –  Gate – oxide – channel

q  Qchannel =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate




q  Qchannel = CV q  C =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox


polysilicongate




q  Qchannel = CV q  C = Cg = εoxWL/tox = CoxWL q  V =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox


polysilicongate

Cox = εox / tox Cox = 8.6*fF/um2




q  Qchannel = CV q  C = Cg = εoxWL/tox = CoxWL q  V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox


polysilicongate

Cox = εox / tox


Carrier velocity q  Charge is carried by e- q  Carrier velocity v proportional to lateral E-field

between source and drain q  v =



between source and drain q  v = µE µ called mobility q  E =



between source and drain q  v = µE µ called mobility q  E = Vds/L q  Time for carrier to cross channel:

–  t =



between source and drain q  v = µE µ called mobility q  E = Vds/L q  Time for carrier to cross channel:

–  t = L / v


nMOS Linear I-V q  Now we know

–  How much charge Qchannel is in the channel –  How much time t each carrier takes to cross

dsI =




channelds

QIt

=

=




channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QItW VC V V VL

VV V V

µ

β

=

⎛ ⎞= − −⎜ ⎟⎝ ⎠

⎛ ⎞= − −⎜ ⎟⎝ ⎠

ox = WCL

β µ


Computed Curves

Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

Linear Resistor


nMOS Saturation I-V q  If Vgd < Vt, channel pinches off near drain

–  When Vds > Vdsat = Vgs – Vt

q  Now drain voltage no longer increases current

dsI =





2dsat

ds gs t dsatVI V V Vβ ⎛ ⎞= − −⎜ ⎟

⎝ ⎠





( )22

2

dsatds gs t dsat

gs t

VI V V V

V V

β

β

⎛ ⎞= − −⎜ ⎟⎝ ⎠

= −


Computed Curves

Vgs = 5v

Vgs = 4.5v

Vgs = 4.0v

Linear Resistor


nMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨

⎝ ⎠⎪⎪

− >⎪⎩

q  Shockley 1st order transistor models


Example q  We will be using a 0.180 µm process for your project

–  From TSMC Semiconductor –  tox = 40 Å –  µ = 180 cm2/V*s –  Vt = 0.4 V

q  Plot Ids vs. Vds

–  Vgs = 0, 0.3,…, 1.8 –  Use W/L = 4/2 λ

( )14

28

3.9 8.85 10350 120 /100 10ox

W W WC A VL L L

β µ µ−

−

⎛ ⎞• ⋅ ⎛ ⎞= = =⎜ ⎟⎜ ⎟⋅ ⎝ ⎠⎝ ⎠180

40 155


pMOS I-V q  All dopings and voltages are

inverted for pMOS q  Mobility µp is determined by

holes –  Typically 2-3x lower than

that of electrons µn

q  Thus pMOS must be wider to provide same current –  Often, assume µn / µp = 2


Current-Voltage Relations Long-Channel Device

Cut-off (VGS – VT < 0) “no current” (not really)


ID versus VDS short channel device

-4

V DS (V) 0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5 x 10

I D (A

)

VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V

0 0.5 1 1.5 2 2.5 0

1

2

3

4

5

6 x 10 -4

V DS (V)

I D (A

)

VGS= 2.5 V

VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V

Resistive Saturation VDS = VGS - VT

Long Channel Short Channel


Rabaey’s unified model for manual analysis

S D

G

B


Transistor Model for Manual Analysis


Simple Model versus SPICE

0 0.5 1 1.5 2 2.5 0

0.5

1

1.5

2

2.5 x 10 -4

V DS (V)

I D (A

)

Velocity Saturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT


Even Simpler: The Transistor as a Switch

VGS ≥ VTR o n

S DID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid


The Transistor as a Switch

This week’s Lab – find Req for our TSMC 180nm process


Saturation Effects

Which is the resistor?

Discharge of 1pf capacitor, with Vgs of 3,4,5 volts. Also, 12k resistor.

d

s

g


More on Capacitance q  Any two conductors separated by an insulator have

capacitance q  Gate to channel capacitor is very important

–  Creates channel charge necessary for operation q  Source and drain have capacitance to body

–  Across reverse-biased diodes –  Called diffusion capacitance because it is

associated with source/drain diffusion


Gate Capacitance q  Approximate channel as connected to source q  Cgs = εoxWL/tox = CoxWL = CpermicronW q  Cpermicron is typically about 2 fF/µm

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9ε0)

polysilicongate


The Gate Capacitance

t ox

n + n +

Cross section

L

Gate oxide

x d x d

L d

Polysilicon gate

Top view

Gate-bulk overlap

Source

n +

Drain

n + W


Dynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB


Physical visualization of FET capacitances



MOS Capacitances Behavior !


Gate Capacitance – Behavior

S D

G

CGCS D

G

CGCS D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off


Measuring the Gate Cap

2 1.5 2 1 2 0.5 0

3

4

5

6

7

8

9

103 102 16

2

VGS (V)

VGS

GateCapacita

nce(F)

0.5 1 1.5 22 2

I


Diffusion Capacitance q  Csb, Cdb

q  Undesirable, called parasitic capacitance q  Capacitance depends on area and perimeter

–  Use small diffusion nodes –  Comparable to Cg

for contacted diff – ½ Cg for uncontacted –  Varies with process


Diffusion Capacitance

Bottom

Side wall

Side wall Channel

Source N D

Channel-stop implant N A 1

Substrate N A

W

x j

L S


Calculation of the FET junction capacitance



Capacitances in 0.25 µm CMOS process

Values for a Typical Device:


Parasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff


Final construction of the nFET RC model


CG


Latchup

(a) Origin of latchup (b) Equivalent circuit

VDD

Rpsubs

Rnwell p-source

n-source

n+ n+p+ p+ p+ n+

p-substrateRpsubs

Rnwell

VDD

n-well


Summary of MOSFET Operating Regions

q Strong Inversion VGS > VT §  Linear (Resistive) VDS < VDSAT §  Saturated (Constant Current) VDS ≥ VDSAT

q Weak Inversion (Sub-Threshold) VGS ≤ VT §  Exponential in VGS with linear VDS dependence


SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular


Main MOS SPICE Parameters


SPICE Parameters for Parasitics


SPICE Transistors Parameters


Circuit Simulation Model of CMOS Inverter

© Digital Integrated Circuits2nd Devices 3: CMOS Transistor Theory Slide 68

Pass Transistors

q We have assumed source is grounded q What if source > 0?

§  e.g. pass transistor passing VDD

VDDVDD


Pass Transistors

q  We have assumed source is grounded q  What if source > 0?

§  e.g. pass transistor passing VDD

q  Vg = VDD §  If Vs > VDD-Vt, Vgs < Vt

§  Hence transistor would turn itself off

q  nMOS pass transistors pull no higher than VDD-Vtn §  Called a degraded “1” §  Approach degraded value slowly (low Ids)

q  pMOS pass transistors pull no lower than Vtp

VDDVDD


Pass Transistor Ckts

VDDVDD

VSS

VDD

VDD

VDD VDD VDD

VDD


Pass Transistor Ckts

VDDVDD Vs = VDD-Vtn

VSS

Vs = |Vtp|

VDD

VDD-Vtn VDD-VtnVDD-Vtn

VDD

VDD VDD VDD

VDD

VDD-Vtn

VDD-2Vtn


Effective Resistance

q  Shockley models have limited value §  Not accurate enough for modern transistors §  Too complicated for much hand analysis

q  Simplification: treat transistor as resistor §  Replace Ids(Vds, Vgs) with effective resistance R

–  Ids = Vds/R §  R averaged across switching of digital gate

q  Too inaccurate to predict current at any given time §  But good enough to predict RC delay


RC Delay Model

q  Use equivalent circuits for MOS transistors §  Ideal switch + capacitance and ON resistance §  Unit nMOS has resistance R, capacitance C §  Unit pMOS has resistance 2R, capacitance C

q  Capacitance proportional to width q  Resistance inversely proportional to width

kgs

dg

s

d

kCkC

kCR/k

kgs

dg

s

d

kC

kC

kC

2R/k


RC Values

q  Capacitance §  C = Cg = Cs = Cd = 2 fF/µm of gate width §  Values similar across many processes

q  Resistance §  R ≈ 6 KΩ*µm in 0.6um process §  Improves with shorter channel lengths

q  Unit transistors §  May refer to minimum contacted device (4/2 λ) §  Or maybe 1 µm wide device §  Doesn’t matter as long as you are consistent


Inverter Delay Estimate

q Estimate the delay of a fanout-of-1 inverter

2

1A

Y 2

1




C

CR

2C

2C

R

2

1A

Y

C

2C

Y2

1




C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1




C

CR

2C

2C

R

2

1A

Y

C

2C

C

2C

C

2C

RY

2

1

d = 6RC

Lecture 4: CMOS Transistor Theory - Pittkmram/1192-2192/lectures/... · 2017. 8. 31. · q nMOS I-V...

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Transcript of Lecture 4: CMOS Transistor Theory - Pittkmram/1192-2192/lectures/... · 2017. 8. 31. · q nMOS I-V...