Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24

Lecture 24:Examples of Multistage Amps

Prof. Niknejad

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Review: Frequency Resp of Multistage Amplifiers

• We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/Bode pltos).

• In most cases, the systematic approach is too cumbersome.

• We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD andd CG are wideband stages …)

• Open Circuit Time Constants: Analytical technique is capable of estimating only the dominant (lowest) pole …for a restricted class of amplifiers.

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

The Special Case

The transfer function can have no zeroes and must have a dominant pole 1 << 2, 3, …, n

...)()(1)(

33

22

1

bjbjbj

HjH o

n

o

jjj

HjH

/1.../1/1)(

21

Factor denominator:

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Approximating the Transfer Function

Multiply out denominator:

n

o

jjj

HjH

/1.../1/1)(

21

n

o

j

H

1

...11

121

Since 1 << 2, 3, …, n

1211

11...

11

n

b

n

o

jjj

HjH

/1.../1/1)(

21

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

How to Find b1?

See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 140) for derivation

Result: b1 is the sum of open-circuit time constants i which can be found by considering each capacitor Ci in the amplifier separately and

finding its Thévenin resistance RTi

i = RTi Ci

n

i iTi

n

i iTiCR

CRb1

111

1

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Finding the Thévenin Resistance

1. Open-circuit all capacitors (i.e.; remove them)

2. For capacitor Ci, find the resistance RTi across itsterminals with all independent sources removed(voltages shorted, currents opened) … might needto apply a test voltage and find the current in somecases.

Insight for design: the bandwidth of the amplifier willbe limited by the capacitor that contributes the largesti = RTi Ci not necessarily the largest Ci

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Complete Amplifier Schematic

Goals: gm1 = 1 mS, Rout =10 M

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Device Sizes

M1: select (W/L)1 = 200/2 to meet specified gm1 = 1 mS find VBIAS = 1.2 V

Cascode current supply devices: select VSG = 1.5 V(W/L)4= (W/L)4B= (W/L)3= (W/L)3B = 64/2M2: select (W/L)2 = 50/2 to meet specified Rout =10 M

find VGS2 = 1.4 VMatch M2 with diode-connected device M2B.

Assuming perfect matching and zero input voltage,what is VOUT?

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Output (Voltage) Swing

Maximum VOUT

Minimum VOUT

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Two-Port Model

Find output resistance Rout

n = (1/20) V-1, n = (1/50) V-1 at L = 2 m ron = (100 A / 20 V-1)-1 = 200 k, rop = 500 k

122333222 1||11|| omoSmoSmoocout rgrRgrRgrrR

SVV

A

VV

Ig

TnGS

Dm

50014.1

)100(22

2

22

SVV

A

VV

Ig

TpSG

Dm

40015.1

)100(2)(2

3

33

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Two-Stage Amplifier Topology

Direct DC connection: use NMOS then PMOS

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Current Supply Design

Assume that the reference is a “sink” set by a resistor

Must mirror the reference current and generate a sink for iSUP 2

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Use Basic Current Supplies

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Complete Amplifier Topology

What’s missing? The device dimensions and the biasvoltage and reference resistor

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Multi-Stage Voltage Amplifier

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Cutting Through the Complexity

Two Approaches:

1. Eliminate “background” transistors to reduce clutter

2. Identify the “signal path” between the input and output

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

First Approach: Find I & V Sources

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

What’s Left?

Voltage at base ofQ2 is set by totempole

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Second Approach: Find Signal Path

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Identifying the Stages

First stage (or two stages): CS/CB cascodeSecond stage (or two stages): CD/CC voltage buffer

Why does this make sense for a voltage amplifier?

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Find Key Two-Port Parameters

2222/, ||1(|| SmoocCBCSout RrgrrR

666 1 Smoupoc RgrRr

Output resistance of cascode:

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Two-Port Parameters (Cont.)

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Output Resistance and Voltage Gain

Source resistance of the CC stage is the output resistanceof the CD stage (small)

434

,

4,

1111

mommo

CCS

mCCoutout ggg

R

gRR

Open-circuit voltage gain Av (last two stages have nearly unity gain):

76621 1|| omooomv rgrrgA

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

DC Bias

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

DC Bias (Cont.)

Simplifying assumption: SGpGSn VVV 5.1

Cascode current supply and totem pole:

diode connected devices set both source-gate and source-drain voltages

select input bias voltage such that ID1 = ID9

devices M1, Q2, M6, and M7 must have same |VDS| orVCE as M9, Q2B, M6B, and M7B (2nd order effect) sometimes called “replica biasing”

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Output Swing: VOUT,MIN

Minimum output voltage: M10, M3 , and Q2 are “suspects”

M10 goes into triode when VOUT = 0.5 V

M3 goes into triode when VSD3 = 0.5 V VOUT = 0.5 V – 0.7 V = -0.2 V

Q2 goes into saturation when VCE2 = 0.1 Vor VBC2 = 0.6 VVOUT = VB2 – VBC2 + VSG3 – VBE4

= 2 V – 0.6 V + 1.5 V – 0.7 V VOUT = 2.2 V

Department of EECS University of California, Berkeley

EECS 105 Fall 2003, Lecture 24 Prof. A. Niknejad

Output Swing: VOUT,MAX

Maximum output voltage: Q4, M5, and M6 are “suspects”

Q4 goes into saturation when VCE4 = 0.1 V VOUT = 4. 9 V

M5 goes triode when VSD5 = 0.5 V VOUT = 3.8 V

M6 goes triode when VSD6 = 0.5 V VOUT = VS6 – 0.5 V + VSG3 – VBE4

= 3.5 – 0.5 + 1.5 – 0.7 V = 3.8 V