Lecture 2 - University of Colorado Boulderecee.colorado.edu/~ecen4517/materials/Lecture2.pdf ·...
Transcript of Lecture 2 - University of Colorado Boulderecee.colorado.edu/~ecen4517/materials/Lecture2.pdf ·...
ECEN 4517 1
Lecture 2ECEN 4517/5517
• Upcoming assignments due:• Exp. 1 final report due in Canvas dropbox by 5:00 pm Friday Jan.
31• Exp. 3 part 1 prelab assignment due in Canvas dropbox by
Tuesday Jan. 4 at noon
• This week: Exp. 2— Introduction to MSP 430
• Lab kits are available in ECEE Electronics Store, ECEE 1B10• You will need this kit to perform Exp. 2.• You will also need an oscilloscope probe and possibly other small
parts (capacitors) from the undergraduate electronics lab parts kit.
ECEN 4517 2
Last week’s Exp. 1
The solar resource: direct radiation (green), global radiation (red), indirect radiation (blue).
Exp. 1 final reports are due in Canvas dropbox by 5:00 pm on Friday Jan 31
• One report per group, with names of a group members on page 1
• See rubric on Exp 1 web page for how Exp. 1 report will be graded
• Dropbox will close at 5:00 pm sharp
Wed
Tues
Thurs
ECEN 4517 3
Lab reports
• One report per group. Include names of every group member on first page of report.
• Report all data from every step of procedure and calculations. Adequately document each step.
• Discuss every step of procedure and calculations– Interpret the data– It is your job to convince the grader that you understand
what is going on with every step– Regurgitating the data, with no discussion or interpretation,
will not yield very many points– Concise is good
• See Exp. 1 rubric
ECEN 4517 4
Upcoming weeks:Design and build MPPT system
Exp. 2: introduction to MSP430 microcontroller
Exp. 3: DC-DC converter
ECEN 4517 5
Experiment 2Introduction to MSP 430F5172 Microcontroller
UnifiedClock
System
32KB16KB8KB
Flash
2KB2KB1KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P18 I/Os
2x 5V 20mAInterrupt
and WakeupPullup/down
Resistors
CPUXV2and
WorkingRegisters
EEM(S: 3+1)
XIN XOUT
JTAG/SBW
Interface
3 DMA
Channel
PowerManagement
LDOSVM/SVSBrownout
SYS
Watchdog
PortMapping
Controller
MPY32
TA0
Timer_A3 CC
Registers
USCI
A0: UART,IrDA, SPI
B0: SPI, I2C
DVCCDVSS AVSS
P1.x8RST/NMI
COMP_B
16 Channels
High,Medium, and
UltralowPowerModes
REF
VoltageReference
DVSS
I/O Ports
P28 I/Os
8x 5V 20mAInterrupt
and WakeupPullup/down
Resistors
P2.x8
I/O Ports
P38 I/Os
2x 5V 20mA
Pullup/downResistors
P3.x8
I/O Ports
PJ7 I/Os
Pullup/downResistors
PJ.x7
CRC16
TD1
Timer_D256 MHz
3 CCRegisters
With BufferEventControl
!
TD0
Timer_D256 MHz
3 CCRegisters
With BufferEventControl
!
DVIOAVCC
32KB16KB8KB
Flash
2KB2KB1KB
RAM
MCLK
ACLK
SMCLK
I/O Ports
P18 I/Os
2x 5V 20mAInterrupt
and WakeupPullup/down
Resistors
CPUXV2and
WorkingRegisters
EEM(S: 3+1)
XIN XOUT
JTAG/SBW
Interface
3 DMA
Channel
PowerManagement
LDOSVM/SVSBrownout
SYS
Watchdog
PortMapping
Controller
MPY32
TA0
Timer_A3 CC
Registers
USCI
A0: UART,IrDA, SPI
B0: SPI, I2C
ADC10_A
200 KSPS
9 Channels
10 Bit
DVCCDVSS AVSS
P1.x8RST/NMI
COMP_B
16 Channels
High,Medium, and
UltralowPowerModes
REF
VoltageReference
DVSS
I/O Ports
P28 I/Os
8x 5V 20mAInterrupt
and WakeupPullup/down
Resistors
P2.x8
I/O Ports
P38 I/Os
2x 5V 20mA
Pullup/downResistors
P3.x8
I/O Ports
PJ7 I/Os
Pullup/downResistors
PJ.x7
CRC16
TD1
Timer_D256 MHz
3 CCRegisters
With BufferEventControl
!
TD0
Timer_D256 MHz
3 CCRegisters
With BufferEventControl
!
DVIOAVCC
UnifiedClock
System
MSP430F51x1MSP430F51x2
www.ti.com SLAS619G –AUGUST 2010–REVISED AUGUST 2012
Functional Block Diagram, MSP430F51x2
Functional Block Diagram, MSP430F51x1
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Programmable multi-use I/O ports (31)
32-bit multiplier
Timer D (2)Timer A (1)
10-bit A/D
Analog comparator
Voltage reference
Clocks: ACLK, SMCLK, MCLK
Up to25 [email protected]
CPU:16 bit
ECEN 4517 6
MSP430F5172: Resources
MSP430F5172 User’s Guide• The primary resource for operation and programming of on-chip
peripherals (PWM, ADC, etc.)• Linked to Exp. 2 web page, 1147 page pdf
MSP430F5172 Data Sheet• Describes pinouts, specifications• Linked to Exp. 2 web page, 103 page pdf
Code Composer Studio 5.3• Development system for MSP430; program in C• On lab computers: free 32 kB limited version
Library of Examples• Accessible within Code Composer Studio, also linked to web page• Many programming examples for each peripheral• Use directory of examples for 430F5172 chip• Also: Erickson’s sample code main.c linked to Exp. 2 web page
ECEN 4517 7
P2.5 TD0.1/PM_TEC0FLT0/PM_P1.6/ TD0.0PM_
P2.0/ TD0.2PM_
P1.7/ TD0.1PM_ P2.4/ TEC0CLR / TD0.0PM_ /PM_TEC0FLT2 PM_
P2.2/ TD1.1PM_
P2.6/ TD0.2PM_TEC0FLT1/PM_
P2.1/P TD1.0M_
P2.3/ TD1.2PM_
DA PACKAGE(TOP VIEW)
1
9
8
7
6
5
4
3
2
10
11
19
18
17
16
14
12
13
15
38
30
31
32
33
34
35
36
37
29
28
20
21
22
23
25
27
26
24
P1.0/PM_ /PM_UCB0STE/A0*/CB0UCA0CLK
P1.2/PM_UCA0RXD/PM_UCA0SOMI/A2*/CB2
P1.1/PM_UCA0TXD/PM_UCA0SIMO/A1*/CB1
P1.5/PM_UCB0SOMI/PM_UCB0SCL/A5*/CB5
P1.4/PM_UCB0SIMO/PM_UCB0SDA/A4*/CB4
P1.3/PM_UCB0CLK/PM_UCA0STE/A3*/CB3
PJ.0/SMCLK/TDO/CB6
PJ.1/MCLK/TDI/TCLK/CB7
PJ.2/ADC10CLK/TMS/CB8
PJ.3/ACLK/TCK/CB9
AVCC
TEST/SBWTCKAVSS
PJ.4/XOUT
PJ.5/XIN RST/NMI/SBWTDIO
P3.5/ TA0.2/A8*/VEREF+*/CB12PM_
P3.6/ TA0.1/A7*/VEREF /CB11PM_ -*-
VCORE
DVSS
DVCC
P2.7/ TEC1CLR/ TD1.0PM_ PM_TEC1FLT1/PM_
P3.0/ TEC1FLT2/ TD1.1PM_ PM_
P3.1/ TEC1FLT0/ TD1.2PM_ PM_
PJ.6/TD1CLK/TD0.1/CB15
P3.2/ TD0.0/ SMCLK/CB14PM_ PM_
P3.3/ TA0CLK/ CBOUT/CB13PM_ PM_
DVIO
DVSS
* Only MSP430F51x2
MSP430F51x1MSP430F51x2
www.ti.com SLAS619G –AUGUST 2010–REVISED AUGUST 2012
Pin Designation, MSP430F51x2IDA and MSP430F51x1IDA
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Microcontroller Pinouts
Timer DPWM outputs
[
to LED (P1.0 output)Px.y is digital I/O
ADC inputs A0 to A5, A7, A8
PM_TD0.xPM_TD1.xSee also pins 20, 23-28, 33
[JTAGprogrammer
ECEN 4517 8
Microcontroller default settings
Upon power-on reset (POR), the MSP430F5172 comes up with the following conditions:• Watchdog timer is enabled• All pins are set to read state• Processor internal clock and core voltage are set to minimum
values. Default clock frequency = 1.045 MHz
• Processor supply voltage is 3.3 V• Internal processor core operates at lower voltage; a programmable
internal voltage regulator reduces the 3.3 V to this lower voltage• Faster clock speeds require higher core voltages• Digital I/O pins can operate at 5 V if 5 V is supplied to DVIO pin.
Otherwise, these pins operate with 3.3 V logic levels
ECEN 4517 9
Development boardin your kit
JTAG(to computer)
Externalpower Jumper:
Select power source—JTAG or external
Header:Processorpins 20-38
Header:Processorpins 1-19
Jumper:Select digital I/O power—Internal 3.3 V or external 5 V
Jumper:Connect or disconnect LED from P1.0
Reset button
ECEN 4517 10
Peripherals are controlled by registers in addressable memory
Example: Port P1, comprised of eight pins labeled P1.0 – P1.7. Digital input/output
For further documentation, see MSP430x5xx/6xx Family User Guide, Ch 12, pp. 406ffThere are additional P1 registers related to interrupts.TI provides a header file that sets up all registers with C code variable names assigned to the correct addresses, so you don’t have to worry about it. Just add the following statement to the beginning of your C code:
#include <msp430f5172.h>This file also defines constants that are useful for setting peripheral functions.
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com Digital I/O Registers
12.4 Digital I/O RegistersThe digital I/O registers are listed in Table 12-2. The base addresses can be found in the device-specificdata sheet. Each port grouping begins at its base address. The address offsets are given in Table 12-2.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 12-2. Digital I/O RegistersOffset Acronym Register Name Type Access Reset Section0Eh P1IV Port 1 Interrupt Vector Read only Word 0000h Section 12.4.10Eh P1IV_L Read only Byte 00h0Fh P1IV_H Read only Byte 00h1Eh P2IV Port 2 Interrupt Vector Read only Word 0000h Section 12.4.21Eh P2IV_L Read only Byte 00h1Fh P2IV_H Read only Byte 00h00h P1IN or Port 1 Input Read only Byte Section 12.4.9
PAIN_L02h P1OUT or Port 1 Output Read/write Byte undefined Section 12.4.10
PAOUT_L04h P1DIR or Port 1 Direction Read/write Byte 00h Section 12.4.11
PADIR_L06h P1REN or Port 1 Resistor Enable Read/write Byte 00h Section 12.4.12
PAREN_L08h P1DS or Port 1 Drive Strength Read/write Byte 00h Section 12.4.13
PADS_L0Ah P1SEL or Port 1 Port Select Read/write Byte 00h Section 12.4.14
PASEL_L18h P1IES or Port 1 Interrupt Edge Select Read/write Byte undefined Section 12.4.3
PAIES_L1Ah P1IE or Port 1 Interrupt Enable Read/write Byte 00h Section 12.4.4
PAIE_L1Ch P1IFG or Port 1 Interrupt Flag Read/write Byte 00h Section 12.4.5
PAIFG_L01h P2IN or Port 2 Input Read only Byte Section 12.4.9
PAIN_H03h P2OUT or Port 2 Output Read/write Byte undefined Section 12.4.10
PAOUT_H05h P2DIR or Port 2 Direction Read/write Byte 00h Section 12.4.11
PADIR_H07h P2REN or Port 2 Resistor Enable Read/write Byte 00h Section 12.4.12
PAREN_H09h P2DS or Port 2 Drive Strength Read/write Byte 00h Section 12.4.13
PADS_H0Bh P2SEL or Port 2 Port Select Read/write Byte 00h Section 12.4.14
PASEL_H19h P2IES or Port 2 Interrupt Edge Select Read/write Byte undefined Section 12.4.6
PAIES_H1Bh P2IE or Port 2 Interrupt Enable Read/write Byte 00h Section 12.4.7
PAIE_H1Dh P2IFG or Port 2 Interrupt Flag Read/write Byte 00h Section 12.4.8
PAIFG_H00h P3IN or Port 3 Input Read only Byte Section 12.4.9
PBIN_L02h P3OUT or Port 3 Output Read/write Byte undefined Section 12.4.10
PBOUT_L
413SLAU208L–June 2008–Revised January 2013 Digital I/O ModuleSubmit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com Digital I/O Registers
12.4 Digital I/O RegistersThe digital I/O registers are listed in Table 12-2. The base addresses can be found in the device-specificdata sheet. Each port grouping begins at its base address. The address offsets are given in Table 12-2.
NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix"_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H"(ANYREG_H) refers to the upper byte of the register (bits 8 through 15).
Table 12-2. Digital I/O RegistersOffset Acronym Register Name Type Access Reset Section0Eh P1IV Port 1 Interrupt Vector Read only Word 0000h Section 12.4.10Eh P1IV_L Read only Byte 00h0Fh P1IV_H Read only Byte 00h1Eh P2IV Port 2 Interrupt Vector Read only Word 0000h Section 12.4.21Eh P2IV_L Read only Byte 00h1Fh P2IV_H Read only Byte 00h00h P1IN or Port 1 Input Read only Byte Section 12.4.9
PAIN_L02h P1OUT or Port 1 Output Read/write Byte undefined Section 12.4.10
PAOUT_L04h P1DIR or Port 1 Direction Read/write Byte 00h Section 12.4.11
PADIR_L06h P1REN or Port 1 Resistor Enable Read/write Byte 00h Section 12.4.12
PAREN_L08h P1DS or Port 1 Drive Strength Read/write Byte 00h Section 12.4.13
PADS_L0Ah P1SEL or Port 1 Port Select Read/write Byte 00h Section 12.4.14
PASEL_L18h P1IES or Port 1 Interrupt Edge Select Read/write Byte undefined Section 12.4.3
PAIES_L1Ah P1IE or Port 1 Interrupt Enable Read/write Byte 00h Section 12.4.4
PAIE_L1Ch P1IFG or Port 1 Interrupt Flag Read/write Byte 00h Section 12.4.5
PAIFG_L01h P2IN or Port 2 Input Read only Byte Section 12.4.9
PAIN_H03h P2OUT or Port 2 Output Read/write Byte undefined Section 12.4.10
PAOUT_H05h P2DIR or Port 2 Direction Read/write Byte 00h Section 12.4.11
PADIR_H07h P2REN or Port 2 Resistor Enable Read/write Byte 00h Section 12.4.12
PAREN_H09h P2DS or Port 2 Drive Strength Read/write Byte 00h Section 12.4.13
PADS_H0Bh P2SEL or Port 2 Port Select Read/write Byte 00h Section 12.4.14
PASEL_H19h P2IES or Port 2 Interrupt Edge Select Read/write Byte undefined Section 12.4.6
PAIES_H1Bh P2IE or Port 2 Interrupt Enable Read/write Byte 00h Section 12.4.7
PAIE_H1Dh P2IFG or Port 2 Interrupt Flag Read/write Byte 00h Section 12.4.8
PAIFG_H00h P3IN or Port 3 Input Read only Byte Section 12.4.9
PBIN_L02h P3OUT or Port 3 Output Read/write Byte undefined Section 12.4.10
PBOUT_L
413SLAU208L–June 2008–Revised January 2013 Digital I/O ModuleSubmit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Read input value
Write output value
0 = input1 = output
0 = off1 = selected as digital I/O
When input, 1 = pullup/down0 = reduced1 = full drive
ECEN 4517 11
Examples
Configure pin P1.0 to be a digital output, and toggle its value
P1DIR |= 0x01; // OR the contents of register P1DIR with hex 01, // forcing the first bit high// This configures pin P1.0 to be an output
P1OUT ^= 0x01; // EXOR the contents of P1OUT with hex 01,// toggling the first bit// This changes the state of logic output P1.0
Turn off the watchdog timer
WDTCTL = WDTPW + WDTHOLD; // Sets the WDT control register WDTCTL to // disable the watchdog timer function
// WDTPW and WDTHOLD are constants defined// in the header file supplied by TI—see user guide
ECEN 4517 12
C code to toggle pin P2.2
#include <msp430f5172.h> // TI-supplied header file
void main(void){
volatile unsigned int i;WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timerP2DIR |= 0x04; // Configure pin P2.2 to output
directionfor (;;) // infinite loop{P2OUT ^= 0x04; // Toggle P2.2 outputi = 10000;do(i--); // Wait 10000 countswhile (i != 0);}
}
The above code will drive P2.2 (pin 19) with a low-frequency square wave.The development boards have an LED connected to P1.0; if the above code is modified to drive P1.0 then it will blink the LED.
ECEN 4517 13
Setting the core voltageand processor clock frequency
2.01.8
12
0
16
20
25
Syste
m�F
requency�-
�MH
z
Supply�Voltage�-�V
The�numbers�within�the�fields�denote�the�supported�PMMCOREVx�settings.
2.2 2.4 3.6
0,�1,�2,�30,�1,�20,�10
1,�2,�31,�21
2,�3
3
2
MSP430F51x1MSP430F51x2
SLAS619G –AUGUST 2010–REVISED AUGUST 2012 www.ti.com
Figure 1. Frequency vs Supply Voltage
34 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
• Lower core voltage means less power dissipation but processor clock frequency is limited.
• At power-on reset: minimum core voltage (level 0) and low clock frequency (1.045 MHz)
• To operate at faster DCO frequency, we must raise core voltage one level at a time, then raise clock frequency. After each step, wait for circuitry to stabilize.
• The processor contains a digitally controlled oscillator (DCO) whose frequency can be programmed.
• Although the MSP430F5172 is powered with a 3.3 V supply, the processor core operates at a reduced voltage that can be programmed.
ECEN 4517 14
Sample CodeCore voltage = level 3, processor frequency = 25 MHz
// Increase Vcore setting to level 3 to support fsystem= 25 MHz, one level at a timeSetVcoreUp (0x01); // call subroutine SetVcoreUp: level0 to level1SetVcoreUp (0x02); // call subroutine SetVcoreUp: level1 to level2SetVcoreUp (0x03); // call subroutine SetVcoreUp: level2 to level3
// Initialize DCO to 25MHz__bis_SR_register(SCG0); // Disable the FLL control loopUCSCTL0 = 0x0000; // Set lowest possible DCOx, MODxUCSCTL1 = DCORSEL_6; // Select DCO range 4.6MHz-88MHz operationUCSCTL2 = FLLD_1 + 763; // Set DCO Multiplier for 25MHz
// (N + 1) * FLLRef = Fdco: (762 + 1) * 32768 = 25MHz. Also set FLL Div = fDCOCLK/2__bic_SR_register(SCG0); // Enable the FLL control loop__delay_cycles(782000); // wait for DCO to settle// 32 x 32 x 25 MHz / 32,768 Hz = 782000 = MCLK cycles for DCO to settle; see user guide
ECEN 4517 15
Subroutine SetVcoreUpSee sample C code, linked to Exp. 2 web page
void SetVcoreUp (unsigned int level){ // Subroutine to change core voltagePMMCTL0_H = PMMPW_H; // Open PMM registers for write
// Set SVS/SVM high side new levelSVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
// Set SVM low side to new levelSVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;while ((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settledPMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flagsPMMCTL0_L = PMMCOREV0 * level; // Set VCore to new levelif ((PMMIFG & SVMLIFG))
while ((PMMIFG & SVMLVLRIFG) == 0); // Wait till new level reached// Set SVS/SVM low side to new level
SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;PMMCTL0_H = 0x00; // Lock PMM registers for write access}
ECEN 4517 16
Operation of Timer D as a PWM
See MSP430x5xx/6xx Family User Guide, Chapter 19
The MSP430F5172 has two Timer D’sEach Timer D includes:• One timer block with 16 bit counter• Three capture/compare registers
(CCR0 – CCR2)• High resolution mode with TDCLK
frequency = n*(DCO frequency)Use CCR0 to set switching frequency: fs= (TDCLK freq)/(CCR0)Use CCR1 and CCR2 to set duty cycles of outputs: D1 = CCR1/CCR0 etc.Need to configure Timer D, and write values to set fs and duty cycle(s)
CCR0*
CCR1
CountMode
16-bit TimerTDR
Set TDIFG
15 0
MCx
Clear
TDCLR
EQU0
CNTLx
RC
10 12 168
TDCLGRPx
GroupLoad Logic
TDSSELx
00
01
10
11
00
01
10
11
ACLK
SMCLK
TDCLK
Timer Clock
Divider
/1/2/4/8
IDx IDEXx
Divider
/1.../8
High ResolutionGenerator
TDCLKMx
00
01
10
TDCLR1
TDHMx
Divider /1/2/4/8
TDHCLKSRx
TDHCLKTRIMx
2 7
TDHCLKRx
5
TDHDx
TDAUXCLK
TDAUXCLROUT
CCR5
CCR6
Comparator 6
CCI
15 0
OUTMODx
CaptureMode
CMx
Sync
COVlogic
OutputUnit6 D
Set Q
OUT
OUT6 Signal
Reset
POR
EQU6
Timer Clock
Timer Clock
VCC
TDR=0
UP/DOWNEQU0
CLLDxLoad
TDCCR6
CCR5
CCR4
CCR1
GroupLoad Logic
GND
VCC
CCI6A
CCI6B
00
01
10
11
CCISx
00
01
10
11CAP
1
0
SCS
1
0
Set TDCCR6
CCIFG
Compare Latch TDCL6
1
0
CH5EVNT
TD6CMB
EXTCLR
CH0EVNT
CH6EVNT EQU6
Timer Block
CCRx Block
TDHREGEN
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com Timer_D Introduction
Figure 19-1. Timer_D Block Diagram
509SLAU208L–June 2008–Revised January 2013 Timer_DSubmit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECEN 4517 17
Example: Configuring Timer D0 as a PWM with 100 kHz switching frequency
… // insert startup code to set DCO to 25 MHz, etc.P1SEL |= BIT7; // Configure P1.7 (pin 16)P1DIR |= BIT7; // (TD0.1 output)P2SEL |= BIT0; // Configure P2.0 (pin 17)P2DIR |= BIT0; // (TD0.2 output)TD0CTL0 = TDSSEL_2; // TDCLK is based on SMCLK = 25MHzTD0CTL1 |= TDCLKM_1; // Select Hi-res local clock for TD0TD0HCTL0 = TDHM_0 + TDHCALEN + TDHEN; // Hi-res clock is 8 x TDCLK = 200MHz
// Calibration and Hi-res mode enableTD0HINT |= TDHLKIE; // Enable hi-res clock lock to TDCKLTD0CCR0 = 2000; // PWM freq = 200 MHz/2000 = 100 kHzTD0CCTL1 = OUTMOD_7 + CLLD_1; // CCR1 reset/set mode, bufferedTD0CCR1 = 1000; // CCR1 duty cycle = 1000/2000 = 0.5TD0CCTL2 = OUTMOD_7 + CLLD_1; // CCR2 reset/set mode, bufferedTBCCR2 = 500; // CCR2 duty cycle = 500/2000 = 0.25TD0CTL0 |= TDCLR + MC_1; // clear TDR, use up mode, start TD0
The TD0.1 and TD0.2 outputs will now continue to run at 100 kHz with duty cycles of 0.5 and 0.25. Subsequent writes to TD0CCR1 or TD0CCR2 will cause the output duty cycle to change at the next 100 kHz switching period.
ECEN 4517 18
Timer DControl Register TD0CTL0
See MSP430x5xx/6xx Family User Guide, Chapter 19, p. 535C code:TD0CTL0 = TDSSEL_2;
This sets the Timer D clock source to SMCLK (derived from processor clock DCO)
TD0CTL0 is a variable associated with this control register in the header file msp430f5172.hTDSSEL_2 is a constant defined in the standard header file, having 01b as bits 9-8. The header file msp430f5172.hdefines such constants for every control register field.
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com Timer_D Registers
19.3.1 TDxCTL0 RegisterTimer_D x Control Register 0
Figure 19-24. TDxCTL0 Register15 14 13 12 11 10 9 8
Reserved TDCLGRPx CNTLx Reserved TDSSELxr0 rw-(0) rw-(0) rw-(0) rw-(0) r0 rw-(0) rw-(0)
7 6 5 4 3 2 1 0ID MCx Reserved TDCLR TDIE TDIFG
rw-(0) rw-(0) rw-(0) rw-(0) r0 w-(0) rw-(0) rw-(0)
Table 19-9. TDxCTL0 Register Description
Bit Field Type Reset Description15 Reserved R 0h Reserved. Always reads as 0.14-13 TDCLGRPx RW 0h TDCLx group
00b = Each TDCLx latch loads independently.01b = TDxCL1+TDxCL2 (TDxCCR1 CLLDx bits control the update)TDxCL3+TDxCL4 (TDxCCR3 CLLDx bits control the update)TDxCL5+TDxCL6 (TDxCCR5 CLLDx bits control the update)TDxCL0 independent10b = TDxCL1+TDxCL2+TDxCL3 (TDxCCR1 CLLDx bits control the update)TDxCL4+TDxCL5+TDxCL6 (TDxCCR4 CLLDx bits control the update)TDxCL0 independent11b = TDxCL0+TDxCL1+TDxCL2+TDxCL3+TDxCL4+TDxCL5+TDxCL6(TDxCCR1 CLLDx bits control the update)
12-11 CNTLx RW 0h Counter length00b = 16-bit, TDR(max) = 0FFFFh01b = 12-bit, TDR(max) = 0FFFh10b = 10-bit, TDR(max) = 03FFh11b = 8-bit, TDR(max) = 0FFh
10 Reserved R 0h Reserved. Always reads as 0.9-8 TDSSELx RW 0h Timer_D clock source select
00b = TDCLK01b = ACLK10b = SMCLK11b = Inverted TDCLK
7-6 ID RW 0h Input divider. These bits, along with the IDEX bits in TDxCTL1, select the dividerfor the input clock.00b = Divide by 101b = Divide by 210b = Divide by 411b = Divide by 8
5-4 MCx RW 0h Mode control. Setting MCx = 00h when Timer_D is not in use saves power.00b = Stop mode: Timer is halted01b = Up mode: Timer counts up to TDCL010b = Continuous mode: Timer counts up to the value set by CNTLx (counterlength)11b = Up/down mode: Timer counts up to TDCL0 and down to 0000h
3 Reserved R 0h Reserved. Always reads as 0.2 TDCLR W 0h Timer_D clear. Setting this bit resets TDR, the TDCLK divider, and the count
direction. The TDCLR bit always read as zero.
535SLAU208L–June 2008–Revised January 2013 Timer_DSubmit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECEN 4517 19
Timer DControl Register TD0HCTL0
See MSP430x5xx/6xx Family User Guide, Chapter 19, p. 543C code:TD0HCTL0 = TDHM_0 + TDHCALEN + TDHEN;
This sets the TDHEN bit to enable high resolution mode
The enhanced accuracy bit is set
The TDHM bits are set to 0, which causes the hi-res clock to be 8x SMCLK = 8 x 25 MHz = 200 MHz.So each clock count is 5 ns
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com Timer_D Registers
19.3.8 TDxHCTL0 RegisterTimer_D x High-Resolution Control Register 0
Figure 19-31. TDxHCTL0 Register15 14 13 12 11 10 9 8
Reserved TDHFWr0 r0 r0 r0 r0 r0 r0 rw-(0)
7 6 5 4 3 2 1 0TDHDx TDHMx TDHRON TDHEAEN TDHREGEN TDHEN
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
Table 19-16. TDxHCTL0 Register Description
Bit Field Type Reset Description15-9 Reserved R 0h Reserved. Always reads as 0.8 TDHFW RW 0h High-resolution generator fast wakeup enable
0b = High-resolution generator fast wakeup disabled1b = High-resolution generator fast wakeup enable
7-6 TDHDx RW 0h High-resolution clock divider. These bits select the divider for the high resolutionclock.00b = Divide by 101b = Divide by 210b = Divide by 411b = Divide by 8
5-4 TDHMx RW 0h Timer_D high-resolution clock multiplication factor00b = High-resolution clock 8x Timer_D clock01b = High-resolution clock 16x Timer_D clock10b = Reserved11b = Reserved
3 TDHRON RW 0h Timer_D high-resolution generator forced on.0b = High-resolution generator is on if the Timer_D counter MCx bits are 01, 10or 11.1b = High-resolution generator is on in all Timer_D MCx modes. The PMMremains in high-current mode.
2 TDHEAEN RW 0h Timer_D high-resolution clock enhanced accuracy enable bit. Setting this bitreduces the accumulated frequency offset of the high-resolution clock generatorand the reference clock.0b = Normal accuracy1b = Enhanced accuracy enable
1 TDHREGEN RW 0h Timer_D regulation enable. Set this bit to synchronize the high-resolution clock tothe Timer_D input clock defined by TDSSELx.0b = Regulation disabled1b = Regulation enabled
0 TDHEN RW 0h Timer_D high-resolution enable bit. This bit must be set to enable high-resolutionoperation mode. Whenever a high-resolution TDAUXCLK from another Timer_Dinstance is used, this bit must also be set.0b = High-resolution mode disable1b = High-resolution mode enable
543SLAU208L–June 2008–Revised January 2013 Timer_DSubmit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECEN 4517 20
ADC10: The 10-Bit A/D Converterof the MSP430
Key features:• Multiplexed inputs• Sample and hold circuit• Successive approximation
register, driven by selectable clock
• Selectable reference sources
• Buffered output memory• 10 bit or 8 bit conversion
Divider/1 .. /8
:1:4:64
000110
10-bit ADC Core
VR- VR+
Convert
SampleandHold
S/H
0011 0110
1 0
0000000100100011010001010110011110001001101010111100110111101111
Sample Timer/4 .. /1024
1
0
1
0
Sync1
0
1
0
00
11
01
10
MODOSC from UCS
ACLK
MCLK
SMCLK
00
11
01
10
ADC10SC
3 inputsfrom Timers
Data Format
ADC10MEM
10-bit WindowComparator
VSS
Vcc
VREF 1.5 / 2.0 / 2.5 V from shared reference
ADC10SR
ADC10ON
ADC10SREFx
ADC10SREF2
Auto
ADC10CONSEQx
ADC10INCHx
A0A1A2A3A4A5A6A7
A15A14A13A12
TempSenseBatt.Monitor
VEREF+
VEREF-
ADC10DIVx
ADC10PDIVx
ADC10SSELx
ADC10BUSYADC10SHP
ADC10MSC
ADC10SHTx
SHI
ADC10ISSH
SAMPCON
ADC10MSC
ADC10HIx
ADC10LOx
ADC10DF
To Interrupt Logic
01
10
ADC10CLK
ReferenceBuffer
ADC10SHSx
A8A9
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com ADC10_A Introduction
A The MODOSC is part of the UCS. See the UCS chapter for more information.B When using ADC10SHP = 0 no synchronisation of the trigger input is done.
Figure 27-1. ADC10_A Block Diagram
697SLAU208L–June 2008–Revised January 2013 ADC10_ASubmit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECEN 4517 21
Successive Approximations
Reference: John H. Davies, MSP430 Microcontroller Basics, Elsevier, 2008, ISBN 987-7506-8276-3.
• After the input signal has been sampled, the 10-bit SAR requires 11 clock cycles to generate an output
• Compare analog input with references
• The MSP430 uses a switched capacitor scheme to perform the comparisons
• See MSP430x5xx Family User’s Guide, Ch. 27
ECEN 4517 22
Capacitor bypassing is required
What the User’s Guide recommends:
Also need capacitance at analog input pin
ECEN 4517 23
Setting up the A/D Converter ADC10
// Configure ADC10ADC10CTL0 = ADC10SHT_2 + ADC10ON; // sample time of 16 clocks, turn on
// use internal ADC 5 MHz clockADC10CTL1 = ADC10SHP + ADC10CONSEQ_0; // software trigger to start a sample
// single channel conversionADC10CTL2 = ADC10RES; // use full 10 bit resolutionADC10MCTL0 = ADC10SREF_1+ADC10INCH_5; // ADC10 ref: use VREF and AVSS
// input channel A5 (pin 10)// Configure internal reference VREFwhile(REFCTL0 & REFGENBUSY); // if ref gen is busy, waitREFCTL0 |= REFVSEL_0 + REFON; // select VREF = 1.5 V, turn on_delay_cycles(75); // delay for VREF to settle
The above code sets up the 10-bit ADC with A5 as its only input, with 1.5 V giving a reading of 210 – 1, and 0 V giving a reading of 0. Each reading will employ a sampling window of 16 ADC clocks = 3.2 µsec.
ECEN 4517 24
Sampling the ADC input
ADC10CTL0 |= ADC10ENC + ADC10SC; // sampling and conversion startwhile(ADC10CTL1 & ADC10BUSY); // wait for completionX = ADC10MEM0; // ADC10MEM0 contains result
The above code is simple and a good start. See CCS5 code examples for use of interrupts that do not require the processor to wait during the conversion time.
ECEN 4517 25
This Week’s Experiment 2
• Become familiar with MSP430
• Set up your MSP 430 to drive a MOSFET at a programmable duty cycle
• No prelab assignment
• Follow the Exp. 2 procedure on the Exp. 2 website. Demonstrate each result to your TA and get his initials on scoresheet. Turn in the Exp. 2 scoresheet, no report otherwise needed.