ECE614: Device Modelling and

Circuit Simulation

Unit 1 IC Fabrication Processing &

Wafer preparation

By Dr. Ghanshyam Singh

ObjectivesAfter studying the material in this unit, you will be able to:

1. Describe how raw silicon is refined into semiconductor grade silicon.

2. Explain the wafer fabrication method for producing monocrystal silicon.

3. Discuss the basic transistor behaviour.

4. Outline and describe the basic process steps for wafer preparation, starting from a silicon ingot and finishing with a wafer.

6. Explain what is Latch-up and how to avoid it in fabrication.

Topics

• Basic fabrication steps.

• Transistor structures.

• Basic transistor behavior.

• Latch up.

Wafers

• A wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed by doping (for example, diffusion or ion implantation, etching, and deposition of various materials.

• Wafers are cut out of silicon boules

• A boule is a single crystal silicone from which

wafers are cut using diamond saws.

Fabrication Process

• Once the wafers are prepared, many process steps are necessary to

produce the desired semiconductor integrated circuit. In general, the steps

can be grouped into four areas:

• •Front end processing (formation of transistors on silicon wafers)

• •Back end processing (interconnection of transistors by metal wires)

• •Test

• •Packaging

• In semiconductor device fabrication, the various processing steps fall into four

general categories: deposition, removal, patterning, and modification of electrical

properties.

Deposition

• Deposition is any process that grows, coats, or otherwise transfers a material onto

the wafer. Available technologies consist of physical vapor deposition (PVD),

chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular

beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among

others.

Removal or Etching Process

• Removal processes are any that remove material from the wafer either in

bulk or selective form and consist primarily of etch processes, both wet

etching and dry etching such as reactive ion etch (RIE). Chemical

mechanical planarization (CMP) is also a removal process used between

levels.

Masking and Patterning

• Patterning covers the series of processes that shape or alter the existing shape of

the deposited materials and is generally referred to as lithography. For example, in

conventional lithography, the wafer is coated with a chemical called a photoresist.

The photoresist is exposed by a stepper, a machine that focuses, aligns, and moves

the mask, exposing select portions of the wafer to short wavelength light. The

unexposed regions are washed away by a developer solution. After etching or

other processing, the remaining photoresist is removed by plasma ashing.

• Many modern chips have eight or more levels produced in over 300 sequenced processing

steps.

Fabrication processes

• IC built on silicon substrate (mono crystal silicone):

– some structures diffused into substrate;

– other structures built on top of substrate.

• Substrate regions are doped with n-type and p-type impurities. (n+,p+ =

heavily doped)

• When silicon is doped, n-type impurities (5-valence electron elements

such as arsenic) charge silicon atoms with electrons, p-type impurities (3-

valence electrons such as boron) charge them with holes

• Wires made of polycrystalline silicon (poly), and/or multiple layers of

aluminum (metal).

• Silicon dioxide (SiO2) is insulator. (is grown over Si by heating Si in a pure

oxygen or water vapor atmosphere)

Simple cross section

substrate

n+ n+p+

substrate

metal1

poly

SiO2(insulator)

metal2

metal3

transistorvia

Photolithography

Mask patterns are put on wafer using photo-

sensitive material:

A typical wafer is made out of extremely pure silicon that is

grown into mono-crystalline cylindrical ingots (boules) up to 12

in (300 mm) in diameter using the Czochralski process. These

ingots are then sliced into wafers about 0.75 mm thick and

polished to obtain a very regular and flat surface.

Process steps

First place tubs to provide properly-doped

substrate for n-type, p-type transistors: (Front-

end processing)

p-tub n-tub

substrate

Process steps, cont’d.

Pattern polysilicon before diffusion regions:

p-tub p-tub

poly polygate oxide

Process steps, cont’d

Add diffusions, performing self-masking:

p-tub p-tub

poly poly

n+n+ p+ p+

Process steps, cont’d

Start adding metal layers: (Backend processing)

p-tub n-tub

poly poly

n+n+ p+ p+

metal 1 metal 1

vias

Transistor structure

n-type transistor:

0.25 micron transistor (Bell Labs)

poly

silicide

source/drain

gate oxide

Transistor layout

n-type (tubs may vary):

w

L

Electrical Transistor Model

• Vgs: gate to source voltage

• Vds: drain to source voltage

• Ids: current flowing between drain and source

• k’: transconductance > 0

• Vt: threshold voltage > 0 for n-type <0 for p-type transistor.

• W/L: width to length ratio

Drain current characteristics

Drain current

• Linear region (Vds < Vgs - Vt):– Id = k’ (W/L)[(Vgs - Vt)Vds - 0.5 Vds

2]

– Not quite a linear relation between Id and Vds but the quadratic term becomes more negligible than the linear term as Vds approaches 0. This is typically the case with the absolute value of the threshold Vt voltage remaining close to 0.

• Saturation region (Vds >= Vgs - Vt):– Id = 0.5k’ (W/L)(Vgs - Vt)

2

– Id remains constant over changes in Vds

– Increases with transconductance, channel width, and decreases with channel length.

0.5 µm transconductances

From a MOSIS process:

• n-type:

– kn’ = 73 µA/V2

– Vtn = 0.7 V

• p-type:

– kp’ = 21 µA/V2

– Vtp = -0.8 V

Current through a transistor

(At saturation)

Example: Using 0.5 µm transconductance parameter of 73

µA/V2, threshold voltage of 0.7 volts, and SCMOS rules

(http://www.mosis.com/Technical/Designrules/scmos/scmos-

main.html)

with W 3λ, L = 2 λ:

• Saturation current at Vgs = 2V:

Id = 0.5k’(W/L)(Vgs-Vt)2= 93 µA

• Saturation current at Vgs = 5V:

Id = 1012 µA ~ 1 mA

Basic transistor parasitics

• There are myriad parasitics and parasitics models. The ones considered

here are the most widely-encountered parasitics.

• Gate to substrate, also gate to source/drain.

• Source/drain capacitance, resistance.

Cg

substrate

Basic transistor parasitics, cont’d

• Gate capacitance Cg. Determined by active area.

• Source/drain overlap capacitances Cgs, Cgd. Determined by source/gate and drain/gate overlaps. Independent of transistor L.

– Cgs = Col W (Col is the unit overlap capacitance per µm2, For small channel length, Col might indirectly depend on L.)

– Gate/bulk overlap capacitance.

Latch-up

• CMOS ICs have built-in undesirable parasitic

silicon-controlled rectifiers (SCRs).

• When powered up, SCRs can turn on, creating

low-resistance path from power to ground.

Current can destroy chip.

• Early CMOS problem. Can be solved with

proper circuit/layout structures.

Silicon Controlled Rectifier(SCR)

Tyristor Circuit

• In normal mode, no current flows over the pnpn path when the middle pn junction is reverse-biased. With the help of a gate pulse voltage, this pn junction can be forced into its breakdown region, making it conduct current. At that point, there will be a path of current from the anode to the cathode with no resistance even after the gate voltage is withdrawn. This is the basis for a high current from VDD to the ground (substrate) in MOS transistors, called the latch up.

QuickTime™ and aTIFF (Uncompressed) decompressor

are needed to see this picture.

p

p

n

n

anode

cathode

gate

FB

FB

RB

Parasitic SCR

circuit I-V behavior

V Reverse voltage

breakdown

Rs and Rw control the bias

voltage on the green

diodes

FB

Breakdown

FB

Parasitic SCR structure

n

pp

n

n

p

Solution: connect the n-tub to the VDD

When transistor on the right conducts, it turns on the

transistor on the left, and this in turn forces the first

transistor to draw more current, establishing a

positive feedback loop.

Solution to latch-up

Use tub ties to connect tub to power rail. Use

enough to create low-voltage connection.

Doping the tub at the

point of contact reduces

the resistance of

contact, and this makes

it more difficult for

bipolar transistor to

turn on.

Tub tie layout

metal (VDD)

n-tub

n+

You can learn more about latch up by downloading the article at http://www.fairchildsemi.com/an/AN/AN-339.pdf#search=%22latch%20up%20problem%22