STUCK-OPEN FAULT ANALYSIS IN CMOS TRANSISTOR BASED COMBINATIONAL CIRCUITS
Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults...
Transcript of Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults...
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Lecture 2 - Fault Modeling• Defects, Errors, and Faults• Some real defects in VLSI and PCB• Why model faults?• Common fault models• Stuck-at faults
• Single stuck-at faults• Fault equivalence• Fault dominance
• Other Common Faults• Faults in FPGAs
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Defects, Faults, and Errors• Defect: unintended difference between the
implemented HW and its intended design– May or may not cause a system failure
• Fault: representation of a defect at the abstracted function level
Defect X Fault
Imperfections in the HW Imperfections in the function
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Defects, Faults, and Errors• Error: Manifestation of a fault that results in
incorrect circuit (system) outputs or states– Caused by faults
• Failure: Deviation of a circuit or system from its specified behavior– Fails to do what it should do– Caused by an error
• Defect --> Fault ---> Error ---> Failure
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Some Real Defects in ChipsProcessing defects
Missing contact windowsParasitic transistorsOxide breakdown. . .
Material defectsBulk defects (cracks, crystal imperfections)Surface impurities (ion migration). . .
Time-dependent defectsDielectric breakdownElectromigration. . .
Packaging defectsContact degradationSeal leaks. . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -Semiconductor Devices and Circuits, Wiley, 1981.
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Example
• Processing defect: a short of b to ground
• Fault: signal b stuck-at logic 0
• Error: z has the wrong value if a = b = 1
a
b
11
z 0 1
0
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Example
• Defect: a short to ground
• Fault: signal b stuck at logic 0
• Error: z has the wrong value if a = b = 1
• But, if a = 0, fault exists, but no error!
a
b
01
z 1 1
0
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Why Model Faults?• Real defects too numerous and often not analyzable
• A fault model identifies targets for testing– Model faults most likely to occur
• Fault model limits the scope of test generation – Create tests only for the modeled faults
• A fault model makes analysis possible– Associate specific defects with specific test patterns
• Effectiveness measurable by experiments– Fault coverage can be computed for specific test patterns
to reflect its effectiveness
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Common Fault Models• Single stuck-at faults
• Transistor open and short faults
• Memory faults
• Functional faults (processors)
• Delay faults (transition, path)
• Analog faults (parametric deviations)
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Single Stuck-at Fault• Three properties define a single stuck-at fault
• Only one line is faulty• The faulty line is permanently set to 0 or 1• The fault can be at an input or output of a gate
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Single Stuck-at Fault• Three properties define a single stuck-at fault
• Only one line is faulty• The faulty line is permanently set to 0 or 1• The fault can be at an input or output of a gate
• Example: NAND gate has 3 fault sites ( ) and 6 single stuck-at faults
a
b
11
z
s-a-0 fault, s-a-1 fault
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Single Stuck-at Fault• Three properties define a single stuck-at fault
• Only one line is faulty• The faulty line is permanently set to 0 or 1• The fault can be at an input or output of a gate
• Example: NAND gate has 3 fault sites ( ) and 6 single stuck-at faults
a
b
11
z 1 (0)
1
Faulty circuit valueGood circuit value
s-a-0
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Single Stuck-at Fault• Three properties define a single stuck-at fault
• Only one line is faulty• The faulty line is permanently set to 0 or 1• The fault can be at an input or output of a gate
• Example: NAND gate has 3 fault sites ( ) and 6 single stuck-at faults
a
b
11
z 1 (0)
1
Test vector for a s-a-0 fault
Faulty circuit valueGood circuit value
s-a-0
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Single Stuck-at Fault
a
b
c
d
e
f
10
g h i 1
j
k
z
01
1
Good circuit value
Example: XOR circuit has 12 fault sites and 24 single stuck-at faults
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Single Stuck-at Fault
a
b
c
d
e
f
10
g h i 1
s-a-0j
k
z
0(1)1(0)
1
Test vector for h s-a-0 fault
Good circuit valueFaulty circuit value
Example: XOR circuit has 12 fault sites and 24 single stuck-at faults
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Fault Equivalence• Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also detect f2.
• If faults f1 and f2 are equivalent then the corresponding faulty functions are identical.
• Fault collapsing: All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
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Equivalence Rules
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0
sa1
sa0sa0sa1
sa1
sa0sa1
AND
NAND
OR
NOR
WIRE
NOT
FANOUT
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Equivalence Rules
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0
sa1
sa0sa1
sa0sa0sa1
sa1
sa0
sa0
sa0sa1
sa1
sa1
AND
NAND
OR
NOR
WIRE
NOT
FANOUT
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Equivalence Examplesa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1sa0 sa1
sa0 sa1
![Page 19: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/19.jpg)
Equivalence Example
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1sa0 sa1
sa0 sa1
sa0 sa1sa0 sa1
sa0 sa1
sa0 sa1sa0 sa1
sa0 sa1
sa0 sa1sa0 sa1
sa0 sa1 16Collapse ratio = ----- = 0.533
30
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Equivalence Example
sa0 sa1sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
![Page 21: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/21.jpg)
Equivalence Example
sa0 sa1sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
Faults in redremoved byequivalencecollapsing
20Collapse ratio = ----- = 0.625
32
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Fault Dominance
• If all tests of some fault F1 detect another fault F2, then F2 is said to dominate F1.
• Dominance fault collapsing: If fault F2 dominates F1, then F2 is removed from the fault list.
![Page 23: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/23.jpg)
Dominance Example
s-a-1F1
s-a-1F2
![Page 24: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/24.jpg)
Dominance Example
s-a-1F1
s-a-1F2 001
110 010000
101100
011
All tests of F2
Only test of F1
![Page 25: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/25.jpg)
Dominance Example
s-a-1F1
s-a-1F2 001
110 010000
101100
011
All tests of F2
Only test of F1s-a-1
s-a-1
s-a-1 s-a-0
A dominance collapsed fault set
![Page 26: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/26.jpg)
Dominance Example
sa1
sa1
sa0 sa1
sa0sa1
sa1
sa0sa1
sa1
sa0sa1
sa1
sa0sa1
sa1
![Page 27: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/27.jpg)
Dominance Example
sa1
sa1
sa0 sa1
sa0sa1
sa1
sa0sa1
sa1
sa0sa1
sa1
sa0sa1
sa1 15Collapse ratio = ----- = 0.5
30
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Dominance Example
sa0sa1
sa0 sa1
sa1
sa1
sa1
sa0 sa1
sa1
sa1
sa0 sa1
sa0
sa0
sa0
sa1
sa1
sa0 sa1
![Page 29: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/29.jpg)
Dominance Example
sa0sa1
sa0 sa1
sa1
sa1
sa1
sa0 sa1
sa1
sa1
sa0 sa1
sa0
sa0
sa0
sa1
sa1
sa0 sa1
Faults in redremoved bydominancecollapsing
18Collapse ratio = ----- = 0.5625
32
![Page 30: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/30.jpg)
Bridging Faults• Two or more normally distinct points (lines) are
shorted together– Logic effect depends on technology– Wired- AND for TTL
– Wired- OR for ECL
– CMOS?
![Page 31: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/31.jpg)
CMOS Transistor Stuck- Short
• Transistor stuck- on may cause ambiguous logic level– depends on the relative impedances of the pull- up & pull-
down networks
• When input is low, both P and N transistors are conducting causing increased quiescent current, called IDDQ fault.
![Page 32: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/32.jpg)
CMOS Transistor Stuck- OPEN
• Transistor stuck- open may cause output floating.
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Functional Faults• Fault effects modeled at a higher level than
logic for function modules, such as– Decoders – Multiplexers – Adders – Counters – RAMs– ROMs
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Functional Faults of Decoder
• f( L i /L j ): Instead of line L i , Line L j is selected
• f( L i /L i +L j ): In addition to L i , L j is selected
• f( L i /0): None of the lines are selected
![Page 35: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/35.jpg)
Memory Faults
• Pattern- sensitive faults: the presence of a faulty signal depends on the signal values of the nearby points – Most common in DRAMs
• Adjacent cell coupling faults – Pattern sensitivity between a pair of cells
![Page 36: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/36.jpg)
Gate- Delay- Fault
• Slow to rise, slow to fall – x is slow to rise when channel resistance R1 is
abnormally high
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Path- Delay- Fault
• Propagation delay of the path exceeds the clock interval.
• The number of paths grows exponentially with the number of gates.
![Page 38: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/38.jpg)
Faults in FPGAs
ffF1F2F3F4
Configuration Memory CellM
M
M M M M M MLUT
BlockRAM
SEU(Bit flip)
clk
clk
E1E2E3
E1E2E1E3E2E3
Permanent faults: same ASIC models apply
But for transients ...
Virtex (Xilinx)
FPGA building blocks:
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Effect of Transients in SRAM-based FPGAs
ffF1F2F3F4
Configuration Memory CellM
M
M M M M M MLUT
BlockRAM
SEU(Bit flip)
clk
clk
E1E2E3
E1E2E1E3E2E3
Possible Bit flipTransient effectCorrected at the next load
Virtex (Xilinx)
CLB Comb. Logic:~0.5 % of the FPGA sensitive area
![Page 40: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/40.jpg)
Effect of Transients in SRAM-based FPGAs
ffF1F2F3F4
Configuration Memory CellM
M
M M M M M MLUT
BlockRAM
SEU(Bit flip)
clk
clk
E1E2E3
E1E2E1E3E2E3
Bit flipTransient effectCorrected at the next load
Virtex (Xilinx)
CLB Flip-flops:~0.5 % of the FPGA sensitive area
![Page 41: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/41.jpg)
Effect of Transients in SRAM-based FPGAs
ffF1F2F3F4
Configuration Memory CellM
M
M M M M M MLUT
BlockRAM
SEU(Bit flip)
clk
clk
E1E2E3
E1E2E1E3E2E3
Bit flipPermanent effectCorrected by
reconfiguration
Virtex (Xilinx)
CLB LUTs:~8% of the FPGA sensitive area
![Page 42: Lecture 2 - Fault Modelingfglima/projeto/aula2t.pdf · • Common fault models • Stuck-at faults • Single stuck-at faults • Fault equivalence • Fault dominance ... Functional](https://reader033.fdocuments.net/reader033/viewer/2022052302/5ab956637f8b9aa6018dbdd3/html5/thumbnails/42.jpg)
Effect of Transients in SRAM-based FPGAs
ffF1F2F3F4
Configuration Memory CellM
M
M M M M M MLUT
BlockRAM
SEU(Bit flip)
clk
clk
E1E2E3
E1E2E1E3E2E3
Virtex (Xilinx)
Short or open circuitCorrected by reconfiguration
Routing and CLB customization:~91.0 % of the FPGA sensitive area
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Summary
• Fault models are analyzable approximations of defects and are essential for a test methodology.
• For digital logic single stuck-at fault model offers best advantage of tools and experience.
• Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests.
• Memory and analog circuits need other specialized fault models and tests.
• Transient faults may have permanent effects in FPGAs