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Lecture 19: Clock Distribution

•  Clock distribution trends •  Distribution networks •  Clock Power •  Clock Skew •  Timing Definitions

•  Source: Ch 7 –  J. Rabaey notes, Weste and Harris Notes, S. Russu, ISSCC,

Clocking

•  Synchronous systems use a clock to keep operations in sequence –  Distinguish this from previous or next –  Determine speed at which machine operates

•  Clock must be distributed to all the sequencing elements –  Flip-flops and latches –  Domino circuits and memories

•  On practical chips, the RC delay of the wire resistance and gate load is very long –  Variations in this delay cause clock to get to different elements at

different times –  This is called clock skew

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Clock definition and parameters

•  Skew –  Spatial variation of the clock

signal as distributed throughout the chip

–  Global vs. local skew •  Clock Jitter

–  Temporal variation of the clock with respect to a reference edge

•  Duty Cycle Variation –  50/50 Design target

The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems

[S. Russu. SoC 2004]

Clock Distribution Trends

[S. Russu. SoC 2004]

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Clock Distribution Networks

Recall: Buffer Sizing •  Recall Example: drive 64-bit datapath with unit inverter

•  N= •  F= •  f=

1 1 1 1

8 4

16 8

2.8

23

64 64 64 64

Initial Driver

Datapath Load

N:f:D:

16465

2818

3415

42.815.3

Fastest

1 2 N

1 f fN

N Ff =

CL CIN

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Example: DEC Alpha 21164 Clocking

•  300MHz, 9M transistors •  2 distributed driver channels

–  3.75nF clock load –  58 cm final driver width –  20Watts (out of 50W)

trise = 0.35ns tskew = 150ps

tcycle= 3.3ns

Clock waveform

Location of clock driver on die

pre-driver

final drivers

Clock Drivers

Alpha Processors

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3D Skew Visualization

Del

ay (p

s)

A B

3D Skew Visualization

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Clock power breakdown example •  30% of power dissipation in clock network •  Most of the power is in the final clock buffers, grid and flip-flops

A B

Review: Timing Definitions

t CLK

t D

t c 2 q

t hold t su

t Q DATA

STABLE

DATA STABLE

Register

CLK

D Q

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Review: Timing Definitions

•  TCQ:

•  Tsetup (U):

•  Thold:

•  Tskew:

Clock Skew

•  Global – long path error –  Data is launched at point A and

received at point C

A B

C

TSKEW

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Clock Skew

•  Local – short path error –  Data is launched at point A and

received at point B

A B

C

TSKEW

Summary

•  Clock distribution networks •  Clock skew and jitter •  Timing definitions