Operating Systems

Lecture 16

Memory Management

June 03, 2013http://web.uettaxila.edu.pk/CMS/SP2013/seOSbs/

Agenda for Today

• Implementation of page table • Performance of paging and protection• Structure of page table • Shared pages • Segmentation • Segmentation architecture• Sharing of Segments • Paged Segmentation

Address Translation

f

Paging Example

Page size = 4 bytes

Process address space = 4 pages

Physical address space = 8 frames

Logical address: (1,3)

= 0111

Physical address: (6,3)

= 11011

0

1

2

3

Page Frame

11011

0111

Addressing in Paging

Logical address space of 16 pages of 1024 words each, mapped into a physical memory of 32 frames.Logical address size?Physical address size?Number of bits for p, f, and d?

Addressing in Paging

No. of bits for p = 4 bitsNo. of bits for f = 5 bitsNo. of bits for d = 11 bits

Addressing in Paging

Logical address size = |p| + |d|= 4+11= 15 bits

Physical address size = |f| + |d|= 5+11= 16 bits

Page Table Size

Page table size = NP * PTES where NP is the number of pages in the process address space and PTES is the page table entry size (equal to |f| based on our discussion so far). Page table size = 16 * 5 bits

= 16 bytes

Another Example

Logical address = 32-bitProcess address space = 232 B

= 4 GBMain memory = RAM = 512 MBPage size = 4KMaximum pages in a process address space = 232 / 4K

= 1M

Another Example

|d| = 12 bits|p| = 32 – 12 = 20 bitsNo. of frames = 512 M / 4 K

= 128 K|f| = 17 bits

Physical address = 17+12 bits

Implementation of Page Table

In CPU registersOK for small process address spaces and large page sizesEffective memory access time (Teffective) is about the same as memory access time (Tmem)

Implementation of Page Table

Keep page table in the main memory

Page table base register (PTBR)

Teffective = 2Tmem

Teffective is not acceptable

Implementation of Page Table

Use a special, small, fast lookup hardware, called translation look-aside buffer (TLB) Typically 64–1024 entriesAn entry is (key, value)Parallel search for key; on a hit, value is returned

Implementation of Page Table

(key,value) is (p,f) for pagingFor a logical address, (p,d), TLB is searched for p. If an entry with a key p is found, we have a hit and f is used to form the physical address. Else, page table in the main memory is searched.

TLB

Logical address: (p, d)

p

f

Implementation of Page Table

The TLB is loaded with the (p,f) pair so that future references to p are found in the TLB, resulting in improved hit ratio.On a context switch, the TLB is flushed and is loaded with values for the scheduled process.

Paging Hardware

Performance of Paging

Teffective on a hit = Tmem + TTLB

Teffective on a miss = 2Tmem + TTLB

If HR is hit ratio and MR is miss ratio, then

Teffective = HR (TTLB + Tmem) + MR (TTLB + 2Tmem)

Example

Tmem = 100 nsecTTLB = 20 nsecHit ratio is 80%Teffective = ?

Teffective = 0.8 (20 + 100) + 0.2 (20 + 2x100)= 140 nanoseconds

Example

Tmem = 100 nsecTTLB = 20 nsecHit ratio is 98%Teffective = ?

Teffective = 0.98 (20 + 100) + 0.02 (20 + 2x100)= 122 nanoseconds

Structure of the Page Table

Hierarchical / Multilevel PagingInverted Page Table

Multilevel Paging

Logical address = 32-bit

Page size = 4K bytes (212 bytes)

Page table entry = 4 bytes

Maximum pages in a process address space = 232 / 4K = 1M

Multilevel Paging

Maximum pages in a process address space = 232 / 4K = 1M

Page table size = 4M bytes

This page cannot fit in one page ⇒ Page the page table

Multilevel Paging

Page table needed for keeping track of pages of the page table—called the outer page table or page directoryNo. of pages in the page table is 4M / 4K = 1KSize of the outer page table is 1K * 4 bytes = 4K bytes ⇒ outer page will fit in one page

Multilevel Paging

2-level paging

Multilevel Paging

Addressing and address translation32-bit logical address: p1 used to index the outer page table and p2 to index the inner page table

page number page offset

p1 p2 d

10 10 12

Multilevel Paging

p1{

p2{

Multilevel Paging

Inverted Page Table

One entry per real page in memory Page table size is limited by the number of frames (i.e., the physical memory) and not process address spaceEach entry in the page table contains (pid, p)

Inverted Page Table

If a page ‘p’ for a process is loaded in frame ‘f’, its entry is stored at index ‘f’ in the page tableWe effectively index the page table with frame number; hence the name inverted page table

Inverted Page Table

Frame Number

Shared Pages

• Reentrant (read-only) code pages of a process address space can be shared

• Shared code appears in the same logical address space of all processes

• Multiple invocations of pico or gcc

Shared Pages

Segmentation

A memory management scheme that supports programmer’s view of memory. A segment is a logical unit such as: main program, procedure, function, method, object, global variables, stack, symbol tableA program is a collection of segments

Segmentation

Segmentation

1

3

2

4

logical memory physical memory

5

Segmentation

1

3

2

4

1

4

2

3

logical memory physical memory

1

4

2

35

5

Segmentation

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2

4

1

4

2

3

logical memory physical memory

1

4

2

35

5

segment table

Segmentation

Logical address consists of a two tuple:<segment-number, offset>

Segment table – maps two-dimensional logical addresses to physical addresses

Segmentation

Each segment table entry has:base – contains the starting physical address where the segments reside in memory.limit – specifies the length of the segment.

Segmentation

Segment-table base register (STBR) points to the segment table’s location in memory.Segment-table length register (STLR) indicates number of segments used by a programSegment number s is legal if s < STLR

Segmentation

CPU

Segmentation Architecture

RelocationDynamicBy segment table

SharingShared segmentsSame segment number

Segmentation Architecture

Dynamic Storage AllocationFirst fitBest fitWorst fit

External fragmentation

Example

Address Translation

Logical and Physical Addresses(2, 399) – PA: 4300+399 = 4699(4, 0) – PA: 4700+0 = 4700(4, 1000) ⇒ trap (3, 1300) ⇒ trap (6, 297) ⇒ trap

Sharing of Segments

Sharing at the segment level and not at the fixed-size page levelSharing at the code or data levelSegment table of multiple processes point to the same segment

Sharing of Segments

Issues with Segmentation

External FragmentationTotal memory space exists to satisfy a space allocation request for a segment, but memory space is not contiguous.

Reduce external fragmentation by compactionShuffle segments to place free memory together in one block.Compaction is possible only if relocation is dynamic, and is done at execution time.

Issues with Segmentation

I/O problemLatch job in memory while it is involved in I/O.Do I/O only into OS buffers

Very large segments ⇒ page program segments—paged segmentation

Issues with Segmentation

Protection

Associate valid/invalid bit with each segment table entry to indicate if the referenced segment is part of the process address space or not Read, write, and execute bits to define legal operations on a segment

Paged Segmentation

Divide every segment in a process into fixed size pagesNeed for a page table per segmentCPU’s memory management unit must support both segmentation and paging

Paged Segmentation

1

3

2

4

logical memory

5

physical memory

Paged Segmentation

1

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2

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logical memory

5

physical memory

1

2

0

3

0123...

10

126 127

31

12610

page table

Paged Segmentation

Logical address is still <s,d>, with s used to index the segment tableEach segment table entry consist of the tuple

<segment-length, page-table-base>The logical address is legal if

d < segment-length

Paged Segmentation

Segment offset, d, is partitioned into two parts: p and d’, where p is used to index the page table associated with segment, s, and d’ is used as offset within a page

Paged Segmentation

p indexes the page table to retrieve frame, f, and physical address (f,d’) is formed

s d

p d’

index segment

tableindex page

tableoffset within the

page p

Paged Segmentation

MULTICS Example

GE 345 processorLogical address = 34 bits Page size = 1 KBs is 18 bits and d is 16 bitsSize of p and d’, largest segment size, and max. number of segments per process?

MULTICS Example

Largest segment = 2d bytes= 216 bytes

Maximum number of pages per segment = 216 / 1 K = 64|p| = log2 64 bits = 6 bits|d’| = log2 1 K = 10 bitsMaximum number of segments per process = 2s = 218

MULTICS Example

s d

p d’18 bits

6 bits 10 bits