Lecture 14: Introduction to Algorithmic State Machines...

Aritmética Computacional 2007 Unidad de Control

Control Unit

Arturo Díaz-PérezDepartamento de Computación

Laboratorio de Tecnologías de InformaciónCINVESTAV-IPN

2Aritmética Computacional 2007 Unidad de Control

Large Digital SystemsIn both combinational and sequential circuit design:

small circuits via gate-level design (truth tables, K maps, etc)large circuits via block-level design (MSI components, etc.)

However, larger digital systems need more abstract and systematic design techniques.One such systematic design method has the following characteristics:

top-down approachseparation of controller from controlled hardwaredevelop an overall architecture (at block levels) before proceeding into the details of hardware.


Top-Down ApproachTop-down approach is immensely important for large complex system (whether hardware, software, or manual systems).Emphasis on macroscopic view, starting from original problem and gradually refine it towards solution.Steps for a top-down design procedure:

Specify the problem clearly (at global/top level without unnecessary details).Break the problem into smaller sub-problems.Repeat the process until subproblems are small enough to be solved directly (implementable).


Controller & Data ProcessorDigital systems are typically processors of information.

They store data through flip-flops, registers and memory, and process them using combinational circuits like adders, multipliers, etc.These processing may pass through complicated sequences.

A digital system consists of two componentsA control algorithm (controller) andAn architecture (data processor)

Control unit (Controller)

Data Processor

(Architecture)

Commands

Input data

External command

Status condition

Output data


Controller & Data ProcessorSeparation of the controller operations from the data processing operations

Control operations give commands that direct the data processing operations to accomplish the desired tasks.Data processing operations manipulates the data according to requirements.

A mechanical analogy: Automobile.Car (data processor): transports people from one location to another.Driver (controller): gives instructions to car to achieve objective.


Flowcharts

Flowcharts: a tool for precise description of algorithms/procedures.

Specify tasks to perform and their sequencing.

Main symbols:Operation box: contains tasks/operations to perform.Decision box: alternative actions based on decisions to be taken.Arrows: indicate appropriate sequencing.


Flowcharts

Flowcharts can be used to implement complex decisions.

get BF to buy

nice colour & style?

yes

no

reject

test out

affordable?

made in Europe?

yes

yesno

fitting?

BF’s opinion?

accep-table

poor

encouraging

insulting

no


ASM ChartsAlgorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems.Major differences from flowcharts are:

uses 3 types of boxes: state box (similar to operation box), decision box and conditional boxcontains exact (or precise) timing information; flowcharts impose a relative timing order for the operations.

From the ASM chart it is possible to obtainthe controlthe architecture (data processor)


Components of ASM Charts

The state box is rectangular in shape. It has at most one entry point and one exit point and is used to specify one or more operations which could be simultaneously completed in one clock cycle.

one or more operations

statebinary code


Components of ASM Charts

The decision box is diamond in shape. It has one entry point but multiple exit points and is used to specify a number of alternative paths that can be followed.

deciding factors

deciding factors


Components of ASM ChartsThe conditional box is represented by a rectangle with rounded corners. It always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box.

conditional operations


ASM Charts: An ExampleInitial state

S

A ← 0F ← 0

A ← A + 1

A2

E ← 0 E ← 1

A3

F ← 1

0

0

0

1

1

1

T2

T1

T0

An example:

A is a register; Ai stands for ith bit of the A register.

A = A4A3A2A1

E and F are single-bit flip-flops.


Register OperationsRegisters are present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers.The register operations are specified in either the state and/or conditional boxes, and are written in the form:

destination register ← function(other registers)where the LHS contains a destination register (or part of one) and the RHS is some function over one or more of the available registers.


Register Operations

Examples of register operations:A ← B Transfer contents of

register B into register A.A ← 0 Clear register A.A ← A − 1 Decrement register A by

1.


Timing in ASM Charts

Precise timing is implicitly present in ASM charts.Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle.A group of boxes which occur within a single clock cycle is called an ASM block.



3 ASM blocks

Initial state

S

A ← 0F ← 0

A ← A + 1

A2

E ← 0 E ← 1

A3

F ← 1

0

0

0

1

1

1

T2

T1

T0



Operations of ASM can be illustrated through a timing diagram.Two factors which must be considered are

operations in an ASM block occur at the same time in one clock cycledecision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block)



clock 1 2 3 4 5 6 7 8 9 10 11 12 13states T0 T0 T1 T1 T1 T1 T1 T1 T1 T2 T0 T0 T0

input S=0 S=1 S=0

registervalues

A=0F=0

A=1

E=0

A=2

E=0

A=3

E=1

A=4

E=1

A=5

E=0

A=6

E=0

A=7

E=1F=1

OperationsA←0F←0

A←A+1E←0

A←A+1E←0

A←A+1E←1

A←A+1E←1

A←A+1E←0

A←A+1E←0

A←A+1E←1

F←1

A = A4A3A2A1


Timing in ASM Chartsclock 1 2 3 4 5 6states T0 T0 T1 T1 T1 T1

input S=0 S=1 S=0

registervalues

A=0F=0

A=1

E=0

A=2

E=0

A=3

E=1

OperationsA←0F←0

A←A+1E←0

A←A+1E←0

A←A+1E←1

A←A+1E←1

A←A+1E←0

A←A+1E←0

A←A+1E←1

F←1

clock 7 8 9 10 11 12 13states T1 T1 T1 T2 T0 T0 T0

input

registervalues

A=4

E=1

A=5

E=0

A=6

E=0

A=7

E=1F=1

OperationsA = A4A3A2A1

Initial state

S

A ← 0F ← 0

A ← A + 1

A2

E ← 0 E ← 1

A3

F ← 1

0

0

0

1

1

1

T2

T1

T0


ASM Chart => Digital System

ASM chart describes a digital system. From ASM chart, we may obtain:

Controller logic (via State Table/Diagram)Architecture/Data Processor

Design of controller is determined from the decision boxes and the required state transitions.Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes.


ASM Chart => Controller

Procedure:Step 1: Identify all states and assign suitable codes.Step 2: Draw state diagram.Step 3: Formulate state table using

State from state boxesInputs from decision boxesOutputs from operations of state/conditional boxes.

Step 4: Obtain state/output equations and draw circuit.


ASM Chart => Controller

Initial state

S

A ← 0F ← 0

A ← A + 1

A2

E ← 0 E ← 1

A3

F ← 1

0

0

0

1

1

1

T2

T1

T0 T0

T1

T2

Assign codes to states:

T0 = 00T1 = 01T2 = 11

Presentstate inputs

Nextstate outputs

G1 G0 S A2 A3 G1+ G0

+ T0 T1 T2

0 0 0 X X 0 0 1 0 00 0 1 X X 0 1 1 0 00 1 X 0 X 0 1 0 1 00 1 X 1 0 0 1 0 1 00 1 X 1 1 1 1 0 1 01 1 X X X 0 0 0 0 1

Inputs from conditions in decision boxes. Outputs = present state of controller.


ASM Chart => Architecture/Data Processor

Architecture is more difficult to design than controller.Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine:

What registers to useHow they can be connectedWhat operations to supportHow these operations are activated.

Guidelines:always use high-level unitssimplest architecture possible.



Various operations are:Counter incremented (A ← A + 1) when state = T1.Counter cleared (A ← 0) when state = T0 and S = 1.E is set (E ← 1) when state = T1 and A2 = 1.E is cleared (E ← 0) when state = T1 and A2 = 0.F is set (F ← 1) when state = T2.

Deduce:One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment).Two flip-flops needed for E and F (e.g.: JK flip-flops).



Controller

K

J Q

K

J Q

Clk

4-bit syn. counter A

A2

A1A2

A3

A3A4

start S

E

F

clock

CPcount

clear

T2

T1

T0

(A ← A + 1) when state = T1.(A ← 0) when state = T0 and S = 1.(E ← 1) when state = T1 and A2 = 1.


Implementing the ControllerOnce the state table is obtained, the controller can be implemented using one of these techniques.1. Traditional method: With JK flip-flops.

design done at gate level.suitable for small controllers.procedure: prepare state table, use K-maps to obtain next-state/output functions.

2. Decoder + D flip-flopssuitable for moderately large controllers.procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection.


Implementing the Controller

3. Multiplexersa more structured approach to implement controller.suitable for moderately large controllers.three level structure:

first level consists of multiplexers that determine the next state of the register; second level is a register that holds the present state; third level has a decoder to provide separate output for each controller state.


Implementing the Controller4. One flip-flop per state

also known as One-Hot Spot Method of ASM synthesis.procedure: allocate one flip-flop per state; from state table, determine the formulae to set each flip-flop; must ensure that controller is properly initialised.

5. PLA/ROMhighly regular approach.ROM approach uses a very simple table lookup technique but suffers from large number of don’t care states.PLA can handle don’t care states well but design method is still at gate-level.


Implementing Controller:With JK Flip-flops

State table obtained from ASM chart:

Presentstate inputs

Nextstate outputs

G1 G0 S A2 A3 G1+ G0

+ T0 T1 T2

0 0 0 X X 0 0 1 0 00 0 1 X X 0 1 1 0 00 1 X 0 X 0 1 0 1 00 1 X 1 0 0 1 0 1 00 1 X 1 1 1 1 0 1 01 1 X X X 0 0 0 0 1

Presentstate inputs

Nextstate

Flip-flopinputs

G1 G0 S A2 A3 G1+ G0

+ JG1 KG1 JG0 KG0

0 0 0 X X 0 0 0 X 0 X0 0 1 X X 0 1 0 X 1 X0 1 X 0 X 0 1 0 X X 00 1 X 1 0 0 1 0 X X 00 1 X 1 1 1 1 1 X X 01 1 X X X 0 0 X 1 X 1

Corresponding state table using JK flip-flops:


Implementing Controller:Decoder + D Flip-flops

The flip-flop input functions can be obtained directly from the state table by inspection.This is because for the D flip-flops, the next state = flip-flop D input.Decoder is then used to provide signals to represent different states.

D Q

D Q

2x4 decoder

T0

T1

T2

unused

G1

G0

?

?

clock



Given the state table: Presentstate inputs

Nextstate outputs

G1 G0 S A2 A3 G1+ G0

+ T0 T1 T2

0 0 0 X X 0 0 1 0 00 0 1 X X 0 1 1 0 00 1 X 0 X 0 1 0 1 00 1 X 1 0 0 1 0 1 00 1 X 1 1 1 1 0 1 01 1 X X X 0 0 0 0 1

We can directly determine the inputs of the D flip-flops for G1 and G0.

DG1 = T1.A2.A3

DG0 = T0.S + T1



Flip-flop input functions:DG1 = T1.A2.A3 DG0 = T0.S + T1

Circuit:

D Q

D Q

2x4 decoder

T0

T1

T2

unused

G1

G0

clock

A2

A3

S


Implementing Controller:One Flip-flop per State

Require n flip-flops for n states; each flip-flop represents one state. (Other methods: n flip-flops for up to 2n states.)

D Q

D Q T1

T0?

?

clock

::



Formulae for next state can be obtained directly from state table:

1. If there is only one line going into the state, then formula = input condition ANDed with the previous state.

2. If there are more than one line, then formula = Ored of all the conditions found in (1)



State diagram:State table:Present

state inputsNextstate

S A2 A3

T0 0 X X T0

T0 1 X X T1

T1 X 0 X T1

T1 X 1 0 T1

T1 X 1 1 T2

T2 X X X T0

T0

S=0 A2=0

T1

S=1

A2=1, A3=0

T2

A2=1, A3=1

Flip-flop input functions:DT0 = T2 + S'.T0

DT1 = S.T0 + A2'.T1 + A2.A3'.T1 = S.T0 + (A2.A3)'.T1

DT2 = A2.A3.T1



Circuit diagram below. To initialized to state T0, set flip-flop of T0 to 1 and clear the rest to zero.

DT0 = T2 + S'.T0

DT1 = S.T0 + (A2.A3)'.T1

DT2 = A2.A3.T1

D Q

T1

T0S

clock

D Q

D Q T2A2A3

clear

preset


Implementing Controller:One Flip-flop per StateAlternative: Use Q' output for T0, and input function for T0 is complemented. To initialise, clear all flip-flops to zero.

DT0 = (T2 + S'.T0)'DT1 = S.T0 + (A2.A3)'.T1

DT2 = A2.A3.T1

D Q

T1

T0

S

clock

D Q

D Q T2A2A3

clear

Q'


Implementing Controller: Multiplexers

Purpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state.

The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart.


Implementing Controller: MultiplexersExample 1: Given the state table.

Presentstate inputs

Nextstate

G1 G0 S A2 A3 G1+ G0

+

0 0 0 X X 0 00 0 1 X X 0 10 1 X 0 X 0 10 1 X 1 0 0 10 1 X 1 1 1 11 1 X X X 0 0

Reformat the state table.

Presentstate

Nextstate

Multiplexerinputs

G1 G0 G1+ G0

+Input

conditions MUX1 MUX00 0 0 0 S'0 0 0 1 S ? ?

0 1 0 1 A2'0 1 0 1 A2. A3'0 1 1 1 A2. A3

? ?

1 1 0 0 1 ? ?



Obtain multiplexer inputs:

Presentstate

Nextstate

Multiplexerinputs

G1 G0 G1+ G0

+Input

conditions MUX1 MUX00 0 0 0 S'0 0 0 1 S 0 S

0 1 0 1 A2'0 1 0 1 A2. A3'0 1 1 1 A2. A3

A2. A3 A2' + A2. A3' + A2. A3= 1

1 1 0 0 1 0 0



Draw circuit:Present

stateMultiplexer

inputsG1 G0 MUX1 MUX0

T0 0 0 0 ST1 0 1 A2. A3 1T2 1 1 0 0

T1

T0

S

clock

D Q

D Q T2

A2A3

2x4 decoder

G1

G0

MUX10123 S1 S0

MUX00123

S1 S0

0

0

0

1

Determine next state of register

Hold present state


Implementing Controller: MultiplexersExample 2:

w 01

T0 00

T1 01

x 10

T3 11 T2 10

y 10 y 01

z 10 z 01

Presentstate

Nextstate

G1 G0 G1+ G0

+Input

conditions

0 0 0 0 w'0 0 0 1 w0 1 1 0 x0 1 1 1 x'1 0 0 0 y'1 0 1 0 y.z'1 0 1 1 y.z1 1 0 1 y'.z1 1 1 0 y1 1 1 1 y'.z'

Presentstate

Multiplexerinputs

G1 G0 MUX1 MUX0T0 0 0 0 wT1 0 1 x+x'=1 x'T2 1 0 y.z' + y.z

= yy.z

T3 1 1 y + y'.z'= y + z'

y'.z +y'.z' = y'



Presentstate

Multiplexerinputs

G1 G0 MUX1 MUX0T0 0 0 0 wT1 0 1 1 x'T2 1 0 y y.zT3 1 1 y + z' y'

T1

T0

w

clock

D Q

D Q T3

yz

2x4 decoder

G1

G0

MUX10123 S1 S0

MUX00123

S1 S0

y'

y

0

x'

1yz'

T2


Implementing Controller: PLA/ROM

Similar to the design using D flip-flops and a decoder.

The only difference is PLA essentially replaces the decoder and all the gates in the inputs of the flip-flops.

PLA/ROMExternal command

Commands to architecture

Present state

Next state

Register to represent states

Lecture 14: Introduction to Algorithmic State Machines...

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